WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/arch.h>
#include <arch/regdef.h>
#include <arch/boot/boot.h>
#include <arch/stack.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
#ifdef CONFIG_SMP
#include <arch/context_offset.h>
#endif
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
/*
 * Here is where the kernel is passed control
 * from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 non-zero for the bootstrap processor, zero for application/secondary processors
 * - %o1 bootinfo structure address
 * - %o2 bootinfo structure size
 *
 * Moreover, we depend on boot having established the
 * following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 
 */
 
.global kernel_image_start
kernel_image_start:
	mov %o0, %l7
 
	/*
	 * Setup basic runtime environment.
	 */
 
	wrpr %g0, NWINDOWS - 2, %cansave		! set maximum saveable windows
	wrpr %g0, 0, %canrestore		! get rid of windows we will never need again
	wrpr %g0, 0, %otherwin			! make sure the window state is consistent
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window traps for kernel
 
	wrpr %g0, 0, %tl			! TL = 0, primary context register is used
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! Disable interrupts and disable 32-bit address masking.
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
	set PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	mov 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
 
	/*
	 * Because we cannot use global mappings (because we want to
	 * have separate 64-bit address spaces for both the kernel
	 * and the userspace), we prepare the identity mapping also in
	 * context 1. This step is required by the
	 * code installing the ITLB mapping.
	 */
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
	! write DTLB data and install the kernel mapping in context 1
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! enter nucleus - using context 0
	wrpr %g0, 1, %tl
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! leave nucleus - using primary context, i.e. context 0
	wrpr %g0, 0, %tl
 
	brz %l7, 1f				! skip if you are not the bootstrap CPU
	nop
 
	/*
	 * So far, we have not touched the stack.
	 * It is a good idead to set the kernel stack to a known state now.
	 */
	sethi %hi(temporary_boot_stack), %sp
	or %sp, %lo(temporary_boot_stack), %sp
	sub %sp, STACK_BIAS, %sp
 
	sethi %hi(bootinfo), %o0
	call memcpy				! copy bootinfo
	or %o0, %lo(bootinfo), %o0
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
0:
	ba 0b
	nop
 
 
	/*
	 * Read MID from the processor.
	 */
1:
	ldxa [%g0] ASI_UPA_CONFIG, %g1
	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
	and %g1, UPA_CONFIG_MID_MASK, %g1
 
#ifdef CONFIG_SMP
	/*
	 * Active loop for APs until the BSP picks them up.
	 * A processor cannot leave the loop until the
	 * global variable 'waking_up_mid' equals its
	 * MID.
	 */
	set waking_up_mid, %g2
2:
	ldx [%g2], %g3
	cmp %g3, %g1
	bne 2b
	nop
 
	/*
	 * Configure stack for the AP.
	 * The AP is expected to use the stack saved
	 * in the ctx global variable.
	 */
	set ctx, %g1
	add %g1, OFFSET_SP, %g1
	ldx [%g1], %o6
 
	call main_ap
	nop
 
	/* Not reached. */
#endif
	
0:
	ba 0b
	nop
 
 
.section K_DATA_START, "aw", @progbits
 
/*
 * Create small stack to be used by the bootstrap processor.
 * It is going to be used only for a very limited period of
 * time, but we switch to it anyway, just to be sure we are
 * properly initialized.
 *
 * What is important is that this piece of memory is covered
 * by the 4M DTLB locked entry and therefore there will be
 * no surprises like deadly combinations of spill trap and
 * and TLB miss on the stack address.
 */
 
#define INITIAL_STACK_SIZE	1024
 
.align STACK_ALIGNMENT
.space INITIAL_STACK_SIZE
.align STACK_ALIGNMENT
temporary_boot_stack:
.space STACK_WINDOW_SAVE_AREA_SIZE
 

Rev 1906	Rev 1917
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/arch.h>	29	#include <arch/arch.h>
30	#include <arch/regdef.h>	30	#include <arch/regdef.h>
31	#include <arch/boot/boot.h>	31	#include <arch/boot/boot.h>
-		32	#include <arch/stack.h>
32		33
33	#include <arch/mm/mmu.h>	34	#include <arch/mm/mmu.h>
34	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
35	#include <arch/mm/tte.h>	36	#include <arch/mm/tte.h>
36		37
37	#ifdef CONFIG_SMP	38	#ifdef CONFIG_SMP
38	#include <arch/context_offset.h>	39	#include <arch/context_offset.h>
39	#endif	40	#endif
40		41
41	.register %g2, #scratch	42	.register %g2, #scratch
42	.register %g3, #scratch	43	.register %g3, #scratch
43		44
44	.section K_TEXT_START, "ax"	45	.section K_TEXT_START, "ax"
45		46
46	/*	47	/*
47	* Here is where the kernel is passed control	48	* Here is where the kernel is passed control
48	* from the boot loader.	49	* from the boot loader.
49	*	50	*
50	* The registers are expected to be in this state:	51	* The registers are expected to be in this state:
51	* - %o0 non-zero for the bootstrap processor, zero for application/secondary processors	52	* - %o0 non-zero for the bootstrap processor, zero for application/secondary processors
52	* - %o1 bootinfo structure address	53	* - %o1 bootinfo structure address
53	* - %o2 bootinfo structure size	54	* - %o2 bootinfo structure size
54	*	55	*
55	* Moreover, we depend on boot having established the	56	* Moreover, we depend on boot having established the
56	* following environment:	57	* following environment:
57	* - TLBs are on	58	* - TLBs are on
58	* - identity mapping for the kernel image	59	* - identity mapping for the kernel image
59	* - identity mapping for memory stack	-
60	*/	60	*/
61		61
62	.global kernel_image_start	62	.global kernel_image_start
63	kernel_image_start:	63	kernel_image_start:
64	mov %o0, %l7	64	mov %o0, %l7
65		65
66	/*	66	/*
67	* Setup basic runtime environment.	67	* Setup basic runtime environment.
68	*/	68	*/
69		69
70	flushw ! flush all but the active register window	70	wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
-		71	wrpr %g0, 0, %canrestore ! get rid of windows we will never need again
-		72	wrpr %g0, 0, %otherwin ! make sure the window state is consistent
-		73	wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel
71		74
72	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	75	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
73		76
74	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.	77	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
75		78
76	wrpr %g0, 0, %pil ! intialize %pil	79	wrpr %g0, 0, %pil ! intialize %pil
77		80
78	/*	81	/*
79	* Switch to kernel trap table.	82	* Switch to kernel trap table.
80	*/	83	*/
81	sethi %hi(trap_table), %g1	84	sethi %hi(trap_table), %g1
82	wrpr %g1, %lo(trap_table), %tba	85	wrpr %g1, %lo(trap_table), %tba
83		86
84	/*	87	/*
85	* Take over the DMMU by installing global locked	88	* Take over the DMMU by installing global locked
86	* TTE entry identically mapping the first 4M	89	* TTE entry identically mapping the first 4M
87	* of memory.	90	* of memory.
88	*	91	*
89	* In case of DMMU, no FLUSH instructions need to be	92	* In case of DMMU, no FLUSH instructions need to be
90	* issued. Because of that, the old DTLB contents can	93	* issued. Because of that, the old DTLB contents can
91	* be demapped pretty straightforwardly and without	94	* be demapped pretty straightforwardly and without
92	* causing any traps.	95	* causing any traps.
93	*/	96	*/
94		97
95	wr %g0, ASI_DMMU, %asi	98	wr %g0, ASI_DMMU, %asi
96		99
97	#define SET_TLB_DEMAP_CMD(r1, context_id) \	100	#define SET_TLB_DEMAP_CMD(r1, context_id) \
98	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	101	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
99		102
100	! demap context 0	103	! demap context 0
101	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	104	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
102	stxa %g0, [%g1] ASI_DMMU_DEMAP	105	stxa %g0, [%g1] ASI_DMMU_DEMAP
103	membar #Sync	106	membar #Sync
104		107
105	#define SET_TLB_TAG(r1, context) \	108	#define SET_TLB_TAG(r1, context) \
106	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	109	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
107		110
108	! write DTLB tag	111	! write DTLB tag
109	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	112	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
110	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	113	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
111	membar #Sync	114	membar #Sync
112		115
113	#define SET_TLB_DATA(r1, r2, imm) \	116	#define SET_TLB_DATA(r1, r2, imm) \
114	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \	117	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \
115	set PAGESIZE_4M, %r2; \	118	set PAGESIZE_4M, %r2; \
116	sllx %r2, TTE_SIZE_SHIFT, %r2; \	119	sllx %r2, TTE_SIZE_SHIFT, %r2; \
117	or %r1, %r2, %r1; \	120	or %r1, %r2, %r1; \
118	mov 1, %r2; \	121	mov 1, %r2; \
119	sllx %r2, TTE_V_SHIFT, %r2; \	122	sllx %r2, TTE_V_SHIFT, %r2; \
120	or %r1, %r2, %r1;	123	or %r1, %r2, %r1;
121		124
122	! write DTLB data and install the kernel mapping	125	! write DTLB data and install the kernel mapping
123	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping	126	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping
124	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	127	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
125	membar #Sync	128	membar #Sync
126		129
127	/*	130	/*
128	* Because we cannot use global mappings (because we want to	131	* Because we cannot use global mappings (because we want to
129	* have separate 64-bit address spaces for both the kernel	132	* have separate 64-bit address spaces for both the kernel
130	* and the userspace), we prepare the identity mapping also in	133	* and the userspace), we prepare the identity mapping also in
131	* context 1. This step is required by the	134	* context 1. This step is required by the
132	* code installing the ITLB mapping.	135	* code installing the ITLB mapping.
133	*/	136	*/
134	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)	137	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
135	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	138	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
136	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	139	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
137	membar #Sync	140	membar #Sync
138		141
139	! write DTLB data and install the kernel mapping in context 1	142	! write DTLB data and install the kernel mapping in context 1
140	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping	143	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
141	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	144	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
142	membar #Sync	145	membar #Sync
143		146
144	/*	147	/*
145	* Now is time to take over the IMMU.	148	* Now is time to take over the IMMU.
146	* Unfortunatelly, it cannot be done as easily as the DMMU,	149	* Unfortunatelly, it cannot be done as easily as the DMMU,
147	* because the IMMU is mapping the code it executes.	150	* because the IMMU is mapping the code it executes.
148	*	151	*
149	* [ Note that brave experiments with disabling the IMMU	152	* [ Note that brave experiments with disabling the IMMU
150	* and using the DMMU approach failed after a dozen	153	* and using the DMMU approach failed after a dozen
151	* of desparate days with only little success. ]	154	* of desparate days with only little success. ]
152	*	155	*
153	* The approach used here is inspired from OpenBSD.	156	* The approach used here is inspired from OpenBSD.
154	* First, the kernel creates IMMU mapping for itself	157	* First, the kernel creates IMMU mapping for itself
155	* in context 1 (MEM_CONTEXT_TEMP) and switches to	158	* in context 1 (MEM_CONTEXT_TEMP) and switches to
156	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	159	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
157	* afterwards and replaced with the kernel permanent	160	* afterwards and replaced with the kernel permanent
158	* mapping. Finally, the kernel switches back to	161	* mapping. Finally, the kernel switches back to
159	* context 0 and demaps context 1.	162	* context 0 and demaps context 1.
160	*	163	*
161	* Moreover, the IMMU requires use of the FLUSH instructions.	164	* Moreover, the IMMU requires use of the FLUSH instructions.
162	* But that is OK because we always use operands with	165	* But that is OK because we always use operands with
163	* addresses already mapped by the taken over DTLB.	166	* addresses already mapped by the taken over DTLB.
164	*/	167	*/
165		168
166	set kernel_image_start, %g5	169	set kernel_image_start, %g5
167		170
168	! write ITLB tag of context 1	171	! write ITLB tag of context 1
169	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	172	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
170	mov VA_DMMU_TAG_ACCESS, %g2	173	mov VA_DMMU_TAG_ACCESS, %g2
171	stxa %g1, [%g2] ASI_IMMU	174	stxa %g1, [%g2] ASI_IMMU
172	flush %g5	175	flush %g5
173		176
174	! write ITLB data and install the temporary mapping in context 1	177	! write ITLB data and install the temporary mapping in context 1
175	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	178	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
176	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	179	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
177	flush %g5	180	flush %g5
178		181
179	! switch to context 1	182	! switch to context 1
180	mov MEM_CONTEXT_TEMP, %g1	183	mov MEM_CONTEXT_TEMP, %g1
181	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	184	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
182	flush %g5	185	flush %g5
183		186
184	! demap context 0	187	! demap context 0
185	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	188	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
186	stxa %g0, [%g1] ASI_IMMU_DEMAP	189	stxa %g0, [%g1] ASI_IMMU_DEMAP
187	flush %g5	190	flush %g5
188		191
189	! write ITLB tag of context 0	192	! write ITLB tag of context 0
190	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	193	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
191	mov VA_DMMU_TAG_ACCESS, %g2	194	mov VA_DMMU_TAG_ACCESS, %g2
192	stxa %g1, [%g2] ASI_IMMU	195	stxa %g1, [%g2] ASI_IMMU
193	flush %g5	196	flush %g5
194		197
195	! write ITLB data and install the permanent kernel mapping in context 0	198	! write ITLB data and install the permanent kernel mapping in context 0
196	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping	199	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
197	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	200	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
198	flush %g5	201	flush %g5
199		202
200	! enter nucleus - using context 0	203	! enter nucleus - using context 0
201	wrpr %g0, 1, %tl	204	wrpr %g0, 1, %tl
202		205
203	! demap context 1	206	! demap context 1
204	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	207	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
205	stxa %g0, [%g1] ASI_IMMU_DEMAP	208	stxa %g0, [%g1] ASI_IMMU_DEMAP
206	flush %g5	209	flush %g5
207		210
208	! set context 0 in the primary context register	211	! set context 0 in the primary context register
209	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	212	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
210	flush %g5	213	flush %g5
211		214
212	! leave nucleus - using primary context, i.e. context 0	215	! leave nucleus - using primary context, i.e. context 0
213	wrpr %g0, 0, %tl	216	wrpr %g0, 0, %tl
214		217
215	brz %l7, 1f ! skip if you are not the bootstrap CPU	218	brz %l7, 1f ! skip if you are not the bootstrap CPU
216	nop	219	nop
217		220
-		221	/*
-		222	* So far, we have not touched the stack.
-		223	* It is a good idead to set the kernel stack to a known state now.
-		224	*/
-		225	sethi %hi(temporary_boot_stack), %sp
-		226	or %sp, %lo(temporary_boot_stack), %sp
-		227	sub %sp, STACK_BIAS, %sp
-		228
218	sethi %hi(bootinfo), %o0	229	sethi %hi(bootinfo), %o0
219	call memcpy ! copy bootinfo	230	call memcpy ! copy bootinfo
220	or %o0, %lo(bootinfo), %o0	231	or %o0, %lo(bootinfo), %o0
221		232
222	call arch_pre_main	233	call arch_pre_main
223	nop	234	nop
224		235
225	call main_bsp	236	call main_bsp
226	nop	237	nop
227		238
228	/* Not reached. */	239	/* Not reached. */
229		240
230	0:	241	0:
231	ba 0b	242	ba 0b
232	nop	243	nop
233		244
234		245
235	/*	246	/*
236	* Read MID from the processor.	247	* Read MID from the processor.
237	*/	248	*/
238	1:	249	1:
239	ldxa [%g0] ASI_UPA_CONFIG, %g1	250	ldxa [%g0] ASI_UPA_CONFIG, %g1
240	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1	251	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
241	and %g1, UPA_CONFIG_MID_MASK, %g1	252	and %g1, UPA_CONFIG_MID_MASK, %g1
242		253
243	#ifdef CONFIG_SMP	254	#ifdef CONFIG_SMP
244	/*	255	/*
245	* Active loop for APs until the BSP picks them up.	256	* Active loop for APs until the BSP picks them up.
246	* A processor cannot leave the loop until the	257	* A processor cannot leave the loop until the
247	* global variable 'waking_up_mid' equals its	258	* global variable 'waking_up_mid' equals its
248	* MID.	259	* MID.
249	*/	260	*/
250	set waking_up_mid, %g2	261	set waking_up_mid, %g2
251	2:	262	2:
252	ldx [%g2], %g3	263	ldx [%g2], %g3
253	cmp %g3, %g1	264	cmp %g3, %g1
254	bne 2b	265	bne 2b
255	nop	266	nop
256		267
257	/*	268	/*
258	* Configure stack for the AP.	269	* Configure stack for the AP.
259	* The AP is expected to use the stack saved	270	* The AP is expected to use the stack saved
260	* in the ctx global variable.	271	* in the ctx global variable.
261	*/	272	*/
262	set ctx, %g1	273	set ctx, %g1
263	add %g1, OFFSET_SP, %g1	274	add %g1, OFFSET_SP, %g1
264	ldx [%g1], %o6	275	ldx [%g1], %o6
265		276
266	call main_ap	277	call main_ap
267	nop	278	nop
268		279
269	/* Not reached. */	280	/* Not reached. */
270	#endif	281	#endif
271		282
272	0:	283	0:
273	ba 0b	284	ba 0b
274	nop	285	nop
-		286
-		287
-		288	.section K_DATA_START, "aw", @progbits
-		289
-		290	/*
-		291	* Create small stack to be used by the bootstrap processor.
-		292	* It is going to be used only for a very limited period of
-		293	* time, but we switch to it anyway, just to be sure we are
-		294	* properly initialized.
-		295	*
-		296	* What is important is that this piece of memory is covered
-		297	* by the 4M DTLB locked entry and therefore there will be
-		298	* no surprises like deadly combinations of spill trap and
-		299	* and TLB miss on the stack address.
-		300	*/
-		301
-		302	#define INITIAL_STACK_SIZE 1024
-		303
-		304	.align STACK_ALIGNMENT
-		305	.space INITIAL_STACK_SIZE
-		306	.align STACK_ALIGNMENT
-		307	temporary_boot_stack:
-		308	.space STACK_WINDOW_SAVE_AREA_SIZE
275		309

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(root)/trunk/kernel/arch/sparc64/src/start.S – Rev 1906 → 1917