WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/arch.h>
#include <arch/regdef.h>
#include <arch/boot/boot.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
#ifdef CONFIG_SMP
#include <arch/context_offset.h>
#endif
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
/*
 * Here is where the kernel is passed control
 * from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 non-zero for the bootstrap processor, zero for application/secondary processors
 * - %o1 bootinfo structure address
 * - %o2 bootinfo structure size
 *
 * Moreover, we depend on boot having established the
 * following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 * - identity mapping for memory stack
 */
 
.global kernel_image_start
kernel_image_start:
	mov %o0, %l7
 
	/*
	 * Setup basic runtime environment.
	 */
 
	flushw					! flush all but the active register window
 
	wrpr %g0, 0, %tl			! TL = 0, primary context register is used
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! Disable interrupts and disable 32-bit address masking.
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Copy the bootinfo structure passed from the boot loader
	 * to the kernel bootinfo structure.
	 */
	brz %l7, 0f				! skip if you are not the bootstrap CPU
	sethi %hi(bootinfo), %o0
	call memcpy
	or %o0, %lo(bootinfo), %o0
0:
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
	set PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	mov 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
 
	/*
	 * Because we cannot use global mappings (because we want to
	 * have separate 64-bit address spaces for both the kernel
	 * and the userspace), we prepare the identity mapping also in
	 * context 1. This step is required by the
	 * code installing the ITLB mapping.
	 */
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
	! write DTLB data and install the kernel mapping in context 1
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! switch to context 0
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! ensure nucleus mapping
	wrpr %g0, 1, %tl
 
	! set context 1 in the primary context register
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! set TL back to 0
	wrpr %g0, 0, %tl
 
	brz %l7, 1f				! skip if you are not the bootstrap CPU
	nop
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
0:
	ba 0b
	nop
 
 
	/*
	 * Read MID from the processor.
	 */
1:
	ldxa [%g0] ASI_UPA_CONFIG, %g1
	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
	and %g1, UPA_CONFIG_MID_MASK, %g1
 
	/*
	 * Active loop for APs until the BSP picks them up.
	 * A processor cannot leave the loop until the
	 * global variable 'waking_up_mid' equals its
	 * MID.
	 */
	set waking_up_mid, %g2
2:
	ldx [%g2], %g3
	cmp %g3, %g1
	bne 2b
	nop
 
#ifdef CONFIG_SMP
	/*
	 * Configure stack for the AP.
	 * The AP is expected to use the stack saved
	 * in the ctx global variable.
	 */
	set ctx, %g1
	add %g1, OFFSET_SP, %g1
	ldx [%g1], %o6
 
	call main_ap
	nop
#endif
 
	/* Not reached. */
	
0:
	ba 0b
	nop
 

Rev 1900	Rev 1903
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
-		29	#include <arch/arch.h>
29	#include <arch/regdef.h>	30	#include <arch/regdef.h>
30	#include <arch/boot/boot.h>	31	#include <arch/boot/boot.h>
31		32
32	#include <arch/mm/mmu.h>	33	#include <arch/mm/mmu.h>
33	#include <arch/mm/tlb.h>	34	#include <arch/mm/tlb.h>
34	#include <arch/mm/tte.h>	35	#include <arch/mm/tte.h>
35		36
-		37	#ifdef CONFIG_SMP
-		38	#include <arch/context_offset.h>
-		39	#endif
-		40
36	.register %g2, #scratch	41	.register %g2, #scratch
37	.register %g3, #scratch	42	.register %g3, #scratch
38		43
39	.section K_TEXT_START, "ax"	44	.section K_TEXT_START, "ax"
40		45
41	/*	46	/*
42	* Here is where the kernel is passed control	47	* Here is where the kernel is passed control
43	* from the boot loader.	48	* from the boot loader.
44	*	49	*
45	* The registers are expected to be in this state:	50	* The registers are expected to be in this state:
46	* - %o0 non-zero for the bootstrap processor, zero for application/secondary processors	51	* - %o0 non-zero for the bootstrap processor, zero for application/secondary processors
47	* - %o1 bootinfo structure address	52	* - %o1 bootinfo structure address
48	* - %o2 bootinfo structure size	53	* - %o2 bootinfo structure size
49	*	54	*
50	* Moreover, we depend on boot having established the	55	* Moreover, we depend on boot having established the
51	* following environment:	56	* following environment:
52	* - TLBs are on	57	* - TLBs are on
53	* - identity mapping for the kernel image	58	* - identity mapping for the kernel image
54	* - identity mapping for memory stack	59	* - identity mapping for memory stack
55	*/	60	*/
56		61
57	.global kernel_image_start	62	.global kernel_image_start
58	kernel_image_start:	63	kernel_image_start:
59	mov %o0, %l7	64	mov %o0, %l7
60		65
61	/*	66	/*
62	* Setup basic runtime environment.	67	* Setup basic runtime environment.
63	*/	68	*/
64		69
65	flushw ! flush all but the active register window	70	flushw ! flush all but the active register window
66		71
67	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	72	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
68		73
69	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.	74	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
70		75
71	wrpr %g0, 0, %pil ! intialize %pil	76	wrpr %g0, 0, %pil ! intialize %pil
72		77
73	/*	78	/*
74	* Copy the bootinfo structure passed from the boot loader	79	* Copy the bootinfo structure passed from the boot loader
75	* to the kernel bootinfo structure.	80	* to the kernel bootinfo structure.
76	*/	81	*/
77	brz %l7, 0f ! skip if you are not the bootstrap CPU	82	brz %l7, 0f ! skip if you are not the bootstrap CPU
78	sethi %hi(bootinfo), %o0	83	sethi %hi(bootinfo), %o0
79	call memcpy	84	call memcpy
80	or %o0, %lo(bootinfo), %o0	85	or %o0, %lo(bootinfo), %o0
81	0:	86	0:
82		87
83	/*	88	/*
84	* Switch to kernel trap table.	89	* Switch to kernel trap table.
85	*/	90	*/
86	sethi %hi(trap_table), %g1	91	sethi %hi(trap_table), %g1
87	wrpr %g1, %lo(trap_table), %tba	92	wrpr %g1, %lo(trap_table), %tba
88		93
89	/*	94	/*
90	* Take over the DMMU by installing global locked	95	* Take over the DMMU by installing global locked
91	* TTE entry identically mapping the first 4M	96	* TTE entry identically mapping the first 4M
92	* of memory.	97	* of memory.
93	*	98	*
94	* In case of DMMU, no FLUSH instructions need to be	99	* In case of DMMU, no FLUSH instructions need to be
95	* issued. Because of that, the old DTLB contents can	100	* issued. Because of that, the old DTLB contents can
96	* be demapped pretty straightforwardly and without	101	* be demapped pretty straightforwardly and without
97	* causing any traps.	102	* causing any traps.
98	*/	103	*/
99		104
100	wr %g0, ASI_DMMU, %asi	105	wr %g0, ASI_DMMU, %asi
101		106
102	#define SET_TLB_DEMAP_CMD(r1, context_id) \	107	#define SET_TLB_DEMAP_CMD(r1, context_id) \
103	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	108	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
104		109
105	! demap context 0	110	! demap context 0
106	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	111	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
107	stxa %g0, [%g1] ASI_DMMU_DEMAP	112	stxa %g0, [%g1] ASI_DMMU_DEMAP
108	membar #Sync	113	membar #Sync
109		114
110	#define SET_TLB_TAG(r1, context) \	115	#define SET_TLB_TAG(r1, context) \
111	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	116	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
112		117
113	! write DTLB tag	118	! write DTLB tag
114	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	119	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
115	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	120	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
116	membar #Sync	121	membar #Sync
117		122
118	#define SET_TLB_DATA(r1, r2, imm) \	123	#define SET_TLB_DATA(r1, r2, imm) \
119	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \	124	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \
120	set PAGESIZE_4M, %r2; \	125	set PAGESIZE_4M, %r2; \
121	sllx %r2, TTE_SIZE_SHIFT, %r2; \	126	sllx %r2, TTE_SIZE_SHIFT, %r2; \
122	or %r1, %r2, %r1; \	127	or %r1, %r2, %r1; \
123	mov 1, %r2; \	128	mov 1, %r2; \
124	sllx %r2, TTE_V_SHIFT, %r2; \	129	sllx %r2, TTE_V_SHIFT, %r2; \
125	or %r1, %r2, %r1;	130	or %r1, %r2, %r1;
126		131
127	! write DTLB data and install the kernel mapping	132	! write DTLB data and install the kernel mapping
128	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping	133	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping
129	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	134	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
130	membar #Sync	135	membar #Sync
131		136
132	/*	137	/*
133	* Because we cannot use global mappings (because we want to	138	* Because we cannot use global mappings (because we want to
134	* have separate 64-bit address spaces for both the kernel	139	* have separate 64-bit address spaces for both the kernel
135	* and the userspace), we prepare the identity mapping also in	140	* and the userspace), we prepare the identity mapping also in
136	* context 1. This step is required by the	141	* context 1. This step is required by the
137	* code installing the ITLB mapping.	142	* code installing the ITLB mapping.
138	*/	143	*/
139	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)	144	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
140	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	145	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
141	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	146	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
142	membar #Sync	147	membar #Sync
143		148
144	! write DTLB data and install the kernel mapping in context 1	149	! write DTLB data and install the kernel mapping in context 1
145	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping	150	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
146	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	151	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
147	membar #Sync	152	membar #Sync
148		153
149	/*	154	/*
150	* Now is time to take over the IMMU.	155	* Now is time to take over the IMMU.
151	* Unfortunatelly, it cannot be done as easily as the DMMU,	156	* Unfortunatelly, it cannot be done as easily as the DMMU,
152	* because the IMMU is mapping the code it executes.	157	* because the IMMU is mapping the code it executes.
153	*	158	*
154	* [ Note that brave experiments with disabling the IMMU	159	* [ Note that brave experiments with disabling the IMMU
155	* and using the DMMU approach failed after a dozen	160	* and using the DMMU approach failed after a dozen
156	* of desparate days with only little success. ]	161	* of desparate days with only little success. ]
157	*	162	*
158	* The approach used here is inspired from OpenBSD.	163	* The approach used here is inspired from OpenBSD.
159	* First, the kernel creates IMMU mapping for itself	164	* First, the kernel creates IMMU mapping for itself
160	* in context 1 (MEM_CONTEXT_TEMP) and switches to	165	* in context 1 (MEM_CONTEXT_TEMP) and switches to
161	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	166	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
162	* afterwards and replaced with the kernel permanent	167	* afterwards and replaced with the kernel permanent
163	* mapping. Finally, the kernel switches back to	168	* mapping. Finally, the kernel switches back to
164	* context 0 and demaps context 1.	169	* context 0 and demaps context 1.
165	*	170	*
166	* Moreover, the IMMU requires use of the FLUSH instructions.	171	* Moreover, the IMMU requires use of the FLUSH instructions.
167	* But that is OK because we always use operands with	172	* But that is OK because we always use operands with
168	* addresses already mapped by the taken over DTLB.	173	* addresses already mapped by the taken over DTLB.
169	*/	174	*/
170		175
171	set kernel_image_start, %g5	176	set kernel_image_start, %g5
172		177
173	! write ITLB tag of context 1	178	! write ITLB tag of context 1
174	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	179	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
175	mov VA_DMMU_TAG_ACCESS, %g2	180	mov VA_DMMU_TAG_ACCESS, %g2
176	stxa %g1, [%g2] ASI_IMMU	181	stxa %g1, [%g2] ASI_IMMU
177	flush %g5	182	flush %g5
178		183
179	! write ITLB data and install the temporary mapping in context 1	184	! write ITLB data and install the temporary mapping in context 1
180	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	185	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
181	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	186	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
182	flush %g5	187	flush %g5
183		188
184	! switch to context 1	189	! switch to context 1
185	mov MEM_CONTEXT_TEMP, %g1	190	mov MEM_CONTEXT_TEMP, %g1
186	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	191	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
187	flush %g5	192	flush %g5
188		193
189	! demap context 0	194	! demap context 0
190	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	195	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
191	stxa %g0, [%g1] ASI_IMMU_DEMAP	196	stxa %g0, [%g1] ASI_IMMU_DEMAP
192	flush %g5	197	flush %g5
193		198
194	! write ITLB tag of context 0	199	! write ITLB tag of context 0
195	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	200	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
196	mov VA_DMMU_TAG_ACCESS, %g2	201	mov VA_DMMU_TAG_ACCESS, %g2
197	stxa %g1, [%g2] ASI_IMMU	202	stxa %g1, [%g2] ASI_IMMU
198	flush %g5	203	flush %g5
199		204
200	! write ITLB data and install the permanent kernel mapping in context 0	205	! write ITLB data and install the permanent kernel mapping in context 0
201	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping	206	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
202	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	207	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
203	flush %g5	208	flush %g5
204		209
205	! switch to context 0	210	! switch to context 0
206	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	211	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
207	flush %g5	212	flush %g5
208		213
209	! ensure nucleus mapping	214	! ensure nucleus mapping
210	wrpr %g0, 1, %tl	215	wrpr %g0, 1, %tl
211		216
212	! set context 1 in the primary context register	217	! set context 1 in the primary context register
213	mov MEM_CONTEXT_TEMP, %g1	218	mov MEM_CONTEXT_TEMP, %g1
214	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	219	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
215	flush %g5	220	flush %g5
216		221
217	! demap context 1	222	! demap context 1
218	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	223	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
219	stxa %g0, [%g1] ASI_IMMU_DEMAP	224	stxa %g0, [%g1] ASI_IMMU_DEMAP
220	flush %g5	225	flush %g5
221		226
222	! set context 0 in the primary context register	227	! set context 0 in the primary context register
223	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	228	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
224	flush %g5	229	flush %g5
225		230
226	! set TL back to 0	231	! set TL back to 0
227	wrpr %g0, 0, %tl	232	wrpr %g0, 0, %tl
228		233
229	brz %l7, 2f ! skip if you are not the bootstrap CPU	234	brz %l7, 1f ! skip if you are not the bootstrap CPU
-		235	nop
230		236
231	call arch_pre_main	237	call arch_pre_main
232	nop	238	nop
233		239
234	call main_bsp	240	call main_bsp
235	nop	241	nop
236		242
237	/* Not reached. */	243	/* Not reached. */
238		244
-		245	0:
-		246	ba 0b
-		247	nop
-		248
-		249
-		250	/*
-		251	* Read MID from the processor.
-		252	*/
-		253	1:
-		254	ldxa [%g0] ASI_UPA_CONFIG, %g1
-		255	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
-		256	and %g1, UPA_CONFIG_MID_MASK, %g1
-		257
-		258	/*
-		259	* Active loop for APs until the BSP picks them up.
-		260	* A processor cannot leave the loop until the
-		261	* global variable 'waking_up_mid' equals its
-		262	* MID.
-		263	*/
-		264	set waking_up_mid, %g2
239	2:	265	2:
-		266	ldx [%g2], %g3
-		267	cmp %g3, %g1
240	b 2b	268	bne 2b
-		269	nop
-		270
-		271	#ifdef CONFIG_SMP
-		272	/*
-		273	* Configure stack for the AP.
-		274	* The AP is expected to use the stack saved
-		275	* in the ctx global variable.
-		276	*/
-		277	set ctx, %g1
-		278	add %g1, OFFSET_SP, %g1
-		279	ldx [%g1], %o6
-		280
-		281	call main_ap
-		282	nop
-		283	#endif
-		284
-		285	/* Not reached. */
-		286
-		287	0:
-		288	ba 0b
241	nop	289	nop
242		290

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(root)/trunk/kernel/arch/sparc64/src/start.S – Rev 1900 → 1903