WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/regdef.h>
#include <arch/boot/boot.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
.register %g2, #scratch
.register %g3, #scratch
 
 
 
.section K_TEXT_START, "ax"
 
/*
 * Here is where the kernel is passed control
 * from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 bootinfo structure address
 * - %o1 bootinfo structure size
 *
 * Moreover, we depend on boot having established the
 * following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 * - identity mapping for memory stack
 */
 
.global kernel_image_start
kernel_image_start:
 
	/*
	 * Setup basic runtime environment.
	 */
 
	flushw				! flush all but the active register window
	wrpr %g0, 0, %tl		! TL = 0, primary context register is used
 
	! Disable interrupts and disable 32-bit address masking.
	rdpr %pstate, %g1
	and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1
	wrpr %g1, 0, %pstate
 
	wrpr %r0, 0, %pil		! intialize %pil
 
	/*
	 * Copy the bootinfo structure passed from the boot loader
	 * to the kernel bootinfo structure.
	 */
	mov %o1, %o2
	mov %o0, %o1
	set bootinfo, %o0
	call memcpy
	nop
 
	/*
	 * Switch to kernel trap table.
	 */
	set trap_table, %g1
	wrpr %g1, 0, %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
	set PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	set 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, TTE_G)
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	set VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	set MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	set VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! switch to context 0
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! ensure nucleus mapping
	wrpr %g0, 1, %tl
 
	! set context 1 in the primary context register
	set MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! set TL back to 0
	wrpr %g0, 0, %tl
	
	call main_bsp
	nop
 
	/* Not reached. */
 
2:
	b 2b
	nop
 

Rev 1823	Rev 1852
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/regdef.h>	29	#include <arch/regdef.h>
30	#include <arch/boot/boot.h>	30	#include <arch/boot/boot.h>
31		31
32	#include <arch/mm/mmu.h>	32	#include <arch/mm/mmu.h>
33	#include <arch/mm/tlb.h>	33	#include <arch/mm/tlb.h>
34	#include <arch/mm/tte.h>	34	#include <arch/mm/tte.h>
35		35
36	.register %g2, #scratch	36	.register %g2, #scratch
37	.register %g3, #scratch	37	.register %g3, #scratch
38	.register %g6, #scratch	-
39	.register %g7, #scratch	-
40		38
41	.section K_TEXT_START, "ax"	39	.section K_TEXT_START, "ax"
42		40
43	/*	41	/*
44	* Here is where the kernel is passed control	42	* Here is where the kernel is passed control
45	* from the boot loader.	43	* from the boot loader.
46	*	44	*
47	* The registers are expected to be in this state:	45	* The registers are expected to be in this state:
48	* - %o0 bootinfo structure address	46	* - %o0 bootinfo structure address
49	* - %o1 bootinfo structure size	47	* - %o1 bootinfo structure size
50	*	48	*
51	* Moreover, we depend on boot having established the	49	* Moreover, we depend on boot having established the
52	* following environment:	50	* following environment:
53	* - TLBs are on	51	* - TLBs are on
54	* - identity mapping for the kernel image	52	* - identity mapping for the kernel image
55	* - identity mapping for memory stack	53	* - identity mapping for memory stack
56	*/	54	*/
57		55
58	.global kernel_image_start	56	.global kernel_image_start
59	kernel_image_start:	57	kernel_image_start:
60		58
61	/*	59	/*
62	* Setup basic runtime environment.	60	* Setup basic runtime environment.
63	*/	61	*/
64		62
65	flushw ! flush all but the active register window	63	flushw ! flush all but the active register window
66	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	64	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
67		65
68	! Disable interrupts and disable 32-bit address masking.	66	! Disable interrupts and disable 32-bit address masking.
69	rdpr %pstate, %g1	67	rdpr %pstate, %g1
70	and %g1, ~(PSTATE_AM_BIT\|PSTATE_IE_BIT), %g1	68	and %g1, ~(PSTATE_AM_BIT\|PSTATE_IE_BIT), %g1
71	wrpr %g1, 0, %pstate	69	wrpr %g1, 0, %pstate
72		70
73	wrpr %r0, 0, %pil ! intialize %pil	71	wrpr %r0, 0, %pil ! intialize %pil
74		72
75	/*	73	/*
76	* Copy the bootinfo structure passed from the boot loader	74	* Copy the bootinfo structure passed from the boot loader
77	* to the kernel bootinfo structure.	75	* to the kernel bootinfo structure.
78	*/	76	*/
79	mov %o1, %o2	77	mov %o1, %o2
80	mov %o0, %o1	78	mov %o0, %o1
81	set bootinfo, %o0	79	set bootinfo, %o0
82	call memcpy	80	call memcpy
83	nop	81	nop
84		82
85	/*	83	/*
86	* Switch to kernel trap table.	84	* Switch to kernel trap table.
87	*/	85	*/
88	set trap_table, %g1	86	set trap_table, %g1
89	wrpr %g1, 0, %tba	87	wrpr %g1, 0, %tba
90		88
91	/*	89	/*
92	* Take over the DMMU by installing global locked	90	* Take over the DMMU by installing global locked
93	* TTE entry identically mapping the first 4M	91	* TTE entry identically mapping the first 4M
94	* of memory.	92	* of memory.
95	*	93	*
96	* In case of DMMU, no FLUSH instructions need to be	94	* In case of DMMU, no FLUSH instructions need to be
97	* issued. Because of that, the old DTLB contents can	95	* issued. Because of that, the old DTLB contents can
98	* be demapped pretty straightforwardly and without	96	* be demapped pretty straightforwardly and without
99	* causing any traps.	97	* causing any traps.
100	*/	98	*/
101		99
102	wr %g0, ASI_DMMU, %asi	100	wr %g0, ASI_DMMU, %asi
103		101
104	#define SET_TLB_DEMAP_CMD(r1, context_id) \	102	#define SET_TLB_DEMAP_CMD(r1, context_id) \
105	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	103	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
106		104
107	! demap context 0	105	! demap context 0
108	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	106	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
109	stxa %g0, [%g1] ASI_DMMU_DEMAP	107	stxa %g0, [%g1] ASI_DMMU_DEMAP
110	membar #Sync	108	membar #Sync
111		109
112	#define SET_TLB_TAG(r1, context) \	110	#define SET_TLB_TAG(r1, context) \
113	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	111	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
114		112
115	! write DTLB tag	113	! write DTLB tag
116	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	114	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
117	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	115	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
118	membar #Sync	116	membar #Sync
119		117
120	#define SET_TLB_DATA(r1, r2, imm) \	118	#define SET_TLB_DATA(r1, r2, imm) \
121	set TTE_L \| TTE_CP \| TTE_P \| TTE_W \| LMA \| imm, %r1; \	119	set TTE_L \| TTE_CP \| TTE_P \| TTE_W \| LMA \| imm, %r1; \
122	set PAGESIZE_4M, %r2; \	120	set PAGESIZE_4M, %r2; \
123	sllx %r2, TTE_SIZE_SHIFT, %r2; \	121	sllx %r2, TTE_SIZE_SHIFT, %r2; \
124	or %r1, %r2, %r1; \	122	or %r1, %r2, %r1; \
125	set 1, %r2; \	123	set 1, %r2; \
126	sllx %r2, TTE_V_SHIFT, %r2; \	124	sllx %r2, TTE_V_SHIFT, %r2; \
127	or %r1, %r2, %r1;	125	or %r1, %r2, %r1;
128		126
129	! write DTLB data and install the kernel mapping	127	! write DTLB data and install the kernel mapping
130	SET_TLB_DATA(g1, g2, TTE_G)	128	SET_TLB_DATA(g1, g2, TTE_G)
131	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	129	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
132	membar #Sync	130	membar #Sync
133		131
134	/*	132	/*
135	* Now is time to take over the IMMU.	133	* Now is time to take over the IMMU.
136	* Unfortunatelly, it cannot be done as easily as the DMMU,	134	* Unfortunatelly, it cannot be done as easily as the DMMU,
137	* because the IMMU is mapping the code it executes.	135	* because the IMMU is mapping the code it executes.
138	*	136	*
139	* [ Note that brave experiments with disabling the IMMU	137	* [ Note that brave experiments with disabling the IMMU
140	* and using the DMMU approach failed after a dozen	138	* and using the DMMU approach failed after a dozen
141	* of desparate days with only little success. ]	139	* of desparate days with only little success. ]
142	*	140	*
143	* The approach used here is inspired from OpenBSD.	141	* The approach used here is inspired from OpenBSD.
144	* First, the kernel creates IMMU mapping for itself	142	* First, the kernel creates IMMU mapping for itself
145	* in context 1 (MEM_CONTEXT_TEMP) and switches to	143	* in context 1 (MEM_CONTEXT_TEMP) and switches to
146	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	144	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
147	* afterwards and replaced with the kernel permanent	145	* afterwards and replaced with the kernel permanent
148	* mapping. Finally, the kernel switches back to	146	* mapping. Finally, the kernel switches back to
149	* context 0 and demaps context 1.	147	* context 0 and demaps context 1.
150	*	148	*
151	* Moreover, the IMMU requires use of the FLUSH instructions.	149	* Moreover, the IMMU requires use of the FLUSH instructions.
152	* But that is OK because we always use operands with	150	* But that is OK because we always use operands with
153	* addresses already mapped by the taken over DTLB.	151	* addresses already mapped by the taken over DTLB.
154	*/	152	*/
155		153
156	set kernel_image_start, %g7	154	set kernel_image_start, %g5
157		155
158	! write ITLB tag of context 1	156	! write ITLB tag of context 1
159	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	157	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
160	set VA_DMMU_TAG_ACCESS, %g2	158	set VA_DMMU_TAG_ACCESS, %g2
161	stxa %g1, [%g2] ASI_IMMU	159	stxa %g1, [%g2] ASI_IMMU
162	flush %g7	160	flush %g5
163		161
164	! write ITLB data and install the temporary mapping in context 1	162	! write ITLB data and install the temporary mapping in context 1
165	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	163	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
166	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	164	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
167	flush %g7	165	flush %g5
168		166
169	! switch to context 1	167	! switch to context 1
170	set MEM_CONTEXT_TEMP, %g1	168	set MEM_CONTEXT_TEMP, %g1
171	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	169	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
172	flush %g7	170	flush %g5
173		171
174	! demap context 0	172	! demap context 0
175	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	173	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
176	stxa %g0, [%g1] ASI_IMMU_DEMAP	174	stxa %g0, [%g1] ASI_IMMU_DEMAP
177	flush %g7	175	flush %g5
178		176
179	! write ITLB tag of context 0	177	! write ITLB tag of context 0
180	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	178	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
181	set VA_DMMU_TAG_ACCESS, %g2	179	set VA_DMMU_TAG_ACCESS, %g2
182	stxa %g1, [%g2] ASI_IMMU	180	stxa %g1, [%g2] ASI_IMMU
183	flush %g7	181	flush %g5
184		182
185	! write ITLB data and install the permanent kernel mapping in context 0	183	! write ITLB data and install the permanent kernel mapping in context 0
186	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	184	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
187	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	185	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
188	flush %g7	186	flush %g5
189		187
190	! switch to context 0	188	! switch to context 0
191	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	189	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
192	flush %g7	190	flush %g5
193		191
194	! ensure nucleus mapping	192	! ensure nucleus mapping
195	wrpr %g0, 1, %tl	193	wrpr %g0, 1, %tl
196		194
197	! set context 1 in the primary context register	195	! set context 1 in the primary context register
198	set MEM_CONTEXT_TEMP, %g1	196	set MEM_CONTEXT_TEMP, %g1
199	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	197	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
200	flush %g7	198	flush %g5
201		199
202	! demap context 1	200	! demap context 1
203	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	201	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
204	stxa %g0, [%g1] ASI_IMMU_DEMAP	202	stxa %g0, [%g1] ASI_IMMU_DEMAP
205	flush %g7	203	flush %g5
206		204
207	! set context 0 in the primary context register	205	! set context 0 in the primary context register
208	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	206	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
209	flush %g7	207	flush %g5
210		208
211	! set TL back to 0	209	! set TL back to 0
212	wrpr %g0, 0, %tl	210	wrpr %g0, 0, %tl
213		211
214	call main_bsp	212	call main_bsp
215	nop	213	nop
216		214
217	/* Not reached. */	215	/* Not reached. */
218		216
219	2:	217	2:
220	b 2b	218	b 2b
221	nop	219	nop
222		220

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/start.S – Rev 1823 → 1852