WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/smp/ipi.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#include <smp/ipi.h>
#include <cpu.h>
#include <arch.h>
#include <arch/cpu.h>
#include <arch/asm.h>
#include <config.h>
#include <mm/tlb.h>
 
#include <arch/interrupt.h>
#include <arch/trap/interrupt.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <time/delay.h>
#include <panic.h>
 
/** Invoke function on another processor.
 *
 * Currently, only functions without arguments are supported.
 * Supporting more arguments in the future should be no big deal.
 *
 * Interrupts must be disabled prior to this call.
 *
 * @param mid MID of the target processor.
 * @param func Function to be invoked.
 */
static void cross_call(int mid, void (* func)(void))
{
    uint64_t status;
    bool done;
 
    /*
     * This function might enable interrupts for a while.
     * In order to prevent migration to another processor,
     * we explicitly disable preemption.
     */
   
    preemption_disable();
   
    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
    if (status & INTR_DISPATCH_STATUS_BUSY)
        panic("Interrupt Dispatch Status busy bit set\n");
   
    do {
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
            func);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
        asi_u64_write(ASI_UDB_INTR_W,
            (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
            ASI_UDB_INTR_W_DISPATCH, 0);
   
        membar();
       
        do {
            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
        } while (status & INTR_DISPATCH_STATUS_BUSY);
       
        done = !(status & INTR_DISPATCH_STATUS_NACK);
        if (!done) {
            /*
             * Prevent deadlock.
             */        
            (void) interrupts_enable();
            delay(20 + (tick_read() & 0xff));
            (void) interrupts_disable();
        }
    } while (done);
   
    preemption_enable();
}
 
/*
 * Deliver IPI to all processors except the current one.
 *
 * The sparc64 architecture does not support any group addressing
 * which is found, for instance, on ia32 and amd64. Therefore we
 * need to simulate the broadcast by sending the message to
 * all target processors step by step.
 *
 * We assume that interrupts are disabled.
 *
 * @param ipi IPI number.
 */
void ipi_broadcast_arch(int ipi)
{
    int i;
   
    void (* func)(void);
   
    switch (ipi) {
    case IPI_TLB_SHOOTDOWN:
        func = tlb_shootdown_ipi_recv;
        break;
 
 
 
 
 
    default:
        panic("Unknown IPI (%d).\n", ipi);
        break;
    }
   
    /*
     * As long as we don't support hot-plugging
     * or hot-unplugging of CPUs, we can walk
     * the cpus array and read processor's MID
     * without locking.
     */
   
    for (i = 0; i < config.cpu_active; i++) {
        if (&cpus[i] == CPU)
            continue;       /* skip the current CPU */
 
        cross_call(cpus[i].arch.mid, func);
    }
}
 
/** @}
 */
 

Rev 2134	Rev 2141
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <smp/ipi.h>	35	#include <smp/ipi.h>
36	#include <cpu.h>	36	#include <cpu.h>
37	#include <arch.h>	37	#include <arch.h>
38	#include <arch/cpu.h>	38	#include <arch/cpu.h>
39	#include <arch/asm.h>	39	#include <arch/asm.h>
40	#include <config.h>	40	#include <config.h>
41	#include <mm/tlb.h>	41	#include <mm/tlb.h>
42	#include <arch/mm/cache.h>	-
43	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
44	#include <arch/trap/interrupt.h>	43	#include <arch/trap/interrupt.h>
45	#include <arch/barrier.h>	44	#include <arch/barrier.h>
46	#include <preemption.h>	45	#include <preemption.h>
47	#include <time/delay.h>	46	#include <time/delay.h>
48	#include <panic.h>	47	#include <panic.h>
49		48
50	/** Invoke function on another processor.	49	/** Invoke function on another processor.
51	*	50	*
52	* Currently, only functions without arguments are supported.	51	* Currently, only functions without arguments are supported.
53	* Supporting more arguments in the future should be no big deal.	52	* Supporting more arguments in the future should be no big deal.
54	*	53	*
55	* Interrupts must be disabled prior to this call.	54	* Interrupts must be disabled prior to this call.
56	*	55	*
57	* @param mid MID of the target processor.	56	* @param mid MID of the target processor.
58	* @param func Function to be invoked.	57	* @param func Function to be invoked.
59	*/	58	*/
60	static void cross_call(int mid, void (* func)(void))	59	static void cross_call(int mid, void (* func)(void))
61	{	60	{
62	uint64_t status;	61	uint64_t status;
63	bool done;	62	bool done;
64		63
65	/*	64	/*
66	* This function might enable interrupts for a while.	65	* This function might enable interrupts for a while.
67	* In order to prevent migration to another processor,	66	* In order to prevent migration to another processor,
68	* we explicitly disable preemption.	67	* we explicitly disable preemption.
69	*/	68	*/
70		69
71	preemption_disable();	70	preemption_disable();
72		71
73	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	72	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
74	if (status & INTR_DISPATCH_STATUS_BUSY)	73	if (status & INTR_DISPATCH_STATUS_BUSY)
75	panic("Interrupt Dispatch Status busy bit set\n");	74	panic("Interrupt Dispatch Status busy bit set\n");
76		75
77	do {	76	do {
78	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)	77	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
79	func);	78	func);
80	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);	79	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
81	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);	80	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
82	asi_u64_write(ASI_UDB_INTR_W,	81	asi_u64_write(ASI_UDB_INTR_W,
83	(mid << INTR_VEC_DISPATCH_MID_SHIFT) \|	82	(mid << INTR_VEC_DISPATCH_MID_SHIFT) \|
84	ASI_UDB_INTR_W_DISPATCH, 0);	83	ASI_UDB_INTR_W_DISPATCH, 0);
85		84
86	membar();	85	membar();
87		86
88	do {	87	do {
89	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	88	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
90	} while (status & INTR_DISPATCH_STATUS_BUSY);	89	} while (status & INTR_DISPATCH_STATUS_BUSY);
91		90
92	done = !(status & INTR_DISPATCH_STATUS_NACK);	91	done = !(status & INTR_DISPATCH_STATUS_NACK);
93	if (!done) {	92	if (!done) {
94	/*	93	/*
95	* Prevent deadlock.	94	* Prevent deadlock.
96	*/	95	*/
97	(void) interrupts_enable();	96	(void) interrupts_enable();
98	delay(20 + (tick_read() & 0xff));	97	delay(20 + (tick_read() & 0xff));
99	(void) interrupts_disable();	98	(void) interrupts_disable();
100	}	99	}
101	} while (done);	100	} while (done);
102		101
103	preemption_enable();	102	preemption_enable();
104	}	103	}
105		104
106	/*	105	/*
107	* Deliver IPI to all processors except the current one.	106	* Deliver IPI to all processors except the current one.
108	*	107	*
109	* The sparc64 architecture does not support any group addressing	108	* The sparc64 architecture does not support any group addressing
110	* which is found, for instance, on ia32 and amd64. Therefore we	109	* which is found, for instance, on ia32 and amd64. Therefore we
111	* need to simulate the broadcast by sending the message to	110	* need to simulate the broadcast by sending the message to
112	* all target processors step by step.	111	* all target processors step by step.
113	*	112	*
114	* We assume that interrupts are disabled.	113	* We assume that interrupts are disabled.
115	*	114	*
116	* @param ipi IPI number.	115	* @param ipi IPI number.
117	*/	116	*/
118	void ipi_broadcast_arch(int ipi)	117	void ipi_broadcast_arch(int ipi)
119	{	118	{
120	int i;	119	int i;
121		120
122	void (* func)(void);	121	void (* func)(void);
123		122
124	switch (ipi) {	123	switch (ipi) {
125	case IPI_TLB_SHOOTDOWN:	124	case IPI_TLB_SHOOTDOWN:
126	func = tlb_shootdown_ipi_recv;	125	func = tlb_shootdown_ipi_recv;
127	break;	126	break;
128	#if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE)))	-
129	case IPI_DCACHE_SHOOTDOWN:	-
130	func = dcache_shootdown_ipi_recv;	-
131	break;	-
132	#endif	-
133	default:	127	default:
134	panic("Unknown IPI (%d).\n", ipi);	128	panic("Unknown IPI (%d).\n", ipi);
135	break;	129	break;
136	}	130	}
137		131
138	/*	132	/*
139	* As long as we don't support hot-plugging	133	* As long as we don't support hot-plugging
140	* or hot-unplugging of CPUs, we can walk	134	* or hot-unplugging of CPUs, we can walk
141	* the cpus array and read processor's MID	135	* the cpus array and read processor's MID
142	* without locking.	136	* without locking.
143	*/	137	*/
144		138
145	for (i = 0; i < config.cpu_active; i++) {	139	for (i = 0; i < config.cpu_active; i++) {
146	if (&cpus[i] == CPU)	140	if (&cpus[i] == CPU)
147	continue; /* skip the current CPU */	141	continue; /* skip the current CPU */
148		142
149	cross_call(cpus[i].arch.mid, func);	143	cross_call(cpus[i].arch.mid, func);
150	}	144	}
151	}	145	}
152		146
153	/** @}	147	/** @}
154	*/	148	*/
155		149

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/smp/ipi.c – Rev 2134 → 2141