WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/smp/ipi.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#include <smp/ipi.h>
#include <cpu.h>
#include <arch.h>
#include <arch/cpu.h>
#include <arch/asm.h>
#include <config.h>
#include <mm/tlb.h>
#include <arch/mm/cache.h>
#include <arch/interrupt.h>
#include <arch/trap/interrupt.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <time/delay.h>
#include <panic.h>
 
/** Invoke function on another processor.
 *
 * Currently, only functions without arguments are supported.
 * Supporting more arguments in the future should be no big deal.
 *
 * Interrupts must be disabled prior to this call.
 *
 * @param mid MID of the target processor.
 * @param func Function to be invoked.
 */
static void cross_call(int mid, void (* func)(void))
{
    uint64_t status;
    bool done;
 
    /*
     * This function might enable interrupts for a while.
     * In order to prevent migration to another processor,
     * we explicitly disable preemption.
     */
   
    preemption_disable();
   
    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
    if (status & INTR_DISPATCH_STATUS_BUSY)
        panic("Interrupt Dispatch Status busy bit set\n");
   
    do {
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
            func);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
        asi_u64_write(ASI_UDB_INTR_W,
            (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
            ASI_UDB_INTR_W_DISPATCH, 0);
   
        membar();
       
        do {
            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
        } while (status & INTR_DISPATCH_STATUS_BUSY);
       
        done = !(status & INTR_DISPATCH_STATUS_NACK);
        if (!done) {
            /*
             * Prevent deadlock.
             */        
            (void) interrupts_enable();
            delay(20 + (tick_read() & 0xff));
            (void) interrupts_disable();
        }
    } while (done);
   
    preemption_enable();
}
 
/*
 * Deliver IPI to all processors except the current one.
 *
 * The sparc64 architecture does not support any group addressing
 * which is found, for instance, on ia32 and amd64. Therefore we
 * need to simulate the broadcast by sending the message to
 * all target processors step by step.
 *
 * We assume that interrupts are disabled.
 *
 * @param ipi IPI number.
 */
void ipi_broadcast_arch(int ipi)
{
    int i;
   
    void (* func)(void);
   
    switch (ipi) {
    case IPI_TLB_SHOOTDOWN:
        func = tlb_shootdown_ipi_recv;
        break;
#if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE)))
    case IPI_DCACHE_SHOOTDOWN:
        func = dcache_shootdown_ipi_recv;
        break;
#endif
    default:
        panic("Unknown IPI (%d).\n", ipi);
        break;
    }
   
    /*
     * As long as we don't support hot-plugging
     * or hot-unplugging of CPUs, we can walk
     * the cpus array and read processor's MID
     * without locking.
     */
   
    for (i = 0; i < config.cpu_active; i++) {
        if (&cpus[i] == CPU)
            continue;       /* skip the current CPU */
 
        cross_call(cpus[i].arch.mid, func);
    }
}
 
/** @}
 */
 

Rev 2089	Rev 2134
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <smp/ipi.h>	35	#include <smp/ipi.h>
36	#include <cpu.h>	36	#include <cpu.h>
37	#include <arch.h>	37	#include <arch.h>
38	#include <arch/cpu.h>	38	#include <arch/cpu.h>
39	#include <arch/asm.h>	39	#include <arch/asm.h>
40	#include <config.h>	40	#include <config.h>
41	#include <mm/tlb.h>	41	#include <mm/tlb.h>
-		42	#include <arch/mm/cache.h>
42	#include <arch/interrupt.h>	43	#include <arch/interrupt.h>
43	#include <arch/trap/interrupt.h>	44	#include <arch/trap/interrupt.h>
44	#include <arch/barrier.h>	45	#include <arch/barrier.h>
45	#include <preemption.h>	46	#include <preemption.h>
46	#include <time/delay.h>	47	#include <time/delay.h>
47	#include <panic.h>	48	#include <panic.h>
48		49
49	/** Invoke function on another processor.	50	/** Invoke function on another processor.
50	*	51	*
51	* Currently, only functions without arguments are supported.	52	* Currently, only functions without arguments are supported.
52	* Supporting more arguments in the future should be no big deal.	53	* Supporting more arguments in the future should be no big deal.
53	*	54	*
54	* Interrupts must be disabled prior to this call.	55	* Interrupts must be disabled prior to this call.
55	*	56	*
56	* @param mid MID of the target processor.	57	* @param mid MID of the target processor.
57	* @param func Function to be invoked.	58	* @param func Function to be invoked.
58	*/	59	*/
59	static void cross_call(int mid, void (* func)(void))	60	static void cross_call(int mid, void (* func)(void))
60	{	61	{
61	uint64_t status;	62	uint64_t status;
62	bool done;	63	bool done;
63		64
64	/*	65	/*
65	* This function might enable interrupts for a while.	66	* This function might enable interrupts for a while.
66	* In order to prevent migration to another processor,	67	* In order to prevent migration to another processor,
67	* we explicitly disable preemption.	68	* we explicitly disable preemption.
68	*/	69	*/
69		70
70	preemption_disable();	71	preemption_disable();
71		72
72	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	73	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
73	if (status & INTR_DISPATCH_STATUS_BUSY)	74	if (status & INTR_DISPATCH_STATUS_BUSY)
74	panic("Interrupt Dispatch Status busy bit set\n");	75	panic("Interrupt Dispatch Status busy bit set\n");
75		76
76	do {	77	do {
77	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)	78	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t)
78	func);	79	func);
79	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);	80	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
80	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);	81	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
81	asi_u64_write(ASI_UDB_INTR_W, (mid <<	82	asi_u64_write(ASI_UDB_INTR_W,
82	INTR_VEC_DISPATCH_MID_SHIFT) \| ASI_UDB_INTR_W_DISPATCH,	83	(mid << INTR_VEC_DISPATCH_MID_SHIFT) \|
83	0);	84	ASI_UDB_INTR_W_DISPATCH, 0);
84		85
85	membar();	86	membar();
86		87
87	do {	88	do {
88	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	89	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
89	} while (status & INTR_DISPATCH_STATUS_BUSY);	90	} while (status & INTR_DISPATCH_STATUS_BUSY);
90		91
91	done = !(status & INTR_DISPATCH_STATUS_NACK);	92	done = !(status & INTR_DISPATCH_STATUS_NACK);
92	if (!done) {	93	if (!done) {
93	/*	94	/*
94	* Prevent deadlock.	95	* Prevent deadlock.
95	*/	96	*/
96	(void) interrupts_enable();	97	(void) interrupts_enable();
97	delay(20 + (tick_read() & 0xff));	98	delay(20 + (tick_read() & 0xff));
98	(void) interrupts_disable();	99	(void) interrupts_disable();
99	}	100	}
100	} while (done);	101	} while (done);
101		102
102	preemption_enable();	103	preemption_enable();
103	}	104	}
104		105
105	/*	106	/*
106	* Deliver IPI to all processors except the current one.	107	* Deliver IPI to all processors except the current one.
107	*	108	*
108	* The sparc64 architecture does not support any group addressing	109	* The sparc64 architecture does not support any group addressing
109	* which is found, for instance, on ia32 and amd64. Therefore we	110	* which is found, for instance, on ia32 and amd64. Therefore we
110	* need to simulate the broadcast by sending the message to	111	* need to simulate the broadcast by sending the message to
111	* all target processors step by step.	112	* all target processors step by step.
112	*	113	*
113	* We assume that interrupts are disabled.	114	* We assume that interrupts are disabled.
114	*	115	*
115	* @param ipi IPI number.	116	* @param ipi IPI number.
116	*/	117	*/
117	void ipi_broadcast_arch(int ipi)	118	void ipi_broadcast_arch(int ipi)
118	{	119	{
119	int i;	120	int i;
120		121
121	void (* func)(void);	122	void (* func)(void);
122		123
123	switch (ipi) {	124	switch (ipi) {
124	case IPI_TLB_SHOOTDOWN:	125	case IPI_TLB_SHOOTDOWN:
125	func = tlb_shootdown_ipi_recv;	126	func = tlb_shootdown_ipi_recv;
126	break;	127	break;
-		128	#if (defined(CONFIG_SMP) && (defined(CONFIG_VIRT_IDX_DCACHE)))
-		129	case IPI_DCACHE_SHOOTDOWN:
-		130	func = dcache_shootdown_ipi_recv;
-		131	break;
-		132	#endif
127	default:	133	default:
128	panic("Unknown IPI (%d).\n", ipi);	134	panic("Unknown IPI (%d).\n", ipi);
129	break;	135	break;
130	}	136	}
131		137
132	/*	138	/*
133	* As long as we don't support hot-plugging	139	* As long as we don't support hot-plugging
134	* or hot-unplugging of CPUs, we can walk	140	* or hot-unplugging of CPUs, we can walk
135	* the cpus array and read processor's MID	141	* the cpus array and read processor's MID
136	* without locking.	142	* without locking.
137	*/	143	*/
138		144
139	for (i = 0; i < config.cpu_active; i++) {	145	for (i = 0; i < config.cpu_active; i++) {
140	if (&cpus[i] == CPU)	146	if (&cpus[i] == CPU)
141	continue; /* skip the current CPU */	147	continue; /* skip the current CPU */
142		148
143	cross_call(cpus[i].arch.mid, func);	149	cross_call(cpus[i].arch.mid, func);
144	}	150	}
145	}	151	}
146		152
147	/** @}	153	/** @}
148	*/	154	*/
149		155

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/smp/ipi.c – Rev 2089 → 2134