WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/smp/ipi.c


/*
 * Copyright (C) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#include <smp/ipi.h>
#include <cpu.h>
#include <arch/cpu.h>
#include <arch/asm.h>
#include <config.h>
#include <mm/tlb.h>
#include <arch/mm/cache.h>
#include <arch/interrupt.h>
#include <arch/trap/interrupt.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <time/delay.h>
#include <panic.h>
 
/** Invoke function on another processor.
 *
 * Currently, only functions without arguments are supported.
 * Supporting more arguments in the future should be no big deal.
 *
 * Interrupts must be disabled prior to this call.
 *
 * @param mid MID of the target processor.
 * @param func Function to be invoked.
 */
static void cross_call(int mid, void (* func)(void))
{
    uint64_t status;
    bool done;
 
    /*
     * This functin might enable interrupts for a while.
     * In order to prevent migration to another processor,
     * we explicitly disable preemption.
     */
   
    preemption_disable();
   
    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
    if (status & INTR_DISPATCH_STATUS_BUSY)
        panic("Interrupt Dispatch Status busy bit set\n");
   
    do {
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
        asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0);
   
        membar();
       
        do {
            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
        } while (status & INTR_DISPATCH_STATUS_BUSY);
       
        done = !(status & INTR_DISPATCH_STATUS_NACK);
        if (!done) {
            /*
             * Prevent deadlock.
             */        
            (void) interrupts_enable();
            delay(20 + (tick_read() & 0xff));
            (void) interrupts_disable();
        }
    } while (done);
   
    preemption_enable();
}
 
/*
 * Deliver IPI to all processors except the current one.
 *
 * The sparc64 architecture does not support any group addressing
 * which is found, for instance, on ia32 and amd64. Therefore we
 * need to simulate the broadcast by sending the message to
 * all target processors step by step.
 *
 * We assume that interrupts are disabled.
 *
 * @param ipi IPI number.
 */
void ipi_broadcast_arch(int ipi)
{
    int i;
   
    void (* func)(void);
   
    switch (ipi) {
    case IPI_TLB_SHOOTDOWN:
        func = tlb_shootdown_ipi_recv;
        break;
    case IPI_DCACHE_SHOOTDOWN:
        func = dcache_shootdown_ipi_recv;
        break;
    default:
        panic("Unknown IPI (%d).\n", ipi);
        break;
    }
   
    /*
     * As long as we don't support hot-plugging
     * or hot-unplugging of CPUs, we can walk
     * the cpus array and read processor's MID
     * without locking.
     */
   
    for (i = 0; i < config.cpu_active; i++) {
        if (&cpus[i] == CPU)
            continue;       /* skip the current CPU */
 
        cross_call(cpus[i].arch.mid, func);
    }
}
 
/** @}
 */
 

Rev 1904	Rev 2009
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <smp/ipi.h>	35	#include <smp/ipi.h>
36	#include <cpu.h>	36	#include <cpu.h>
37	#include <arch/cpu.h>	37	#include <arch/cpu.h>
38	#include <arch/asm.h>	38	#include <arch/asm.h>
39	#include <config.h>	39	#include <config.h>
40	#include <mm/tlb.h>	40	#include <mm/tlb.h>
-		41	#include <arch/mm/cache.h>
41	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
42	#include <arch/trap/interrupt.h>	43	#include <arch/trap/interrupt.h>
43	#include <arch/barrier.h>	44	#include <arch/barrier.h>
44	#include <preemption.h>	45	#include <preemption.h>
45	#include <time/delay.h>	46	#include <time/delay.h>
46	#include <panic.h>	47	#include <panic.h>
47		48
48	/** Invoke function on another processor.	49	/** Invoke function on another processor.
49	*	50	*
50	* Currently, only functions without arguments are supported.	51	* Currently, only functions without arguments are supported.
51	* Supporting more arguments in the future should be no big deal.	52	* Supporting more arguments in the future should be no big deal.
52	*	53	*
53	* Interrupts must be disabled prior to this call.	54	* Interrupts must be disabled prior to this call.
54	*	55	*
55	* @param mid MID of the target processor.	56	* @param mid MID of the target processor.
56	* @param func Function to be invoked.	57	* @param func Function to be invoked.
57	*/	58	*/
58	static void cross_call(int mid, void (* func)(void))	59	static void cross_call(int mid, void (* func)(void))
59	{	60	{
60	uint64_t status;	61	uint64_t status;
61	bool done;	62	bool done;
62		63
63	/*	64	/*
64	* This functin might enable interrupts for a while.	65	* This functin might enable interrupts for a while.
65	* In order to prevent migration to another processor,	66	* In order to prevent migration to another processor,
66	* we explicitly disable preemption.	67	* we explicitly disable preemption.
67	*/	68	*/
68		69
69	preemption_disable();	70	preemption_disable();
70		71
71	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	72	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
72	if (status & INTR_DISPATCH_STATUS_BUSY)	73	if (status & INTR_DISPATCH_STATUS_BUSY)
73	panic("Interrupt Dispatch Status busy bit set\n");	74	panic("Interrupt Dispatch Status busy bit set\n");
74		75
75	do {	76	do {
76	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);	77	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
77	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);	78	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
78	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);	79	asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
79	asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) \| ASI_UDB_INTR_W_DISPATCH, 0);	80	asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) \| ASI_UDB_INTR_W_DISPATCH, 0);
80		81
81	membar();	82	membar();
82		83
83	do {	84	do {
84	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);	85	status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
85	} while (status & INTR_DISPATCH_STATUS_BUSY);	86	} while (status & INTR_DISPATCH_STATUS_BUSY);
86		87
87	done = !(status & INTR_DISPATCH_STATUS_NACK);	88	done = !(status & INTR_DISPATCH_STATUS_NACK);
88	if (!done) {	89	if (!done) {
89	/*	90	/*
90	* Prevent deadlock.	91	* Prevent deadlock.
91	*/	92	*/
92	(void) interrupts_enable();	93	(void) interrupts_enable();
93	delay(20 + (tick_read() & 0xff));	94	delay(20 + (tick_read() & 0xff));
94	(void) interrupts_disable();	95	(void) interrupts_disable();
95	}	96	}
96	} while (done);	97	} while (done);
97		98
98	preemption_enable();	99	preemption_enable();
99	}	100	}
100		101
101	/*	102	/*
102	* Deliver IPI to all processors except the current one.	103	* Deliver IPI to all processors except the current one.
103	*	104	*
104	* The sparc64 architecture does not support any group addressing	105	* The sparc64 architecture does not support any group addressing
105	* which is found, for instance, on ia32 and amd64. Therefore we	106	* which is found, for instance, on ia32 and amd64. Therefore we
106	* need to simulate the broadcast by sending the message to	107	* need to simulate the broadcast by sending the message to
107	* all target processors step by step.	108	* all target processors step by step.
108	*	109	*
109	* We assume that interrupts are disabled.	110	* We assume that interrupts are disabled.
110	*	111	*
111	* @param ipi IPI number.	112	* @param ipi IPI number.
112	*/	113	*/
113	void ipi_broadcast_arch(int ipi)	114	void ipi_broadcast_arch(int ipi)
114	{	115	{
115	int i;	116	int i;
116		117
117	void (* func)(void);	118	void (* func)(void);
118		119
119	switch (ipi) {	120	switch (ipi) {
120	case IPI_TLB_SHOOTDOWN:	121	case IPI_TLB_SHOOTDOWN:
121	func = tlb_shootdown_ipi_recv;	122	func = tlb_shootdown_ipi_recv;
122	break;	123	break;
-		124	case IPI_DCACHE_SHOOTDOWN:
-		125	func = dcache_shootdown_ipi_recv;
-		126	break;
123	default:	127	default:
124	panic("Unknown IPI (%d).\n", ipi);	128	panic("Unknown IPI (%d).\n", ipi);
125	break;	129	break;
126	}	130	}
127		131
128	/*	132	/*
129	* As long as we don't support hot-plugging	133	* As long as we don't support hot-plugging
130	* or hot-unplugging of CPUs, we can walk	134	* or hot-unplugging of CPUs, we can walk
131	* the cpus array and read processor's MID	135	* the cpus array and read processor's MID
132	* without locking.	136	* without locking.
133	*/	137	*/
134		138
135	for (i = 0; i < config.cpu_active; i++) {	139	for (i = 0; i < config.cpu_active; i++) {
136	if (&cpus[i] == CPU)	140	if (&cpus[i] == CPU)
137	continue; /* skip the current CPU */	141	continue; /* skip the current CPU */
138		142
139	cross_call(cpus[i].arch.mid, func);	143	cross_call(cpus[i].arch.mid, func);
140	}	144	}
141	}	145	}
142		146
143	/** @}	147	/** @}
144	*/	148	*/
145		149

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(root)/trunk/kernel/arch/sparc64/src/smp/ipi.c – Rev 1904 → 2009