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/*
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/*
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 * Copyright (C) 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64
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/** @addtogroup sparc64
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <smp/ipi.h>
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#include <smp/ipi.h>
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#include <cpu.h>
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#include <arch/cpu.h>
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#include <arch/asm.h>
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#include <config.h>
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#include <mm/tlb.h>
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#include <arch/interrupt.h>
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#include <arch/trap/interrupt.h>
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#include <arch/barrier.h>
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#include <preemption.h>
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#include <time/delay.h>
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#include <panic.h>
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/** Invoke function on another processor.
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 *
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 * Currently, only functions without arguments are supported.
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 * Supporting more arguments in the future should be no big deal.
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 *
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 * Interrupts must be disabled prior to this call.
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 *
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 * @param mid MID of the target processor.
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 * @param func Function to be invoked.
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 */
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static void cross_call(int mid, void (* func)(void))
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{
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    uint64_t status;
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    bool done;
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    /*
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     * This functin might enable interrupts for a while.
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     * In order to prevent migration to another processor,
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     * we explicitly disable preemption.
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     */
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    preemption_disable();
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    status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
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    if (status & INTR_DISPATCH_STATUS_BUSY)
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        panic("Interrupt Dispatch Status busy bit set\n");
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    do {
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
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        asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
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        asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0);
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        membar();
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        do {
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            status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
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        } while (status & INTR_DISPATCH_STATUS_BUSY);
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        done = !(status & INTR_DISPATCH_STATUS_NACK);
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        if (!done) {
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            /*
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             * Prevent deadlock.
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             */        
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            (void) interrupts_enable();
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            delay(20 + (tick_read() & 0xff));
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            (void) interrupts_disable();
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        }
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    } while (done);
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    preemption_enable();
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}
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/*
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 * Deliver IPI to all processors except the current one.
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 *
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 * The sparc64 architecture does not support any group addressing
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 * which is found, for instance, on ia32 and amd64. Therefore we
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 * need to simulate the broadcast by sending the message to
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 * all target processors step by step.
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 *
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 * We assume that interrupts are disabled.
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 *
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 * @param ipi IPI number.
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 */
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void ipi_broadcast_arch(int ipi)
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void ipi_broadcast_arch(int ipi)
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{
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{
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    int i;
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    void (* func)(void);
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    switch (ipi) {
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    case IPI_TLB_SHOOTDOWN:
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        func = tlb_shootdown_ipi_recv;
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        break;
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    default:
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        panic("Unknown IPI (%d).\n", ipi);
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        break;
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    }
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    /*
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     * As long as we don't support hot-plugging
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     * or hot-unplugging of CPUs, we can walk
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     * the cpus array and read processor's MID
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     * without locking.
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    /* TODO */
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     */
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    for (i = 0; i < config.cpu_active; i++) {
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        if (&cpus[i] == CPU)
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            continue;       /* skip the current CPU */
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        cross_call(cpus[i].arch.mid, func);
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    }
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}
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}
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/** @}
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/** @}
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 */
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 */
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