WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tsb.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tsb.h>
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
#include <arch/barrier.h>
#include <mm/as.h>
#include <arch/types.h>
#include <macros.h>
#include <debug.h>
 
#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
 
/** Invalidate portion of TSB.
 *
 * We assume that the address space is already locked. Note that respective
 * portions of both TSBs are invalidated at a time.
 *
 * @param as Address space.
 * @param page First page to invalidate in TSB.
 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
 *  whole TSB.
 */
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
{
    index_t i0, i;
    count_t cnt;
   
    ASSERT(as->arch.itsb && as->arch.dtsb);
   
    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
        cnt = ITSB_ENTRY_COUNT;
    else
        cnt = pages * 2;
   
    for (i = 0; i < cnt; i++) {
        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
    }
}
 
/** Copy software PTE to ITSB.
 *
 * @param t     Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
 */
void itsb_pte_copy(pte_t *t, index_t index)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    tsb = &as->arch.itsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
        VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** Copy software PTE to DTSB.
 *
 * @param t Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro    If true, the mapping is copied read-only.
 */
void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    tsb = &as->arch.dtsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
        VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    tsb->data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.w = ro ? false : t->w;
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** @}
 */
 

Rev 2141	Rev 2161
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tsb.h>	35	#include <arch/mm/tsb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/mm/page.h>	37	#include <arch/mm/page.h>
38	#include <arch/barrier.h>	38	#include <arch/barrier.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <macros.h>	41	#include <macros.h>
42	#include <debug.h>	42	#include <debug.h>
43		43
44	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)	44	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
45		45
46	/** Invalidate portion of TSB.	46	/** Invalidate portion of TSB.
47	*	47	*
48	* We assume that the address space is already locked. Note that respective	48	* We assume that the address space is already locked. Note that respective
49	* portions of both TSBs are invalidated at a time.	49	* portions of both TSBs are invalidated at a time.
50	*	50	*
51	* @param as Address space.	51	* @param as Address space.
52	* @param page First page to invalidate in TSB.	52	* @param page First page to invalidate in TSB.
53	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the	53	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the
54	* whole TSB.	54	* whole TSB.
55	*/	55	*/
56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)	56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
57	{	57	{
58	index_t i0, i;	58	index_t i0, i;
59	count_t cnt;	59	count_t cnt;
60		60
61	ASSERT(as->arch.itsb && as->arch.dtsb);	61	ASSERT(as->arch.itsb && as->arch.dtsb);
62		62
63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;	63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
64	cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT);	64	if (pages == (count_t) -1 \|\| (pages * 2) > ITSB_ENTRY_COUNT)
-		65	cnt = ITSB_ENTRY_COUNT;
-		66	else
-		67	cnt = pages * 2;
65		68
66	for (i = 0; i < cnt; i++) {	69	for (i = 0; i < cnt; i++) {
67	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =	70	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
68	true;	71	true;
69	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =	72	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
70	true;	73	true;
71	}	74	}
72	}	75	}
73		76
74	/** Copy software PTE to ITSB.	77	/** Copy software PTE to ITSB.
75	*	78	*
76	* @param t Software PTE.	79	* @param t Software PTE.
77	* @param index Zero if lower 8K-subpage, one if higher 8K subpage.	80	* @param index Zero if lower 8K-subpage, one if higher 8K subpage.
78	*/	81	*/
79	void itsb_pte_copy(pte_t *t, index_t index)	82	void itsb_pte_copy(pte_t *t, index_t index)
80	{	83	{
81	as_t *as;	84	as_t *as;
82	tsb_entry_t *tsb;	85	tsb_entry_t *tsb;
83	index_t entry;	86	index_t entry;
84		87
85	as = t->as;	88	as = t->as;
86	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	89	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
87	tsb = &as->arch.itsb[entry];	90	tsb = &as->arch.itsb[entry];
88		91
89	/*	92	/*
90	* We use write barriers to make sure that the TSB load	93	* We use write barriers to make sure that the TSB load
91	* won't use inconsistent data or that the fault will	94	* won't use inconsistent data or that the fault will
92	* be repeated.	95	* be repeated.
93	*/	96	*/
94		97
95	tsb->tag.invalid = true; /* invalidate the entry	98	tsb->tag.invalid = true; /* invalidate the entry
96	* (tag target has this	99	* (tag target has this
97	* set to 0) */	100	* set to 0) */
98		101
99	write_barrier();	102	write_barrier();
100		103
101	tsb->tag.context = as->asid;	104	tsb->tag.context = as->asid;
102	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	105	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
103	VA_TAG_PAGE_SHIFT;	106	VA_TAG_PAGE_SHIFT;
104	tsb->data.value = 0;	107	tsb->data.value = 0;
105	tsb->data.size = PAGESIZE_8K;	108	tsb->data.size = PAGESIZE_8K;
106	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	109	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
107	tsb->data.cp = t->c;	110	tsb->data.cp = t->c;
108	tsb->data.p = t->k; /* p as privileged */	111	tsb->data.p = t->k; /* p as privileged */
109	tsb->data.v = t->p;	112	tsb->data.v = t->p;
110		113
111	write_barrier();	114	write_barrier();
112		115
113	tsb->tag.invalid = false; /* mark the entry as valid */	116	tsb->tag.invalid = false; /* mark the entry as valid */
114	}	117	}
115		118
116	/** Copy software PTE to DTSB.	119	/** Copy software PTE to DTSB.
117	*	120	*
118	* @param t Software PTE.	121	* @param t Software PTE.
119	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.	122	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
120	* @param ro If true, the mapping is copied read-only.	123	* @param ro If true, the mapping is copied read-only.
121	*/	124	*/
122	void dtsb_pte_copy(pte_t *t, index_t index, bool ro)	125	void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
123	{	126	{
124	as_t *as;	127	as_t *as;
125	tsb_entry_t *tsb;	128	tsb_entry_t *tsb;
126	index_t entry;	129	index_t entry;
127		130
128	as = t->as;	131	as = t->as;
129	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;	132	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
130	tsb = &as->arch.dtsb[entry];	133	tsb = &as->arch.dtsb[entry];
131		134
132	/*	135	/*
133	* We use write barriers to make sure that the TSB load	136	* We use write barriers to make sure that the TSB load
134	* won't use inconsistent data or that the fault will	137	* won't use inconsistent data or that the fault will
135	* be repeated.	138	* be repeated.
136	*/	139	*/
137		140
138	tsb->tag.invalid = true; /* invalidate the entry	141	tsb->tag.invalid = true; /* invalidate the entry
139	* (tag target has this	142	* (tag target has this
140	* set to 0) */	143	* set to 0) */
141		144
142	write_barrier();	145	write_barrier();
143		146
144	tsb->tag.context = as->asid;	147	tsb->tag.context = as->asid;
145	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>	148	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
146	VA_TAG_PAGE_SHIFT;	149	VA_TAG_PAGE_SHIFT;
147	tsb->data.value = 0;	150	tsb->data.value = 0;
148	tsb->data.size = PAGESIZE_8K;	151	tsb->data.size = PAGESIZE_8K;
149	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;	152	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
150	tsb->data.cp = t->c;	153	tsb->data.cp = t->c;
151	#ifdef CONFIG_VIRT_IDX_DCACHE	154	#ifdef CONFIG_VIRT_IDX_DCACHE
152	tsb->data.cv = t->c;	155	tsb->data.cv = t->c;
153	#endif /* CONFIG_VIRT_IDX_DCACHE */	156	#endif /* CONFIG_VIRT_IDX_DCACHE */
154	tsb->data.p = t->k; /* p as privileged */	157	tsb->data.p = t->k; /* p as privileged */
155	tsb->data.w = ro ? false : t->w;	158	tsb->data.w = ro ? false : t->w;
156	tsb->data.v = t->p;	159	tsb->data.v = t->p;
157		160
158	write_barrier();	161	write_barrier();
159		162
160	tsb->tag.invalid = true; /* mark the entry as valid */	163	tsb->tag.invalid = false; /* mark the entry as valid */
161	}	164	}
162		165
163	/** @}	166	/** @}
164	*/	167	*/
165		168

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/mm/tsb.c – Rev 2141 → 2161