WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tsb.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tsb.h>
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
#include <arch/barrier.h>
#include <mm/as.h>
#include <arch/types.h>
#include <macros.h>
#include <debug.h>
 
#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
 
/** Invalidate portion of TSB.
 *
 * We assume that the address space is already locked. Note that respective
 * portions of both TSBs are invalidated at a time.
 *
 * @param as Address space.
 * @param page First page to invalidate in TSB.
 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
 *  whole TSB.
 */
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
{
    index_t i0, i;
    count_t cnt;
   
    ASSERT(as->arch.itsb && as->arch.dtsb);
   
    i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
    cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT);
   
    for (i = 0; i < cnt; i++) {
        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
            true;
    }
}
 
/** Copy software PTE to ITSB.
 *
 * @param t     Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
 */
void itsb_pte_copy(pte_t *t, index_t index)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    tsb = &as->arch.itsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
        VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** Copy software PTE to DTSB.
 *
 * @param t Software PTE.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro    If true, the mapping is copied read-only.
 */
void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
{
    as_t *as;
    tsb_entry_t *tsb;
    index_t entry;
   
    as = t->as;
    entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
    tsb = &as->arch.dtsb[entry];
 
    /*
     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
        VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
    tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    tsb->data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.w = ro ? false : t->w;
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = true;    /* mark the entry as valid */
}
 
/** @}
 */
 

Rev 2089	Rev 2141
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tsb.h>	35	#include <arch/mm/tsb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
-		37	#include <arch/mm/page.h>
37	#include <arch/barrier.h>	38	#include <arch/barrier.h>
38	#include <mm/as.h>	39	#include <mm/as.h>
39	#include <arch/types.h>	40	#include <arch/types.h>
40	#include <macros.h>	41	#include <macros.h>
41	#include <debug.h>	42	#include <debug.h>
42		43
43	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - PAGE_WIDTH)) - 1)	44	#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
44		45
45	/** Invalidate portion of TSB.	46	/** Invalidate portion of TSB.
46	*	47	*
47	* We assume that the address space is already locked. Note that respective	48	* We assume that the address space is already locked. Note that respective
48	* portions of both TSBs are invalidated at a time.	49	* portions of both TSBs are invalidated at a time.
49	*	50	*
50	* @param as Address space.	51	* @param as Address space.
51	* @param page First page to invalidate in TSB.	52	* @param page First page to invalidate in TSB.
52	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the	53	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the
53	* whole TSB.	54	* whole TSB.
54	*/	55	*/
55	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)	56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
56	{	57	{
57	index_t i0, i;	58	index_t i0, i;
58	count_t cnt;	59	count_t cnt;
59		60
60	ASSERT(as->arch.itsb && as->arch.dtsb);	61	ASSERT(as->arch.itsb && as->arch.dtsb);
61		62
62	i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;	63	i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
63	cnt = min(pages, ITSB_ENTRY_COUNT);	64	cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT);
64		65
65	for (i = 0; i < cnt; i++) {	66	for (i = 0; i < cnt; i++) {
66	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =	67	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
67	true;	68	true;
68	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =	69	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
69	true;	70	true;
70	}	71	}
71	}	72	}
72		73
73	/** Copy software PTE to ITSB.	74	/** Copy software PTE to ITSB.
74	*	75	*
75	* @param t Software PTE.	76	* @param t Software PTE.
-		77	* @param index Zero if lower 8K-subpage, one if higher 8K subpage.
76	*/	78	*/
77	void itsb_pte_copy(pte_t *t)	79	void itsb_pte_copy(pte_t *t, index_t index)
78	{	80	{
79	as_t *as;	81	as_t *as;
80	tsb_entry_t *tsb;	82	tsb_entry_t *tsb;
-		83	index_t entry;
81		84
82	as = t->as;	85	as = t->as;
83	tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];	86	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		87	tsb = &as->arch.itsb[entry];
84		88
85	/*	89	/*
86	* We use write barriers to make sure that the TSB load	90	* We use write barriers to make sure that the TSB load
87	* won't use inconsistent data or that the fault will	91	* won't use inconsistent data or that the fault will
88	* be repeated.	92	* be repeated.
89	*/	93	*/
90		94
91	tsb->tag.invalid = true; /* invalidate the entry	95	tsb->tag.invalid = true; /* invalidate the entry
92	* (tag target has this	96	* (tag target has this
93	* set to 0) */	97	* set to 0) */
94		98
95	write_barrier();	99	write_barrier();
96		100
97	tsb->tag.context = as->asid;	101	tsb->tag.context = as->asid;
98	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;	102	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
-		103	VA_TAG_PAGE_SHIFT;
99	tsb->data.value = 0;	104	tsb->data.value = 0;
100	tsb->data.size = PAGESIZE_8K;	105	tsb->data.size = PAGESIZE_8K;
101	tsb->data.pfn = t->frame >> FRAME_WIDTH;	106	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
102	tsb->data.cp = t->c;	107	tsb->data.cp = t->c;
103	tsb->data.p = t->k; /* p as privileged */	108	tsb->data.p = t->k; /* p as privileged */
104	tsb->data.v = t->p;	109	tsb->data.v = t->p;
105		110
106	write_barrier();	111	write_barrier();
107		112
108	tsb->tag.invalid = false; /* mark the entry as valid */	113	tsb->tag.invalid = false; /* mark the entry as valid */
109	}	114	}
110		115
111	/** Copy software PTE to DTSB.	116	/** Copy software PTE to DTSB.
112	*	117	*
113	* @param t Software PTE.	118	* @param t Software PTE.
-		119	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
114	* @param ro If true, the mapping is copied read-only.	120	* @param ro If true, the mapping is copied read-only.
115	*/	121	*/
116	void dtsb_pte_copy(pte_t *t, bool ro)	122	void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
117	{	123	{
118	as_t *as;	124	as_t *as;
119	tsb_entry_t *tsb;	125	tsb_entry_t *tsb;
-		126	index_t entry;
120		127
121	as = t->as;	128	as = t->as;
122	tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];	129	entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-		130	tsb = &as->arch.dtsb[entry];
123		131
124	/*	132	/*
125	* We use write barriers to make sure that the TSB load	133	* We use write barriers to make sure that the TSB load
126	* won't use inconsistent data or that the fault will	134	* won't use inconsistent data or that the fault will
127	* be repeated.	135	* be repeated.
128	*/	136	*/
129		137
130	tsb->tag.invalid = true; /* invalidate the entry	138	tsb->tag.invalid = true; /* invalidate the entry
131	* (tag target has this	139	* (tag target has this
132	* set to 0) */	140	* set to 0) */
133		141
134	write_barrier();	142	write_barrier();
135		143
136	tsb->tag.context = as->asid;	144	tsb->tag.context = as->asid;
137	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;	145	tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
-		146	VA_TAG_PAGE_SHIFT;
138	tsb->data.value = 0;	147	tsb->data.value = 0;
139	tsb->data.size = PAGESIZE_8K;	148	tsb->data.size = PAGESIZE_8K;
140	tsb->data.pfn = t->frame >> FRAME_WIDTH;	149	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
141	tsb->data.cp = t->c;	150	tsb->data.cp = t->c;
142	#ifdef CONFIG_VIRT_IDX_DCACHE	151	#ifdef CONFIG_VIRT_IDX_DCACHE
143	tsb->data.cv = t->c;	152	tsb->data.cv = t->c;
144	#endif /* CONFIG_VIRT_IDX_DCACHE */	153	#endif /* CONFIG_VIRT_IDX_DCACHE */
145	tsb->data.p = t->k; /* p as privileged */	154	tsb->data.p = t->k; /* p as privileged */
146	tsb->data.w = ro ? false : t->w;	155	tsb->data.w = ro ? false : t->w;
147	tsb->data.v = t->p;	156	tsb->data.v = t->p;
148		157
149	write_barrier();	158	write_barrier();
150		159
151	tsb->tag.invalid = true; /* mark the entry as valid */	160	tsb->tag.invalid = true; /* mark the entry as valid */
152	}	161	}
153		162
154	/** @}	163	/** @}
155	*/	164	*/
156		165

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/mm/tsb.c – Rev 2089 → 2141