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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (C) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tsb.h> |
35 | #include <arch/mm/tsb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/barrier.h> |
37 | #include <arch/barrier.h> |
38 | #include <mm/as.h> |
38 | #include <mm/as.h> |
39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
40 | #include <typedefs.h> |
40 | #include <typedefs.h> |
41 | #include <macros.h> |
41 | #include <macros.h> |
42 | #include <debug.h> |
42 | #include <debug.h> |
43 | 43 | ||
44 | #define TSB_INDEX_MASK ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1) |
44 | #define TSB_INDEX_MASK ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1) |
45 | 45 | ||
46 | /** Invalidate portion of TSB. |
46 | /** Invalidate portion of TSB. |
47 | * |
47 | * |
48 | * We assume that the address space is already locked. |
48 | * We assume that the address space is already locked. |
49 | * Note that respective portions of both TSBs |
49 | * Note that respective portions of both TSBs |
50 | * are invalidated at a time. |
50 | * are invalidated at a time. |
51 | * |
51 | * |
52 | * @param as Address space. |
52 | * @param as Address space. |
53 | * @param page First page to invalidate in TSB. |
53 | * @param page First page to invalidate in TSB. |
54 | * @param pages Number of pages to invalidate. |
54 | * @param pages Number of pages to invalidate. |
55 | * Value of (count_t) -1 means the whole TSB. |
55 | * Value of (count_t) -1 means the whole TSB. |
56 | */ |
56 | */ |
57 | void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
57 | void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
58 | { |
58 | { |
59 | index_t i0, i; |
59 | index_t i0, i; |
60 | count_t cnt; |
60 | count_t cnt; |
61 | 61 | ||
62 | ASSERT(as->arch.itsb && as->arch.dtsb); |
62 | ASSERT(as->arch.itsb && as->arch.dtsb); |
63 | 63 | ||
64 | i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK; |
64 | i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK; |
65 | cnt = min(pages, ITSB_ENTRY_COUNT); |
65 | cnt = min(pages, ITSB_ENTRY_COUNT); |
66 | 66 | ||
67 | for (i = 0; i < cnt; i++) { |
67 | for (i = 0; i < cnt; i++) { |
68 | as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true; |
68 | as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true; |
69 | as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true; |
69 | as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true; |
70 | } |
70 | } |
71 | } |
71 | } |
72 | 72 | ||
73 | /** Copy software PTE to ITSB. |
73 | /** Copy software PTE to ITSB. |
74 | * |
74 | * |
75 | * @param t Software PTE. |
75 | * @param t Software PTE. |
76 | */ |
76 | */ |
77 | void itsb_pte_copy(pte_t *t) |
77 | void itsb_pte_copy(pte_t *t) |
78 | { |
78 | { |
79 | as_t *as; |
79 | as_t *as; |
80 | tsb_entry_t *tsb; |
80 | tsb_entry_t *tsb; |
81 | 81 | ||
82 | as = t->as; |
82 | as = t->as; |
83 | tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
83 | tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
84 | 84 | ||
85 | /* |
85 | /* |
86 | * We use write barriers to make sure that the TSB load |
86 | * We use write barriers to make sure that the TSB load |
87 | * won't use inconsistent data or that the fault will |
87 | * won't use inconsistent data or that the fault will |
88 | * be repeated. |
88 | * be repeated. |
89 | */ |
89 | */ |
90 | 90 | ||
91 | tsb->tag.invalid = true; /* invalidate the entry |
91 | tsb->tag.invalid = true; /* invalidate the entry |
92 | * (tag target has this |
92 | * (tag target has this |
93 | * set to 0) */ |
93 | * set to 0) */ |
94 | 94 | ||
95 | write_barrier(); |
95 | write_barrier(); |
96 | 96 | ||
97 | tsb->tag.context = as->asid; |
97 | tsb->tag.context = as->asid; |
98 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
98 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
99 | tsb->data.value = 0; |
99 | tsb->data.value = 0; |
100 | tsb->data.size = PAGESIZE_8K; |
100 | tsb->data.size = PAGESIZE_8K; |
101 | tsb->data.pfn = t->frame >> FRAME_WIDTH; |
101 | tsb->data.pfn = t->frame >> FRAME_WIDTH; |
102 | tsb->data.cp = t->c; |
102 | tsb->data.cp = t->c; |
103 | #ifdef CONFIG_VIRT_IDX_CACHE |
- | |
104 | tsb->data.cv = t->c; |
- | |
105 | #endif /* CONFIG_VIRT_IDX_CACHE */ |
- | |
106 | tsb->data.p = t->k; /* p as privileged */ |
103 | tsb->data.p = t->k; /* p as privileged */ |
107 | tsb->data.v = t->p; |
104 | tsb->data.v = t->p; |
108 | 105 | ||
109 | write_barrier(); |
106 | write_barrier(); |
110 | 107 | ||
111 | tsb->tag.invalid = false; /* mark the entry as valid */ |
108 | tsb->tag.invalid = false; /* mark the entry as valid */ |
112 | } |
109 | } |
113 | 110 | ||
114 | /** Copy software PTE to DTSB. |
111 | /** Copy software PTE to DTSB. |
115 | * |
112 | * |
116 | * @param t Software PTE. |
113 | * @param t Software PTE. |
117 | * @param ro If true, the mapping is copied read-only. |
114 | * @param ro If true, the mapping is copied read-only. |
118 | */ |
115 | */ |
119 | void dtsb_pte_copy(pte_t *t, bool ro) |
116 | void dtsb_pte_copy(pte_t *t, bool ro) |
120 | { |
117 | { |
121 | as_t *as; |
118 | as_t *as; |
122 | tsb_entry_t *tsb; |
119 | tsb_entry_t *tsb; |
123 | 120 | ||
124 | as = t->as; |
121 | as = t->as; |
125 | tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
122 | tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
126 | 123 | ||
127 | /* |
124 | /* |
128 | * We use write barriers to make sure that the TSB load |
125 | * We use write barriers to make sure that the TSB load |
129 | * won't use inconsistent data or that the fault will |
126 | * won't use inconsistent data or that the fault will |
130 | * be repeated. |
127 | * be repeated. |
131 | */ |
128 | */ |
132 | 129 | ||
133 | tsb->tag.invalid = true; /* invalidate the entry |
130 | tsb->tag.invalid = true; /* invalidate the entry |
134 | * (tag target has this |
131 | * (tag target has this |
135 | * set to 0) */ |
132 | * set to 0) */ |
136 | 133 | ||
137 | write_barrier(); |
134 | write_barrier(); |
138 | 135 | ||
139 | tsb->tag.context = as->asid; |
136 | tsb->tag.context = as->asid; |
140 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
137 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
141 | tsb->data.value = 0; |
138 | tsb->data.value = 0; |
142 | tsb->data.size = PAGESIZE_8K; |
139 | tsb->data.size = PAGESIZE_8K; |
143 | tsb->data.pfn = t->frame >> FRAME_WIDTH; |
140 | tsb->data.pfn = t->frame >> FRAME_WIDTH; |
144 | tsb->data.cp = t->c; |
141 | tsb->data.cp = t->c; |
145 | #ifdef CONFIG_VIRT_IDX_CACHE |
142 | #ifdef CONFIG_VIRT_IDX_DCACHE |
146 | tsb->data.cv = t->c; |
143 | tsb->data.cv = t->c; |
147 | #endif /* CONFIG_VIRT_IDX_CACHE */ |
144 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
148 | tsb->data.p = t->k; /* p as privileged */ |
145 | tsb->data.p = t->k; /* p as privileged */ |
149 | tsb->data.w = ro ? false : t->w; |
146 | tsb->data.w = ro ? false : t->w; |
150 | tsb->data.v = t->p; |
147 | tsb->data.v = t->p; |
151 | 148 | ||
152 | write_barrier(); |
149 | write_barrier(); |
153 | 150 | ||
154 | tsb->tag.invalid = true; /* mark the entry as valid */ |
151 | tsb->tag.invalid = true; /* mark the entry as valid */ |
155 | } |
152 | } |
156 | 153 | ||
157 | /** @} |
154 | /** @} |
158 | */ |
155 | */ |
159 | 156 |