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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (C) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tsb.h> |
35 | #include <arch/mm/tsb.h> |
- | 36 | #include <arch/mm/tlb.h> |
|
- | 37 | #include <arch/barrier.h> |
|
36 | #include <mm/as.h> |
38 | #include <mm/as.h> |
37 | #include <arch/types.h> |
39 | #include <arch/types.h> |
38 | #include <typedefs.h> |
40 | #include <typedefs.h> |
- | 41 | #include <macros.h> |
|
- | 42 | #include <debug.h> |
|
- | 43 | ||
- | 44 | #define TSB_INDEX_MASK ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1) |
|
39 | 45 | ||
40 | /** Invalidate portion of TSB. |
46 | /** Invalidate portion of TSB. |
41 | * |
47 | * |
42 | * We assume that the address space is already locked. |
48 | * We assume that the address space is already locked. |
- | 49 | * Note that respective portions of both TSBs |
|
- | 50 | * are invalidated at a time. |
|
43 | * |
51 | * |
44 | * @param as Address space. |
52 | * @param as Address space. |
45 | * @param page First page to invalidate in TSB. |
53 | * @param page First page to invalidate in TSB. |
46 | * @param pages Number of pages to invalidate. |
54 | * @param pages Number of pages to invalidate. Value of (count_t) -1 means the whole TSB. |
47 | */ |
55 | */ |
48 | void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
56 | void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
49 | { |
57 | { |
- | 58 | index_t i0, i; |
|
- | 59 | count_t cnt; |
|
- | 60 | ||
- | 61 | ASSERT(as->arch.itsb && as->arch.dtsb); |
|
- | 62 | ||
- | 63 | i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK; |
|
- | 64 | cnt = min(pages, ITSB_ENTRY_COUNT); |
|
- | 65 | ||
- | 66 | for (i = 0; i < cnt; i++) { |
|
- | 67 | as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = 0; |
|
- | 68 | as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = 0; |
|
- | 69 | } |
|
- | 70 | } |
|
- | 71 | ||
- | 72 | /** Copy software PTE to ITSB. |
|
- | 73 | * |
|
- | 74 | * @param t Software PTE. |
|
- | 75 | */ |
|
- | 76 | void itsb_pte_copy(pte_t *t) |
|
- | 77 | { |
|
- | 78 | as_t *as; |
|
- | 79 | tsb_entry_t *tsb; |
|
- | 80 | ||
- | 81 | as = t->as; |
|
- | 82 | tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
|
- | 83 | ||
- | 84 | /* |
|
- | 85 | * We use write barriers to make sure that the TSB load |
|
- | 86 | * won't use inconsistent data or that the fault will |
|
- | 87 | * be repeated. |
|
- | 88 | */ |
|
- | 89 | ||
- | 90 | tsb->tag.invalid = 1; /* invalidate the entry (tag target has this set to 0 */ |
|
- | 91 | ||
- | 92 | write_barrier(); |
|
- | 93 | ||
- | 94 | tsb->tag.context = as->asid; |
|
- | 95 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
|
- | 96 | tsb->data.value = 0; |
|
- | 97 | tsb->data.size = PAGESIZE_8K; |
|
- | 98 | tsb->data.pfn = t->frame >> PAGE_WIDTH; |
|
- | 99 | tsb->data.cp = t->c; |
|
- | 100 | tsb->data.cv = t->c; |
|
- | 101 | tsb->data.p = t->k; /* p as privileged */ |
|
- | 102 | tsb->data.v = t->p; |
|
- | 103 | ||
- | 104 | write_barrier(); |
|
- | 105 | ||
- | 106 | tsb->tag.invalid = 0; /* mark the entry as valid */ |
|
- | 107 | } |
|
- | 108 | ||
- | 109 | /** Copy software PTE to DTSB. |
|
- | 110 | * |
|
- | 111 | * @param t Software PTE. |
|
- | 112 | * @param ro If true, the mapping is copied read-only. |
|
- | 113 | */ |
|
- | 114 | void dtsb_pte_copy(pte_t *t, bool ro) |
|
- | 115 | { |
|
- | 116 | as_t *as; |
|
- | 117 | tsb_entry_t *tsb; |
|
- | 118 | ||
- | 119 | as = t->as; |
|
- | 120 | tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK]; |
|
- | 121 | ||
- | 122 | /* |
|
- | 123 | * We use write barriers to make sure that the TSB load |
|
- | 124 | * won't use inconsistent data or that the fault will |
|
- | 125 | * be repeated. |
|
- | 126 | */ |
|
- | 127 | ||
- | 128 | tsb->tag.invalid = 1; /* invalidate the entry (tag target has this set to 0) */ |
|
- | 129 | ||
- | 130 | write_barrier(); |
|
- | 131 | ||
- | 132 | tsb->tag.context = as->asid; |
|
- | 133 | tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; |
|
- | 134 | tsb->data.value = 0; |
|
- | 135 | tsb->data.size = PAGESIZE_8K; |
|
- | 136 | tsb->data.pfn = t->frame >> PAGE_WIDTH; |
|
- | 137 | tsb->data.cp = t->c; |
|
- | 138 | tsb->data.cv = t->c; |
|
- | 139 | tsb->data.p = t->k; /* p as privileged */ |
|
- | 140 | tsb->data.w = ro ? false : t->w; |
|
- | 141 | tsb->data.v = t->p; |
|
- | 142 | ||
- | 143 | write_barrier(); |
|
- | 144 | ||
- | 145 | tsb->tag.invalid = 0; /* mark the entry as valid */ |
|
50 | } |
146 | } |
51 | 147 | ||
52 | /** @} |
148 | /** @} |
53 | */ |
149 | */ |
54 | 150 |