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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <arch/mm/frame.h> |
37 | #include <arch/mm/frame.h> |
38 | #include <arch/mm/page.h> |
38 | #include <arch/mm/page.h> |
39 | #include <arch/mm/mmu.h> |
39 | #include <arch/mm/mmu.h> |
40 | #include <mm/asid.h> |
40 | #include <mm/asid.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <arch/types.h> |
42 | #include <arch/types.h> |
43 | #include <typedefs.h> |
43 | #include <typedefs.h> |
44 | #include <config.h> |
44 | #include <config.h> |
45 | #include <arch/trap/trap.h> |
45 | #include <arch/trap/trap.h> |
46 | #include <panic.h> |
46 | #include <panic.h> |
47 | #include <arch/asm.h> |
47 | #include <arch/asm.h> |
48 | #include <symtab.h> |
48 | #include <symtab.h> |
49 | 49 | ||
50 | #include <arch/drivers/fb.h> |
50 | #include <arch/drivers/fb.h> |
51 | #include <arch/drivers/i8042.h> |
51 | #include <arch/drivers/i8042.h> |
52 | 52 | ||
53 | char *context_encoding[] = { |
53 | char *context_encoding[] = { |
54 | "Primary", |
54 | "Primary", |
55 | "Secondary", |
55 | "Secondary", |
56 | "Nucleus", |
56 | "Nucleus", |
57 | "Reserved" |
57 | "Reserved" |
58 | }; |
58 | }; |
59 | 59 | ||
60 | void tlb_arch_init(void) |
60 | void tlb_arch_init(void) |
61 | { |
61 | { |
- | 62 | /* |
|
- | 63 | * TLBs are actually initialized by |
|
- | 64 | * take_over_tlb_and_tt() early |
|
- | 65 | * in start.S. |
|
- | 66 | */ |
|
62 | } |
67 | } |
63 | 68 | ||
64 | /** Insert privileged mapping into DMMU TLB. |
69 | /** Insert privileged mapping into DMMU TLB. |
65 | * |
70 | * |
66 | * @param page Virtual page address. |
71 | * @param page Virtual page address. |
67 | * @param frame Physical frame address. |
72 | * @param frame Physical frame address. |
68 | * @param pagesize Page size. |
73 | * @param pagesize Page size. |
69 | * @param locked True for permanent mappings, false otherwise. |
74 | * @param locked True for permanent mappings, false otherwise. |
70 | * @param cacheable True if the mapping is cacheable, false otherwise. |
75 | * @param cacheable True if the mapping is cacheable, false otherwise. |
71 | */ |
76 | */ |
72 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
77 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
73 | { |
78 | { |
74 | tlb_tag_access_reg_t tag; |
79 | tlb_tag_access_reg_t tag; |
75 | tlb_data_t data; |
80 | tlb_data_t data; |
76 | page_address_t pg; |
81 | page_address_t pg; |
77 | frame_address_t fr; |
82 | frame_address_t fr; |
78 | 83 | ||
79 | pg.address = page; |
84 | pg.address = page; |
80 | fr.address = frame; |
85 | fr.address = frame; |
81 | 86 | ||
82 | tag.value = ASID_KERNEL; |
87 | tag.value = ASID_KERNEL; |
83 | tag.vpn = pg.vpn; |
88 | tag.vpn = pg.vpn; |
84 | 89 | ||
85 | dtlb_tag_access_write(tag.value); |
90 | dtlb_tag_access_write(tag.value); |
86 | 91 | ||
87 | data.value = 0; |
92 | data.value = 0; |
88 | data.v = true; |
93 | data.v = true; |
89 | data.size = pagesize; |
94 | data.size = pagesize; |
90 | data.pfn = fr.pfn; |
95 | data.pfn = fr.pfn; |
91 | data.l = locked; |
96 | data.l = locked; |
92 | data.cp = cacheable; |
97 | data.cp = cacheable; |
93 | data.cv = cacheable; |
98 | data.cv = cacheable; |
94 | data.p = true; |
99 | data.p = true; |
95 | data.w = true; |
100 | data.w = true; |
96 | data.g = true; |
101 | data.g = true; |
97 | 102 | ||
98 | dtlb_data_in_write(data.value); |
103 | dtlb_data_in_write(data.value); |
99 | } |
104 | } |
100 | 105 | ||
101 | /** ITLB miss handler. */ |
106 | /** ITLB miss handler. */ |
102 | void fast_instruction_access_mmu_miss(void) |
107 | void fast_instruction_access_mmu_miss(void) |
103 | { |
108 | { |
104 | panic("%s\n", __FUNCTION__); |
109 | panic("%s\n", __FUNCTION__); |
105 | } |
110 | } |
106 | 111 | ||
107 | /** DTLB miss handler. */ |
112 | /** DTLB miss handler. */ |
108 | void fast_data_access_mmu_miss(void) |
113 | void fast_data_access_mmu_miss(void) |
109 | { |
114 | { |
110 | tlb_tag_access_reg_t tag; |
115 | tlb_tag_access_reg_t tag; |
111 | uintptr_t tpc; |
116 | uintptr_t tpc; |
112 | char *tpc_str; |
117 | char *tpc_str; |
113 | 118 | ||
114 | tag.value = dtlb_tag_access_read(); |
119 | tag.value = dtlb_tag_access_read(); |
115 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
120 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
116 | tpc = tpc_read(); |
121 | tpc = tpc_read(); |
117 | tpc_str = get_symtab_entry(tpc); |
122 | tpc_str = get_symtab_entry(tpc); |
118 | 123 | ||
119 | printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context); |
124 | printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context); |
120 | printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?"); |
125 | printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?"); |
121 | panic("%s\n", __FUNCTION__); |
126 | panic("%s\n", __FUNCTION__); |
122 | } |
127 | } |
123 | 128 | ||
124 | /* |
129 | /* |
125 | * Identity map piece of faulting kernel address space. |
130 | * Identity map piece of faulting kernel address space. |
126 | */ |
131 | */ |
127 | dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true); |
132 | dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true); |
128 | } |
133 | } |
129 | 134 | ||
130 | /** DTLB protection fault handler. */ |
135 | /** DTLB protection fault handler. */ |
131 | void fast_data_access_protection(void) |
136 | void fast_data_access_protection(void) |
132 | { |
137 | { |
133 | panic("%s\n", __FUNCTION__); |
138 | panic("%s\n", __FUNCTION__); |
134 | } |
139 | } |
135 | 140 | ||
136 | /** Print contents of both TLBs. */ |
141 | /** Print contents of both TLBs. */ |
137 | void tlb_print(void) |
142 | void tlb_print(void) |
138 | { |
143 | { |
139 | int i; |
144 | int i; |
140 | tlb_data_t d; |
145 | tlb_data_t d; |
141 | tlb_tag_read_reg_t t; |
146 | tlb_tag_read_reg_t t; |
142 | 147 | ||
143 | printf("I-TLB contents:\n"); |
148 | printf("I-TLB contents:\n"); |
144 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
149 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
145 | d.value = itlb_data_access_read(i); |
150 | d.value = itlb_data_access_read(i); |
146 | t.value = itlb_tag_read_read(i); |
151 | t.value = itlb_tag_read_read(i); |
147 | 152 | ||
148 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
153 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
149 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
154 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
150 | } |
155 | } |
151 | 156 | ||
152 | printf("D-TLB contents:\n"); |
157 | printf("D-TLB contents:\n"); |
153 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
158 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
154 | d.value = dtlb_data_access_read(i); |
159 | d.value = dtlb_data_access_read(i); |
155 | t.value = dtlb_tag_read_read(i); |
160 | t.value = dtlb_tag_read_read(i); |
156 | 161 | ||
157 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
162 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
158 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
163 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
159 | } |
164 | } |
160 | 165 | ||
161 | } |
166 | } |
162 | 167 | ||
163 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
168 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
164 | void tlb_invalidate_all(void) |
169 | void tlb_invalidate_all(void) |
165 | { |
170 | { |
166 | int i; |
171 | int i; |
167 | tlb_data_t d; |
172 | tlb_data_t d; |
168 | tlb_tag_read_reg_t t; |
173 | tlb_tag_read_reg_t t; |
169 | 174 | ||
170 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
175 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
171 | d.value = itlb_data_access_read(i); |
176 | d.value = itlb_data_access_read(i); |
172 | if (!d.l) { |
177 | if (!d.l) { |
173 | t.value = itlb_tag_read_read(i); |
178 | t.value = itlb_tag_read_read(i); |
174 | d.v = false; |
179 | d.v = false; |
175 | itlb_tag_access_write(t.value); |
180 | itlb_tag_access_write(t.value); |
176 | itlb_data_access_write(i, d.value); |
181 | itlb_data_access_write(i, d.value); |
177 | } |
182 | } |
178 | } |
183 | } |
179 | 184 | ||
180 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
185 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
181 | d.value = dtlb_data_access_read(i); |
186 | d.value = dtlb_data_access_read(i); |
182 | if (!d.l) { |
187 | if (!d.l) { |
183 | t.value = dtlb_tag_read_read(i); |
188 | t.value = dtlb_tag_read_read(i); |
184 | d.v = false; |
189 | d.v = false; |
185 | dtlb_tag_access_write(t.value); |
190 | dtlb_tag_access_write(t.value); |
186 | dtlb_data_access_write(i, d.value); |
191 | dtlb_data_access_write(i, d.value); |
187 | } |
192 | } |
188 | } |
193 | } |
189 | 194 | ||
190 | } |
195 | } |
191 | 196 | ||
192 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
197 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
193 | * |
198 | * |
194 | * @param asid Address Space ID. |
199 | * @param asid Address Space ID. |
195 | */ |
200 | */ |
196 | void tlb_invalidate_asid(asid_t asid) |
201 | void tlb_invalidate_asid(asid_t asid) |
197 | { |
202 | { |
198 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
203 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
199 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
204 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
200 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
205 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
201 | } |
206 | } |
202 | 207 | ||
203 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
208 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
204 | * |
209 | * |
205 | * @param asid Address Space ID. |
210 | * @param asid Address Space ID. |
206 | * @param page First page which to sweep out from ITLB and DTLB. |
211 | * @param page First page which to sweep out from ITLB and DTLB. |
207 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
212 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
208 | */ |
213 | */ |
209 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
214 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
210 | { |
215 | { |
211 | int i; |
216 | int i; |
212 | 217 | ||
213 | for (i = 0; i < cnt; i++) { |
218 | for (i = 0; i < cnt; i++) { |
214 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
219 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
215 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
220 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
216 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
221 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
217 | } |
222 | } |
218 | } |
223 | } |
219 | 224 | ||
220 | /** @} |
225 | /** @} |
221 | */ |
226 | */ |
222 | 227 |