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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
30 | #include <mm/tlb.h> |
30 | #include <mm/tlb.h> |
- | 31 | #include <genarch/mm/asid_fifo.h> |
|
31 | #include <arch/mm/frame.h> |
32 | #include <arch/mm/frame.h> |
32 | #include <arch/mm/page.h> |
33 | #include <arch/mm/page.h> |
33 | #include <arch/mm/mmu.h> |
34 | #include <arch/mm/mmu.h> |
34 | #include <print.h> |
35 | #include <print.h> |
35 | #include <arch/types.h> |
36 | #include <arch/types.h> |
36 | #include <typedefs.h> |
37 | #include <typedefs.h> |
37 | #include <config.h> |
38 | #include <config.h> |
38 | #include <arch/trap/trap.h> |
39 | #include <arch/trap/trap.h> |
39 | 40 | ||
40 | /** Initialize ITLB and DTLB. |
41 | /** Initialize ITLB and DTLB. |
41 | * |
42 | * |
42 | * The goal of this function is to disable MMU |
43 | * The goal of this function is to disable MMU |
43 | * so that both TLBs can be purged and new |
44 | * so that both TLBs can be purged and new |
44 | * kernel 4M locked entry can be installed. |
45 | * kernel 4M locked entry can be installed. |
45 | * After TLB is initialized, MMU is enabled |
46 | * After TLB is initialized, MMU is enabled |
46 | * again. |
47 | * again. |
47 | * |
48 | * |
48 | * Switching MMU off imposes the requirement for |
49 | * Switching MMU off imposes the requirement for |
49 | * the kernel to run in identity mapped environment. |
50 | * the kernel to run in identity mapped environment. |
50 | */ |
51 | */ |
51 | void tlb_arch_init(void) |
52 | void tlb_arch_init(void) |
52 | { |
53 | { |
53 | tlb_tag_access_reg_t tag; |
54 | tlb_tag_access_reg_t tag; |
54 | tlb_data_t data; |
55 | tlb_data_t data; |
55 | frame_address_t fr; |
56 | frame_address_t fr; |
56 | page_address_t pg; |
57 | page_address_t pg; |
57 | 58 | ||
- | 59 | asid_fifo_init(); |
|
- | 60 | ||
58 | fr.address = config.base; |
61 | fr.address = config.base; |
59 | pg.address = config.base; |
62 | pg.address = config.base; |
60 | 63 | ||
61 | immu_disable(); |
64 | immu_disable(); |
62 | dmmu_disable(); |
65 | dmmu_disable(); |
63 | 66 | ||
64 | /* |
67 | /* |
65 | * For simplicity, we do identity mapping of first 4M of memory. |
68 | * For simplicity, we do identity mapping of first 4M of memory. |
66 | * The very next change should be leaving the first 4M unmapped. |
69 | * The very next change should be leaving the first 4M unmapped. |
67 | */ |
70 | */ |
68 | tag.value = 0; |
71 | tag.value = 0; |
69 | tag.vpn = pg.vpn; |
72 | tag.vpn = pg.vpn; |
70 | 73 | ||
71 | itlb_tag_access_write(tag.value); |
74 | itlb_tag_access_write(tag.value); |
72 | dtlb_tag_access_write(tag.value); |
75 | dtlb_tag_access_write(tag.value); |
73 | 76 | ||
74 | data.value = 0; |
77 | data.value = 0; |
75 | data.v = true; |
78 | data.v = true; |
76 | data.size = PAGESIZE_4M; |
79 | data.size = PAGESIZE_4M; |
77 | data.pfn = fr.pfn; |
80 | data.pfn = fr.pfn; |
78 | data.l = true; |
81 | data.l = true; |
79 | data.cp = 1; |
82 | data.cp = 1; |
80 | data.cv = 1; |
83 | data.cv = 1; |
81 | data.p = true; |
84 | data.p = true; |
82 | data.w = true; |
85 | data.w = true; |
83 | data.g = true; |
86 | data.g = true; |
84 | 87 | ||
85 | itlb_data_in_write(data.value); |
88 | itlb_data_in_write(data.value); |
86 | dtlb_data_in_write(data.value); |
89 | dtlb_data_in_write(data.value); |
87 | 90 | ||
88 | /* |
91 | /* |
89 | * Register window traps can occur before MMU is enabled again. |
92 | * Register window traps can occur before MMU is enabled again. |
90 | * This ensures that any such traps will be handled from |
93 | * This ensures that any such traps will be handled from |
91 | * kernel identity mapped trap handler. |
94 | * kernel identity mapped trap handler. |
92 | */ |
95 | */ |
93 | trap_switch_trap_table(); |
96 | trap_switch_trap_table(); |
94 | 97 | ||
95 | tlb_invalidate_all(); |
98 | tlb_invalidate_all(); |
96 | 99 | ||
97 | dmmu_enable(); |
100 | dmmu_enable(); |
98 | immu_enable(); |
101 | immu_enable(); |
99 | } |
102 | } |
100 | 103 | ||
101 | /** Print contents of both TLBs. */ |
104 | /** Print contents of both TLBs. */ |
102 | void tlb_print(void) |
105 | void tlb_print(void) |
103 | { |
106 | { |
104 | int i; |
107 | int i; |
105 | tlb_data_t d; |
108 | tlb_data_t d; |
106 | tlb_tag_read_reg_t t; |
109 | tlb_tag_read_reg_t t; |
107 | 110 | ||
108 | printf("I-TLB contents:\n"); |
111 | printf("I-TLB contents:\n"); |
109 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
112 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
110 | d.value = itlb_data_access_read(i); |
113 | d.value = itlb_data_access_read(i); |
111 | t.value = itlb_tag_read_read(i); |
114 | t.value = itlb_tag_read_read(i); |
112 | 115 | ||
113 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
116 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
114 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
117 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
115 | } |
118 | } |
116 | 119 | ||
117 | printf("D-TLB contents:\n"); |
120 | printf("D-TLB contents:\n"); |
118 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
121 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
119 | d.value = dtlb_data_access_read(i); |
122 | d.value = dtlb_data_access_read(i); |
120 | t.value = dtlb_tag_read_read(i); |
123 | t.value = dtlb_tag_read_read(i); |
121 | 124 | ||
122 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
125 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
123 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
126 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
124 | } |
127 | } |
125 | 128 | ||
126 | } |
129 | } |
127 | 130 | ||
128 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
131 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
129 | void tlb_invalidate_all(void) |
132 | void tlb_invalidate_all(void) |
130 | { |
133 | { |
131 | int i; |
134 | int i; |
132 | tlb_data_t d; |
135 | tlb_data_t d; |
133 | tlb_tag_read_reg_t t; |
136 | tlb_tag_read_reg_t t; |
134 | 137 | ||
135 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
138 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
136 | d.value = itlb_data_access_read(i); |
139 | d.value = itlb_data_access_read(i); |
137 | if (!d.l) { |
140 | if (!d.l) { |
138 | t.value = itlb_tag_read_read(i); |
141 | t.value = itlb_tag_read_read(i); |
139 | d.v = false; |
142 | d.v = false; |
140 | itlb_tag_access_write(t.value); |
143 | itlb_tag_access_write(t.value); |
141 | itlb_data_access_write(i, d.value); |
144 | itlb_data_access_write(i, d.value); |
142 | } |
145 | } |
143 | } |
146 | } |
144 | 147 | ||
145 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
148 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
146 | d.value = dtlb_data_access_read(i); |
149 | d.value = dtlb_data_access_read(i); |
147 | if (!d.l) { |
150 | if (!d.l) { |
148 | t.value = dtlb_tag_read_read(i); |
151 | t.value = dtlb_tag_read_read(i); |
149 | d.v = false; |
152 | d.v = false; |
150 | dtlb_tag_access_write(t.value); |
153 | dtlb_tag_access_write(t.value); |
151 | dtlb_data_access_write(i, d.value); |
154 | dtlb_data_access_write(i, d.value); |
152 | } |
155 | } |
153 | } |
156 | } |
154 | 157 | ||
155 | } |
158 | } |
156 | 159 | ||
157 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
160 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
158 | * |
161 | * |
159 | * @param asid Address Space ID. |
162 | * @param asid Address Space ID. |
160 | */ |
163 | */ |
161 | void tlb_invalidate_asid(asid_t asid) |
164 | void tlb_invalidate_asid(asid_t asid) |
162 | { |
165 | { |
163 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
166 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
164 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
167 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
165 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
168 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
166 | } |
169 | } |
167 | 170 | ||
168 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
171 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
169 | * |
172 | * |
170 | * @param asid Address Space ID. |
173 | * @param asid Address Space ID. |
171 | * @param page First page which to sweep out from ITLB and DTLB. |
174 | * @param page First page which to sweep out from ITLB and DTLB. |
172 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
175 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
173 | */ |
176 | */ |
174 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
177 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
175 | { |
178 | { |
176 | int i; |
179 | int i; |
177 | 180 | ||
178 | for (i = 0; i < cnt; i++) { |
181 | for (i = 0; i < cnt; i++) { |
179 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
182 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
180 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
183 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
181 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
184 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
182 | } |
185 | } |
183 | } |
186 | } |
184 | 187 |