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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/mm/tlb.h> |
29 | #include <arch/mm/tlb.h> |
30 | #include <mm/tlb.h> |
30 | #include <mm/tlb.h> |
31 | #include <arch/mm/frame.h> |
31 | #include <arch/mm/frame.h> |
32 | #include <arch/mm/page.h> |
32 | #include <arch/mm/page.h> |
33 | #include <arch/mm/mmu.h> |
33 | #include <arch/mm/mmu.h> |
34 | #include <print.h> |
34 | #include <print.h> |
35 | #include <arch/types.h> |
35 | #include <arch/types.h> |
36 | #include <typedefs.h> |
36 | #include <typedefs.h> |
37 | #include <config.h> |
37 | #include <config.h> |
38 | #include <arch/trap/trap.h> |
38 | #include <arch/trap/trap.h> |
- | 39 | #include <panic.h> |
|
39 | 40 | ||
40 | /** Initialize ITLB and DTLB. |
41 | /** Initialize ITLB and DTLB. |
41 | * |
42 | * |
42 | * The goal of this function is to disable MMU |
43 | * The goal of this function is to disable MMU |
43 | * so that both TLBs can be purged and new |
44 | * so that both TLBs can be purged and new |
44 | * kernel 4M locked entry can be installed. |
45 | * kernel 4M locked entry can be installed. |
45 | * After TLB is initialized, MMU is enabled |
46 | * After TLB is initialized, MMU is enabled |
46 | * again. |
47 | * again. |
47 | * |
48 | * |
48 | * Switching MMU off imposes the requirement for |
49 | * Switching MMU off imposes the requirement for |
49 | * the kernel to run in identity mapped environment. |
50 | * the kernel to run in identity mapped environment. |
50 | */ |
51 | */ |
51 | void tlb_arch_init(void) |
52 | void tlb_arch_init(void) |
52 | { |
53 | { |
53 | tlb_tag_access_reg_t tag; |
54 | tlb_tag_access_reg_t tag; |
54 | tlb_data_t data; |
55 | tlb_data_t data; |
55 | frame_address_t fr; |
56 | frame_address_t fr; |
56 | page_address_t pg; |
57 | page_address_t pg; |
57 | 58 | ||
58 | fr.address = config.base; |
59 | fr.address = config.base; |
59 | pg.address = config.base; |
60 | pg.address = config.base; |
60 | 61 | ||
61 | immu_disable(); |
62 | immu_disable(); |
62 | dmmu_disable(); |
63 | dmmu_disable(); |
63 | 64 | ||
64 | /* |
65 | /* |
65 | * We do identity mapping of 4M-page at 4M. |
66 | * We do identity mapping of 4M-page at 4M. |
66 | */ |
67 | */ |
67 | tag.value = 0; |
68 | tag.value = 0; |
68 | tag.vpn = pg.vpn; |
69 | tag.vpn = pg.vpn; |
69 | 70 | ||
70 | itlb_tag_access_write(tag.value); |
71 | itlb_tag_access_write(tag.value); |
71 | dtlb_tag_access_write(tag.value); |
72 | dtlb_tag_access_write(tag.value); |
72 | 73 | ||
73 | data.value = 0; |
74 | data.value = 0; |
74 | data.v = true; |
75 | data.v = true; |
75 | data.size = PAGESIZE_4M; |
76 | data.size = PAGESIZE_4M; |
76 | data.pfn = fr.pfn; |
77 | data.pfn = fr.pfn; |
77 | data.l = true; |
78 | data.l = true; |
78 | data.cp = 1; |
79 | data.cp = 1; |
79 | data.cv = 1; |
80 | data.cv = 1; |
80 | data.p = true; |
81 | data.p = true; |
81 | data.w = true; |
82 | data.w = true; |
82 | data.g = true; |
83 | data.g = true; |
83 | 84 | ||
84 | itlb_data_in_write(data.value); |
85 | itlb_data_in_write(data.value); |
85 | dtlb_data_in_write(data.value); |
86 | dtlb_data_in_write(data.value); |
86 | 87 | ||
87 | /* |
88 | /* |
88 | * Register window traps can occur before MMU is enabled again. |
89 | * Register window traps can occur before MMU is enabled again. |
89 | * This ensures that any such traps will be handled from |
90 | * This ensures that any such traps will be handled from |
90 | * kernel identity mapped trap handler. |
91 | * kernel identity mapped trap handler. |
91 | */ |
92 | */ |
92 | trap_switch_trap_table(); |
93 | trap_switch_trap_table(); |
93 | 94 | ||
94 | tlb_invalidate_all(); |
95 | tlb_invalidate_all(); |
95 | 96 | ||
96 | dmmu_enable(); |
97 | dmmu_enable(); |
97 | immu_enable(); |
98 | immu_enable(); |
98 | } |
99 | } |
- | 100 | ||
- | 101 | /** ITLB miss handler. */ |
|
- | 102 | void fast_instruction_access_mmu_miss(void) |
|
- | 103 | { |
|
- | 104 | panic("%s\n", __FUNCTION__); |
|
- | 105 | } |
|
- | 106 | ||
- | 107 | /** DTLB miss handler. */ |
|
- | 108 | void fast_data_access_mmu_miss(void) |
|
- | 109 | { |
|
- | 110 | panic("%s\n", __FUNCTION__); |
|
- | 111 | } |
|
- | 112 | ||
- | 113 | /** DTLB protection fault handler. */ |
|
- | 114 | void fast_data_access_protection(void) |
|
- | 115 | { |
|
- | 116 | panic("%s\n", __FUNCTION__); |
|
- | 117 | } |
|
99 | 118 | ||
100 | /** Print contents of both TLBs. */ |
119 | /** Print contents of both TLBs. */ |
101 | void tlb_print(void) |
120 | void tlb_print(void) |
102 | { |
121 | { |
103 | int i; |
122 | int i; |
104 | tlb_data_t d; |
123 | tlb_data_t d; |
105 | tlb_tag_read_reg_t t; |
124 | tlb_tag_read_reg_t t; |
106 | 125 | ||
107 | printf("I-TLB contents:\n"); |
126 | printf("I-TLB contents:\n"); |
108 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
127 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
109 | d.value = itlb_data_access_read(i); |
128 | d.value = itlb_data_access_read(i); |
110 | t.value = itlb_tag_read_read(i); |
129 | t.value = itlb_tag_read_read(i); |
111 | 130 | ||
112 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
131 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
113 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
132 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
114 | } |
133 | } |
115 | 134 | ||
116 | printf("D-TLB contents:\n"); |
135 | printf("D-TLB contents:\n"); |
117 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
136 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
118 | d.value = dtlb_data_access_read(i); |
137 | d.value = dtlb_data_access_read(i); |
119 | t.value = dtlb_tag_read_read(i); |
138 | t.value = dtlb_tag_read_read(i); |
120 | 139 | ||
121 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
140 | printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
122 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
141 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
123 | } |
142 | } |
124 | 143 | ||
125 | } |
144 | } |
126 | 145 | ||
127 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
146 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
128 | void tlb_invalidate_all(void) |
147 | void tlb_invalidate_all(void) |
129 | { |
148 | { |
130 | int i; |
149 | int i; |
131 | tlb_data_t d; |
150 | tlb_data_t d; |
132 | tlb_tag_read_reg_t t; |
151 | tlb_tag_read_reg_t t; |
133 | 152 | ||
134 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
153 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
135 | d.value = itlb_data_access_read(i); |
154 | d.value = itlb_data_access_read(i); |
136 | if (!d.l) { |
155 | if (!d.l) { |
137 | t.value = itlb_tag_read_read(i); |
156 | t.value = itlb_tag_read_read(i); |
138 | d.v = false; |
157 | d.v = false; |
139 | itlb_tag_access_write(t.value); |
158 | itlb_tag_access_write(t.value); |
140 | itlb_data_access_write(i, d.value); |
159 | itlb_data_access_write(i, d.value); |
141 | } |
160 | } |
142 | } |
161 | } |
143 | 162 | ||
144 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
163 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
145 | d.value = dtlb_data_access_read(i); |
164 | d.value = dtlb_data_access_read(i); |
146 | if (!d.l) { |
165 | if (!d.l) { |
147 | t.value = dtlb_tag_read_read(i); |
166 | t.value = dtlb_tag_read_read(i); |
148 | d.v = false; |
167 | d.v = false; |
149 | dtlb_tag_access_write(t.value); |
168 | dtlb_tag_access_write(t.value); |
150 | dtlb_data_access_write(i, d.value); |
169 | dtlb_data_access_write(i, d.value); |
151 | } |
170 | } |
152 | } |
171 | } |
153 | 172 | ||
154 | } |
173 | } |
155 | 174 | ||
156 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
175 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
157 | * |
176 | * |
158 | * @param asid Address Space ID. |
177 | * @param asid Address Space ID. |
159 | */ |
178 | */ |
160 | void tlb_invalidate_asid(asid_t asid) |
179 | void tlb_invalidate_asid(asid_t asid) |
161 | { |
180 | { |
162 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
181 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
163 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
182 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
164 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
183 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
165 | } |
184 | } |
166 | 185 | ||
167 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
186 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
168 | * |
187 | * |
169 | * @param asid Address Space ID. |
188 | * @param asid Address Space ID. |
170 | * @param page First page which to sweep out from ITLB and DTLB. |
189 | * @param page First page which to sweep out from ITLB and DTLB. |
171 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
190 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
172 | */ |
191 | */ |
173 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
192 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
174 | { |
193 | { |
175 | int i; |
194 | int i; |
176 | 195 | ||
177 | for (i = 0; i < cnt; i++) { |
196 | for (i = 0; i < cnt; i++) { |
178 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
197 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
179 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
198 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
180 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
199 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
181 | } |
200 | } |
182 | } |
201 | } |
183 | 202 |