WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
static void itlb_pte_copy(pte_t *t, index_t index);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
    const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * Invalidate all non-locked DTLB and ITLB entries.
     */
    tlb_invalidate_all();
 
    /*
     * Clear both SFSRs.
     */
    dtlb_sfsr_write(0);
    itlb_sfsr_write(0);
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
    bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t     Page Table Entry to be copied.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 * @param ro    If true, the entry will be created read-only, regardless of its
 *      w field.
 */
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t     Page Table Entry to be copied.
 * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
 */
void itlb_pte_copy(pte_t *t, index_t index)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t, index);
#ifdef CONFIG_TSB
        itsb_pte_copy(t, index);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate,
                __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved by the
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    index_t index;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
            "kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, index, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    index_t index;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is
         * writable. Demap the old mapping and insert an updated mapping
         * into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
            va + index * MMU_PAGE_SIZE);
        dtlb_pte_copy(t, index, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, index, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
 
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
    const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
        tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << MMU_PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
        tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void dump_sfsr_and_sfar(void)
{
    tlb_sfsr_reg_t sfsr;
    uintptr_t sfar;
 
    sfsr.value = dtlb_sfsr_read();
    sfar = dtlb_sfar_read();
   
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
        "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
        sfsr.ow, sfsr.fv);
    printf("DTLB SFAR: address=%p\n", sfar);
   
    dtlb_sfsr_write(0);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    /*
     * Walk all ITLB and DTLB entries and remove all unlocked mappings.
     *
     * The kernel doesn't use global mappings so any locked global mappings
     * found  must have been created by someone else. Their only purpose now
     * is to collide with proper mappings. Invalidate immediately. It should
     * be safe to invalidate them as late as now.
     */
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l || d.g) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l || d.g) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
 * (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified
 * address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
            page + i * MMU_PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 2134	Rev 2141
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <config.h>	47	#include <config.h>
48	#include <arch/trap/trap.h>	48	#include <arch/trap/trap.h>
49	#include <arch/trap/exception.h>	49	#include <arch/trap/exception.h>
50	#include <panic.h>	50	#include <panic.h>
51	#include <arch/asm.h>	51	#include <arch/asm.h>
52		52
53	#ifdef CONFIG_TSB	53	#ifdef CONFIG_TSB
54	#include <arch/mm/tsb.h>	54	#include <arch/mm/tsb.h>
55	#endif	55	#endif
56		56
57	static void dtlb_pte_copy(pte_t *t, bool ro);	57	static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
58	static void itlb_pte_copy(pte_t *t);	58	static void itlb_pte_copy(pte_t *t, index_t index);
59	static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const	59	static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
60	char *str);	60	const char *str);
61	static void do_fast_data_access_mmu_miss_fault(istate_t *istate,	61	static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
62	tlb_tag_access_reg_t tag, const char *str);	62	tlb_tag_access_reg_t tag, const char *str);
63	static void do_fast_data_access_protection_fault(istate_t *istate,	63	static void do_fast_data_access_protection_fault(istate_t *istate,
64	tlb_tag_access_reg_t tag, const char *str);	64	tlb_tag_access_reg_t tag, const char *str);
65		65
66	char *context_encoding[] = {	66	char *context_encoding[] = {
67	"Primary",	67	"Primary",
68	"Secondary",	68	"Secondary",
69	"Nucleus",	69	"Nucleus",
70	"Reserved"	70	"Reserved"
71	};	71	};
72		72
73	void tlb_arch_init(void)	73	void tlb_arch_init(void)
74	{	74	{
75	/*	75	/*
76	* Invalidate all non-locked DTLB and ITLB entries.	76	* Invalidate all non-locked DTLB and ITLB entries.
77	*/	77	*/
78	tlb_invalidate_all();	78	tlb_invalidate_all();
79		79
80	/*	80	/*
81	* Clear both SFSRs.	81	* Clear both SFSRs.
82	*/	82	*/
83	dtlb_sfsr_write(0);	83	dtlb_sfsr_write(0);
84	itlb_sfsr_write(0);	84	itlb_sfsr_write(0);
85	}	85	}
86		86
87	/** Insert privileged mapping into DMMU TLB.	87	/** Insert privileged mapping into DMMU TLB.
88	*	88	*
89	* @param page Virtual page address.	89	* @param page Virtual page address.
90	* @param frame Physical frame address.	90	* @param frame Physical frame address.
91	* @param pagesize Page size.	91	* @param pagesize Page size.
92	* @param locked True for permanent mappings, false otherwise.	92	* @param locked True for permanent mappings, false otherwise.
93	* @param cacheable True if the mapping is cacheable, false otherwise.	93	* @param cacheable True if the mapping is cacheable, false otherwise.
94	*/	94	*/
95	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool	95	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
96	locked, bool cacheable)	96	bool locked, bool cacheable)
97	{	97	{
98	tlb_tag_access_reg_t tag;	98	tlb_tag_access_reg_t tag;
99	tlb_data_t data;	99	tlb_data_t data;
100	page_address_t pg;	100	page_address_t pg;
101	frame_address_t fr;	101	frame_address_t fr;
102		102
103	pg.address = page;	103	pg.address = page;
104	fr.address = frame;	104	fr.address = frame;
105		105
106	tag.value = ASID_KERNEL;	106	tag.value = ASID_KERNEL;
107	tag.vpn = pg.vpn;	107	tag.vpn = pg.vpn;
108		108
109	dtlb_tag_access_write(tag.value);	109	dtlb_tag_access_write(tag.value);
110		110
111	data.value = 0;	111	data.value = 0;
112	data.v = true;	112	data.v = true;
113	data.size = pagesize;	113	data.size = pagesize;
114	data.pfn = fr.pfn;	114	data.pfn = fr.pfn;
115	data.l = locked;	115	data.l = locked;
116	data.cp = cacheable;	116	data.cp = cacheable;
117	#ifdef CONFIG_VIRT_IDX_DCACHE	117	#ifdef CONFIG_VIRT_IDX_DCACHE
118	data.cv = cacheable;	118	data.cv = cacheable;
119	#endif /* CONFIG_VIRT_IDX_DCACHE */	119	#endif /* CONFIG_VIRT_IDX_DCACHE */
120	data.p = true;	120	data.p = true;
121	data.w = true;	121	data.w = true;
122	data.g = false;	122	data.g = false;
123		123
124	dtlb_data_in_write(data.value);	124	dtlb_data_in_write(data.value);
125	}	125	}
126		126
127	/** Copy PTE to TLB.	127	/** Copy PTE to TLB.
128	*	128	*
129	* @param t Page Table Entry to be copied.	129	* @param t Page Table Entry to be copied.
-		130	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
130	* @param ro If true, the entry will be created read-only, regardless of its w	131	* @param ro If true, the entry will be created read-only, regardless of its
131	* field.	132	* w field.
132	*/	133	*/
133	void dtlb_pte_copy(pte_t *t, bool ro)	134	void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
134	{	135	{
135	tlb_tag_access_reg_t tag;	136	tlb_tag_access_reg_t tag;
136	tlb_data_t data;	137	tlb_data_t data;
137	page_address_t pg;	138	page_address_t pg;
138	frame_address_t fr;	139	frame_address_t fr;
139		140
140	pg.address = t->page;	141	pg.address = t->page + (index << MMU_PAGE_WIDTH);
141	fr.address = t->frame;	142	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
142		143
143	tag.value = 0;	144	tag.value = 0;
144	tag.context = t->as->asid;	145	tag.context = t->as->asid;
145	tag.vpn = pg.vpn;	146	tag.vpn = pg.vpn;
146		147
147	dtlb_tag_access_write(tag.value);	148	dtlb_tag_access_write(tag.value);
148		149
149	data.value = 0;	150	data.value = 0;
150	data.v = true;	151	data.v = true;
151	data.size = PAGESIZE_8K;	152	data.size = PAGESIZE_8K;
152	data.pfn = fr.pfn;	153	data.pfn = fr.pfn;
153	data.l = false;	154	data.l = false;
154	data.cp = t->c;	155	data.cp = t->c;
155	#ifdef CONFIG_VIRT_IDX_DCACHE	156	#ifdef CONFIG_VIRT_IDX_DCACHE
156	data.cv = t->c;	157	data.cv = t->c;
157	#endif /* CONFIG_VIRT_IDX_DCACHE */	158	#endif /* CONFIG_VIRT_IDX_DCACHE */
158	data.p = t->k; /* p like privileged */	159	data.p = t->k; /* p like privileged */
159	data.w = ro ? false : t->w;	160	data.w = ro ? false : t->w;
160	data.g = t->g;	161	data.g = t->g;
161		162
162	dtlb_data_in_write(data.value);	163	dtlb_data_in_write(data.value);
163	}	164	}
164		165
165	/** Copy PTE to ITLB.	166	/** Copy PTE to ITLB.
166	*	167	*
167	* @param t Page Table Entry to be copied.	168	* @param t Page Table Entry to be copied.
-		169	* @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
168	*/	170	*/
169	void itlb_pte_copy(pte_t *t)	171	void itlb_pte_copy(pte_t *t, index_t index)
170	{	172	{
171	tlb_tag_access_reg_t tag;	173	tlb_tag_access_reg_t tag;
172	tlb_data_t data;	174	tlb_data_t data;
173	page_address_t pg;	175	page_address_t pg;
174	frame_address_t fr;	176	frame_address_t fr;
175		177
176	pg.address = t->page;	178	pg.address = t->page + (index << MMU_PAGE_WIDTH);
177	fr.address = t->frame;	179	fr.address = t->frame + (index << MMU_PAGE_WIDTH);
178		180
179	tag.value = 0;	181	tag.value = 0;
180	tag.context = t->as->asid;	182	tag.context = t->as->asid;
181	tag.vpn = pg.vpn;	183	tag.vpn = pg.vpn;
182		184
183	itlb_tag_access_write(tag.value);	185	itlb_tag_access_write(tag.value);
184		186
185	data.value = 0;	187	data.value = 0;
186	data.v = true;	188	data.v = true;
187	data.size = PAGESIZE_8K;	189	data.size = PAGESIZE_8K;
188	data.pfn = fr.pfn;	190	data.pfn = fr.pfn;
189	data.l = false;	191	data.l = false;
190	data.cp = t->c;	192	data.cp = t->c;
191	data.p = t->k; /* p like privileged */	193	data.p = t->k; /* p like privileged */
192	data.w = false;	194	data.w = false;
193	data.g = t->g;	195	data.g = t->g;
194		196
195	itlb_data_in_write(data.value);	197	itlb_data_in_write(data.value);
196	}	198	}
197		199
198	/** ITLB miss handler. */	200	/** ITLB miss handler. */
199	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	201	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
200	{	202	{
201	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	203	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
-		204	index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
202	pte_t *t;	205	pte_t *t;
203		206
204	page_table_lock(AS, true);	207	page_table_lock(AS, true);
205	t = page_mapping_find(AS, va);	208	t = page_mapping_find(AS, va);
206	if (t && PTE_EXECUTABLE(t)) {	209	if (t && PTE_EXECUTABLE(t)) {
207	/*	210	/*
208	* The mapping was found in the software page hash table.	211	* The mapping was found in the software page hash table.
209	* Insert it into ITLB.	212	* Insert it into ITLB.
210	*/	213	*/
211	t->a = true;	214	t->a = true;
212	itlb_pte_copy(t);	215	itlb_pte_copy(t, index);
213	#ifdef CONFIG_TSB	216	#ifdef CONFIG_TSB
214	itsb_pte_copy(t);	217	itsb_pte_copy(t, index);
215	#endif	218	#endif
216	page_table_unlock(AS, true);	219	page_table_unlock(AS, true);
217	} else {	220	} else {
218	/*	221	/*
219	* Forward the page fault to the address space page fault	222	* Forward the page fault to the address space page fault
220	* handler.	223	* handler.
221	*/	224	*/
222	page_table_unlock(AS, true);	225	page_table_unlock(AS, true);
223	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	226	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
224	do_fast_instruction_access_mmu_miss_fault(istate,	227	do_fast_instruction_access_mmu_miss_fault(istate,
225	__FUNCTION__);	228	__FUNCTION__);
226	}	229	}
227	}	230	}
228	}	231	}
229		232
230	/** DTLB miss handler.	233	/** DTLB miss handler.
231	*	234	*
232	* Note that some faults (e.g. kernel faults) were already resolved by the	235	* Note that some faults (e.g. kernel faults) were already resolved by the
233	* low-level, assembly language part of the fast_data_access_mmu_miss handler.	236	* low-level, assembly language part of the fast_data_access_mmu_miss handler.
234	*/	237	*/
235	void fast_data_access_mmu_miss(int n, istate_t *istate)	238	void fast_data_access_mmu_miss(int n, istate_t *istate)
236	{	239	{
237	tlb_tag_access_reg_t tag;	240	tlb_tag_access_reg_t tag;
238	uintptr_t va;	241	uintptr_t va;
-		242	index_t index;
239	pte_t *t;	243	pte_t *t;
240		244
241	tag.value = dtlb_tag_access_read();	245	tag.value = dtlb_tag_access_read();
-		246	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
242	va = tag.vpn << PAGE_WIDTH;	247	index = tag.vpn % MMU_PAGES_PER_PAGE;
243		248
244	if (tag.context == ASID_KERNEL) {	249	if (tag.context == ASID_KERNEL) {
245	if (!tag.vpn) {	250	if (!tag.vpn) {
246	/* NULL access in kernel */	251	/* NULL access in kernel */
247	do_fast_data_access_mmu_miss_fault(istate, tag,	252	do_fast_data_access_mmu_miss_fault(istate, tag,
248	__FUNCTION__);	253	__FUNCTION__);
249	}	254	}
250	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "	255	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
251	"kernel page fault.");	256	"kernel page fault.");
252	}	257	}
253		258
254	page_table_lock(AS, true);	259	page_table_lock(AS, true);
255	t = page_mapping_find(AS, va);	260	t = page_mapping_find(AS, va);
256	if (t) {	261	if (t) {
257	/*	262	/*
258	* The mapping was found in the software page hash table.	263	* The mapping was found in the software page hash table.
259	* Insert it into DTLB.	264	* Insert it into DTLB.
260	*/	265	*/
261	t->a = true;	266	t->a = true;
262	dtlb_pte_copy(t, true);	267	dtlb_pte_copy(t, index, true);
263	#ifdef CONFIG_TSB	268	#ifdef CONFIG_TSB
264	dtsb_pte_copy(t, true);	269	dtsb_pte_copy(t, index, true);
265	#endif	270	#endif
266	page_table_unlock(AS, true);	271	page_table_unlock(AS, true);
267	} else {	272	} else {
268	/*	273	/*
269	* Forward the page fault to the address space page fault handler.	274	* Forward the page fault to the address space page fault
-		275	* handler.
270	*/	276	*/
271	page_table_unlock(AS, true);	277	page_table_unlock(AS, true);
272	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	278	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
273	do_fast_data_access_mmu_miss_fault(istate, tag,	279	do_fast_data_access_mmu_miss_fault(istate, tag,
274	__FUNCTION__);	280	__FUNCTION__);
275	}	281	}
276	}	282	}
277	}	283	}
278		284
279	/** DTLB protection fault handler. */	285	/** DTLB protection fault handler. */
280	void fast_data_access_protection(int n, istate_t *istate)	286	void fast_data_access_protection(int n, istate_t *istate)
281	{	287	{
282	tlb_tag_access_reg_t tag;	288	tlb_tag_access_reg_t tag;
283	uintptr_t va;	289	uintptr_t va;
-		290	index_t index;
284	pte_t *t;	291	pte_t *t;
285		292
286	tag.value = dtlb_tag_access_read();	293	tag.value = dtlb_tag_access_read();
287	va = tag.vpn << PAGE_WIDTH;	294	va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
-		295	index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */
288		296
289	page_table_lock(AS, true);	297	page_table_lock(AS, true);
290	t = page_mapping_find(AS, va);	298	t = page_mapping_find(AS, va);
291	if (t && PTE_WRITABLE(t)) {	299	if (t && PTE_WRITABLE(t)) {
292	/*	300	/*
293	* The mapping was found in the software page hash table and is	301	* The mapping was found in the software page hash table and is
294	* writable. Demap the old mapping and insert an updated mapping	302	* writable. Demap the old mapping and insert an updated mapping
295	* into DTLB.	303	* into DTLB.
296	*/	304	*/
297	t->a = true;	305	t->a = true;
298	t->d = true;	306	t->d = true;
299	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	307	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
-		308	va + index * MMU_PAGE_SIZE);
300	dtlb_pte_copy(t, false);	309	dtlb_pte_copy(t, index, false);
301	#ifdef CONFIG_TSB	310	#ifdef CONFIG_TSB
302	dtsb_pte_copy(t, false);	311	dtsb_pte_copy(t, index, false);
303	#endif	312	#endif
304	page_table_unlock(AS, true);	313	page_table_unlock(AS, true);
305	} else {	314	} else {
306	/*	315	/*
307	* Forward the page fault to the address space page fault	316	* Forward the page fault to the address space page fault
308	* handler.	317	* handler.
309	*/	318	*/
310	page_table_unlock(AS, true);	319	page_table_unlock(AS, true);
311	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	320	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
312	do_fast_data_access_protection_fault(istate, tag,	321	do_fast_data_access_protection_fault(istate, tag,
313	__FUNCTION__);	322	__FUNCTION__);
314	}	323	}
315	}	324	}
316	}	325	}
317		326
318	/** Print contents of both TLBs. */	327	/** Print contents of both TLBs. */
319	void tlb_print(void)	328	void tlb_print(void)
320	{	329	{
321	int i;	330	int i;
322	tlb_data_t d;	331	tlb_data_t d;
323	tlb_tag_read_reg_t t;	332	tlb_tag_read_reg_t t;
324		333
325	printf("I-TLB contents:\n");	334	printf("I-TLB contents:\n");
326	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	335	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
327	d.value = itlb_data_access_read(i);	336	d.value = itlb_data_access_read(i);
328	t.value = itlb_tag_read_read(i);	337	t.value = itlb_tag_read_read(i);
329		338
330	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "	339	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
331	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "	340	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
332	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,	341	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
333	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,	342	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
334	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	343	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
335	}	344	}
336		345
337	printf("D-TLB contents:\n");	346	printf("D-TLB contents:\n");
338	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	347	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
339	d.value = dtlb_data_access_read(i);	348	d.value = dtlb_data_access_read(i);
340	t.value = dtlb_tag_read_read(i);	349	t.value = dtlb_tag_read_read(i);
341		350
342	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "	351	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
343	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "	352	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
344	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,	353	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
345	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,	354	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
346	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	355	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
347	}	356	}
348		357
349	}	358	}
350		359
351	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char	360	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
352	*str)	361	const char *str)
353	{	362	{
354	fault_if_from_uspace(istate, "%s\n", str);	363	fault_if_from_uspace(istate, "%s\n", str);
355	dump_istate(istate);	364	dump_istate(istate);
356	panic("%s\n", str);	365	panic("%s\n", str);
357	}	366	}
358		367
359	void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t	368	void do_fast_data_access_mmu_miss_fault(istate_t *istate,
360	tag, const char *str)	369	tlb_tag_access_reg_t tag, const char *str)
361	{	370	{
362	uintptr_t va;	371	uintptr_t va;
363		372
364	va = tag.vpn << PAGE_WIDTH;	373	va = tag.vpn << MMU_PAGE_WIDTH;
365		374
366	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	375	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
367	tag.context);	376	tag.context);
368	dump_istate(istate);	377	dump_istate(istate);
369	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	378	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
370	panic("%s\n", str);	379	panic("%s\n", str);
371	}	380	}
372		381
373	void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t	382	void do_fast_data_access_protection_fault(istate_t *istate,
374	tag, const char *str)	383	tlb_tag_access_reg_t tag, const char *str)
375	{	384	{
376	uintptr_t va;	385	uintptr_t va;
377		386
378	va = tag.vpn << PAGE_WIDTH;	387	va = tag.vpn << MMU_PAGE_WIDTH;
379		388
380	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,	389	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
381	tag.context);	390	tag.context);
382	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	391	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
383	dump_istate(istate);	392	dump_istate(istate);
384	panic("%s\n", str);	393	panic("%s\n", str);
385	}	394	}
386		395
387	void dump_sfsr_and_sfar(void)	396	void dump_sfsr_and_sfar(void)
388	{	397	{
389	tlb_sfsr_reg_t sfsr;	398	tlb_sfsr_reg_t sfsr;
390	uintptr_t sfar;	399	uintptr_t sfar;
391		400
392	sfsr.value = dtlb_sfsr_read();	401	sfsr.value = dtlb_sfsr_read();
393	sfar = dtlb_sfar_read();	402	sfar = dtlb_sfar_read();
394		403
395	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "	404	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
396	"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,	405	"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
397	sfsr.ow, sfsr.fv);	406	sfsr.ow, sfsr.fv);
398	printf("DTLB SFAR: address=%p\n", sfar);	407	printf("DTLB SFAR: address=%p\n", sfar);
399		408
400	dtlb_sfsr_write(0);	409	dtlb_sfsr_write(0);
401	}	410	}
402		411
403	/** Invalidate all unlocked ITLB and DTLB entries. */	412	/** Invalidate all unlocked ITLB and DTLB entries. */
404	void tlb_invalidate_all(void)	413	void tlb_invalidate_all(void)
405	{	414	{
406	int i;	415	int i;
407	tlb_data_t d;	416	tlb_data_t d;
408	tlb_tag_read_reg_t t;	417	tlb_tag_read_reg_t t;
409		418
410	/*	419	/*
411	* Walk all ITLB and DTLB entries and remove all unlocked mappings.	420	* Walk all ITLB and DTLB entries and remove all unlocked mappings.
412	*	421	*
413	* The kernel doesn't use global mappings so any locked global mappings	422	* The kernel doesn't use global mappings so any locked global mappings
414	* found must have been created by someone else. Their only purpose now	423	* found must have been created by someone else. Their only purpose now
415	* is to collide with proper mappings. Invalidate immediately. It should	424	* is to collide with proper mappings. Invalidate immediately. It should
416	* be safe to invalidate them as late as now.	425	* be safe to invalidate them as late as now.
417	*/	426	*/
418		427
419	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	428	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
420	d.value = itlb_data_access_read(i);	429	d.value = itlb_data_access_read(i);
421	if (!d.l \|\| d.g) {	430	if (!d.l \|\| d.g) {
422	t.value = itlb_tag_read_read(i);	431	t.value = itlb_tag_read_read(i);
423	d.v = false;	432	d.v = false;
424	itlb_tag_access_write(t.value);	433	itlb_tag_access_write(t.value);
425	itlb_data_access_write(i, d.value);	434	itlb_data_access_write(i, d.value);
426	}	435	}
427	}	436	}
428		437
429	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	438	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
430	d.value = dtlb_data_access_read(i);	439	d.value = dtlb_data_access_read(i);
431	if (!d.l \|\| d.g) {	440	if (!d.l \|\| d.g) {
432	t.value = dtlb_tag_read_read(i);	441	t.value = dtlb_tag_read_read(i);
433	d.v = false;	442	d.v = false;
434	dtlb_tag_access_write(t.value);	443	dtlb_tag_access_write(t.value);
435	dtlb_data_access_write(i, d.value);	444	dtlb_data_access_write(i, d.value);
436	}	445	}
437	}	446	}
438		447
439	}	448	}
440		449
441	/** Invalidate all ITLB and DTLB entries that belong to specified ASID	450	/** Invalidate all ITLB and DTLB entries that belong to specified ASID
442	* (Context).	451	* (Context).
443	*	452	*
444	* @param asid Address Space ID.	453	* @param asid Address Space ID.
445	*/	454	*/
446	void tlb_invalidate_asid(asid_t asid)	455	void tlb_invalidate_asid(asid_t asid)
447	{	456	{
448	tlb_context_reg_t pc_save, ctx;	457	tlb_context_reg_t pc_save, ctx;
449		458
450	/* switch to nucleus because we are mapped by the primary context */	459	/* switch to nucleus because we are mapped by the primary context */
451	nucleus_enter();	460	nucleus_enter();
452		461
453	ctx.v = pc_save.v = mmu_primary_context_read();	462	ctx.v = pc_save.v = mmu_primary_context_read();
454	ctx.context = asid;	463	ctx.context = asid;
455	mmu_primary_context_write(ctx.v);	464	mmu_primary_context_write(ctx.v);
456		465
457	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	466	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
458	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	467	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
459		468
460	mmu_primary_context_write(pc_save.v);	469	mmu_primary_context_write(pc_save.v);
461		470
462	nucleus_leave();	471	nucleus_leave();
463	}	472	}
464		473
465	/** Invalidate all ITLB and DTLB entries for specified page range in specified	474	/** Invalidate all ITLB and DTLB entries for specified page range in specified
466	* address space.	475	* address space.
467	*	476	*
468	* @param asid Address Space ID.	477	* @param asid Address Space ID.
469	* @param page First page which to sweep out from ITLB and DTLB.	478	* @param page First page which to sweep out from ITLB and DTLB.
470	* @param cnt Number of ITLB and DTLB entries to invalidate.	479	* @param cnt Number of ITLB and DTLB entries to invalidate.
471	*/	480	*/
472	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	481	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
473	{	482	{
474	int i;	483	int i;
475	tlb_context_reg_t pc_save, ctx;	484	tlb_context_reg_t pc_save, ctx;
476		485
477	/* switch to nucleus because we are mapped by the primary context */	486	/* switch to nucleus because we are mapped by the primary context */
478	nucleus_enter();	487	nucleus_enter();
479		488
480	ctx.v = pc_save.v = mmu_primary_context_read();	489	ctx.v = pc_save.v = mmu_primary_context_read();
481	ctx.context = asid;	490	ctx.context = asid;
482	mmu_primary_context_write(ctx.v);	491	mmu_primary_context_write(ctx.v);
483		492
484	for (i = 0; i < cnt; i++) {	493	for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
485	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,	494	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
486	page + i * PAGE_SIZE);	495	page + i * MMU_PAGE_SIZE);
487	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,	496	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
488	page + i * PAGE_SIZE);	497	page + i * MMU_PAGE_SIZE);
489	}	498	}
490		499
491	mmu_primary_context_write(pc_save.v);	500	mmu_primary_context_write(pc_save.v);

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(root)/trunk/kernel/arch/sparc64/src/mm/tlb.c – Rev 2134 → 2141