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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
36 | #include <mm/tlb.h> |
37 | #include <mm/as.h> |
37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
38 | #include <mm/asid.h> |
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
41 | #include <arch/mm/mmu.h> |
41 | #include <arch/mm/mmu.h> |
42 | #include <arch/interrupt.h> |
42 | #include <arch/interrupt.h> |
43 | #include <interrupt.h> |
43 | #include <interrupt.h> |
44 | #include <arch.h> |
44 | #include <arch.h> |
45 | #include <print.h> |
45 | #include <print.h> |
46 | #include <arch/types.h> |
46 | #include <arch/types.h> |
47 | #include <typedefs.h> |
- | |
48 | #include <config.h> |
47 | #include <config.h> |
49 | #include <arch/trap/trap.h> |
48 | #include <arch/trap/trap.h> |
50 | #include <arch/trap/exception.h> |
49 | #include <arch/trap/exception.h> |
51 | #include <panic.h> |
50 | #include <panic.h> |
52 | #include <arch/asm.h> |
51 | #include <arch/asm.h> |
53 | 52 | ||
54 | #ifdef CONFIG_TSB |
53 | #ifdef CONFIG_TSB |
55 | #include <arch/mm/tsb.h> |
54 | #include <arch/mm/tsb.h> |
56 | #endif |
55 | #endif |
57 | 56 | ||
58 | static void dtlb_pte_copy(pte_t *t, bool ro); |
57 | static void dtlb_pte_copy(pte_t *t, bool ro); |
59 | static void itlb_pte_copy(pte_t *t); |
58 | static void itlb_pte_copy(pte_t *t); |
60 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const |
59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const |
61 | char *str); |
60 | char *str); |
62 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
63 | tlb_tag_access_reg_t tag, const char *str); |
62 | tlb_tag_access_reg_t tag, const char *str); |
64 | static void do_fast_data_access_protection_fault(istate_t *istate, |
63 | static void do_fast_data_access_protection_fault(istate_t *istate, |
65 | tlb_tag_access_reg_t tag, const char *str); |
64 | tlb_tag_access_reg_t tag, const char *str); |
66 | 65 | ||
67 | char *context_encoding[] = { |
66 | char *context_encoding[] = { |
68 | "Primary", |
67 | "Primary", |
69 | "Secondary", |
68 | "Secondary", |
70 | "Nucleus", |
69 | "Nucleus", |
71 | "Reserved" |
70 | "Reserved" |
72 | }; |
71 | }; |
73 | 72 | ||
74 | void tlb_arch_init(void) |
73 | void tlb_arch_init(void) |
75 | { |
74 | { |
76 | /* |
75 | /* |
77 | * Invalidate all non-locked DTLB and ITLB entries. |
76 | * Invalidate all non-locked DTLB and ITLB entries. |
78 | */ |
77 | */ |
79 | tlb_invalidate_all(); |
78 | tlb_invalidate_all(); |
80 | 79 | ||
81 | /* |
80 | /* |
82 | * Clear both SFSRs. |
81 | * Clear both SFSRs. |
83 | */ |
82 | */ |
84 | dtlb_sfsr_write(0); |
83 | dtlb_sfsr_write(0); |
85 | itlb_sfsr_write(0); |
84 | itlb_sfsr_write(0); |
86 | } |
85 | } |
87 | 86 | ||
88 | /** Insert privileged mapping into DMMU TLB. |
87 | /** Insert privileged mapping into DMMU TLB. |
89 | * |
88 | * |
90 | * @param page Virtual page address. |
89 | * @param page Virtual page address. |
91 | * @param frame Physical frame address. |
90 | * @param frame Physical frame address. |
92 | * @param pagesize Page size. |
91 | * @param pagesize Page size. |
93 | * @param locked True for permanent mappings, false otherwise. |
92 | * @param locked True for permanent mappings, false otherwise. |
94 | * @param cacheable True if the mapping is cacheable, false otherwise. |
93 | * @param cacheable True if the mapping is cacheable, false otherwise. |
95 | */ |
94 | */ |
96 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool |
95 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool |
97 | locked, bool cacheable) |
96 | locked, bool cacheable) |
98 | { |
97 | { |
99 | tlb_tag_access_reg_t tag; |
98 | tlb_tag_access_reg_t tag; |
100 | tlb_data_t data; |
99 | tlb_data_t data; |
101 | page_address_t pg; |
100 | page_address_t pg; |
102 | frame_address_t fr; |
101 | frame_address_t fr; |
103 | 102 | ||
104 | pg.address = page; |
103 | pg.address = page; |
105 | fr.address = frame; |
104 | fr.address = frame; |
106 | 105 | ||
107 | tag.value = ASID_KERNEL; |
106 | tag.value = ASID_KERNEL; |
108 | tag.vpn = pg.vpn; |
107 | tag.vpn = pg.vpn; |
109 | 108 | ||
110 | dtlb_tag_access_write(tag.value); |
109 | dtlb_tag_access_write(tag.value); |
111 | 110 | ||
112 | data.value = 0; |
111 | data.value = 0; |
113 | data.v = true; |
112 | data.v = true; |
114 | data.size = pagesize; |
113 | data.size = pagesize; |
115 | data.pfn = fr.pfn; |
114 | data.pfn = fr.pfn; |
116 | data.l = locked; |
115 | data.l = locked; |
117 | data.cp = cacheable; |
116 | data.cp = cacheable; |
118 | #ifdef CONFIG_VIRT_IDX_DCACHE |
117 | #ifdef CONFIG_VIRT_IDX_DCACHE |
119 | data.cv = cacheable; |
118 | data.cv = cacheable; |
120 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
119 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
121 | data.p = true; |
120 | data.p = true; |
122 | data.w = true; |
121 | data.w = true; |
123 | data.g = false; |
122 | data.g = false; |
124 | 123 | ||
125 | dtlb_data_in_write(data.value); |
124 | dtlb_data_in_write(data.value); |
126 | } |
125 | } |
127 | 126 | ||
128 | /** Copy PTE to TLB. |
127 | /** Copy PTE to TLB. |
129 | * |
128 | * |
130 | * @param t Page Table Entry to be copied. |
129 | * @param t Page Table Entry to be copied. |
131 | * @param ro If true, the entry will be created read-only, regardless of its w |
130 | * @param ro If true, the entry will be created read-only, regardless of its w |
132 | * field. |
131 | * field. |
133 | */ |
132 | */ |
134 | void dtlb_pte_copy(pte_t *t, bool ro) |
133 | void dtlb_pte_copy(pte_t *t, bool ro) |
135 | { |
134 | { |
136 | tlb_tag_access_reg_t tag; |
135 | tlb_tag_access_reg_t tag; |
137 | tlb_data_t data; |
136 | tlb_data_t data; |
138 | page_address_t pg; |
137 | page_address_t pg; |
139 | frame_address_t fr; |
138 | frame_address_t fr; |
140 | 139 | ||
141 | pg.address = t->page; |
140 | pg.address = t->page; |
142 | fr.address = t->frame; |
141 | fr.address = t->frame; |
143 | 142 | ||
144 | tag.value = 0; |
143 | tag.value = 0; |
145 | tag.context = t->as->asid; |
144 | tag.context = t->as->asid; |
146 | tag.vpn = pg.vpn; |
145 | tag.vpn = pg.vpn; |
147 | 146 | ||
148 | dtlb_tag_access_write(tag.value); |
147 | dtlb_tag_access_write(tag.value); |
149 | 148 | ||
150 | data.value = 0; |
149 | data.value = 0; |
151 | data.v = true; |
150 | data.v = true; |
152 | data.size = PAGESIZE_8K; |
151 | data.size = PAGESIZE_8K; |
153 | data.pfn = fr.pfn; |
152 | data.pfn = fr.pfn; |
154 | data.l = false; |
153 | data.l = false; |
155 | data.cp = t->c; |
154 | data.cp = t->c; |
156 | #ifdef CONFIG_VIRT_IDX_DCACHE |
155 | #ifdef CONFIG_VIRT_IDX_DCACHE |
157 | data.cv = t->c; |
156 | data.cv = t->c; |
158 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
157 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
159 | data.p = t->k; /* p like privileged */ |
158 | data.p = t->k; /* p like privileged */ |
160 | data.w = ro ? false : t->w; |
159 | data.w = ro ? false : t->w; |
161 | data.g = t->g; |
160 | data.g = t->g; |
162 | 161 | ||
163 | dtlb_data_in_write(data.value); |
162 | dtlb_data_in_write(data.value); |
164 | } |
163 | } |
165 | 164 | ||
166 | /** Copy PTE to ITLB. |
165 | /** Copy PTE to ITLB. |
167 | * |
166 | * |
168 | * @param t Page Table Entry to be copied. |
167 | * @param t Page Table Entry to be copied. |
169 | */ |
168 | */ |
170 | void itlb_pte_copy(pte_t *t) |
169 | void itlb_pte_copy(pte_t *t) |
171 | { |
170 | { |
172 | tlb_tag_access_reg_t tag; |
171 | tlb_tag_access_reg_t tag; |
173 | tlb_data_t data; |
172 | tlb_data_t data; |
174 | page_address_t pg; |
173 | page_address_t pg; |
175 | frame_address_t fr; |
174 | frame_address_t fr; |
176 | 175 | ||
177 | pg.address = t->page; |
176 | pg.address = t->page; |
178 | fr.address = t->frame; |
177 | fr.address = t->frame; |
179 | 178 | ||
180 | tag.value = 0; |
179 | tag.value = 0; |
181 | tag.context = t->as->asid; |
180 | tag.context = t->as->asid; |
182 | tag.vpn = pg.vpn; |
181 | tag.vpn = pg.vpn; |
183 | 182 | ||
184 | itlb_tag_access_write(tag.value); |
183 | itlb_tag_access_write(tag.value); |
185 | 184 | ||
186 | data.value = 0; |
185 | data.value = 0; |
187 | data.v = true; |
186 | data.v = true; |
188 | data.size = PAGESIZE_8K; |
187 | data.size = PAGESIZE_8K; |
189 | data.pfn = fr.pfn; |
188 | data.pfn = fr.pfn; |
190 | data.l = false; |
189 | data.l = false; |
191 | data.cp = t->c; |
190 | data.cp = t->c; |
192 | data.p = t->k; /* p like privileged */ |
191 | data.p = t->k; /* p like privileged */ |
193 | data.w = false; |
192 | data.w = false; |
194 | data.g = t->g; |
193 | data.g = t->g; |
195 | 194 | ||
196 | itlb_data_in_write(data.value); |
195 | itlb_data_in_write(data.value); |
197 | } |
196 | } |
198 | 197 | ||
199 | /** ITLB miss handler. */ |
198 | /** ITLB miss handler. */ |
200 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
199 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
201 | { |
200 | { |
202 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
201 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
203 | pte_t *t; |
202 | pte_t *t; |
204 | 203 | ||
205 | page_table_lock(AS, true); |
204 | page_table_lock(AS, true); |
206 | t = page_mapping_find(AS, va); |
205 | t = page_mapping_find(AS, va); |
207 | if (t && PTE_EXECUTABLE(t)) { |
206 | if (t && PTE_EXECUTABLE(t)) { |
208 | /* |
207 | /* |
209 | * The mapping was found in the software page hash table. |
208 | * The mapping was found in the software page hash table. |
210 | * Insert it into ITLB. |
209 | * Insert it into ITLB. |
211 | */ |
210 | */ |
212 | t->a = true; |
211 | t->a = true; |
213 | itlb_pte_copy(t); |
212 | itlb_pte_copy(t); |
214 | #ifdef CONFIG_TSB |
213 | #ifdef CONFIG_TSB |
215 | itsb_pte_copy(t); |
214 | itsb_pte_copy(t); |
216 | #endif |
215 | #endif |
217 | page_table_unlock(AS, true); |
216 | page_table_unlock(AS, true); |
218 | } else { |
217 | } else { |
219 | /* |
218 | /* |
220 | * Forward the page fault to the address space page fault |
219 | * Forward the page fault to the address space page fault |
221 | * handler. |
220 | * handler. |
222 | */ |
221 | */ |
223 | page_table_unlock(AS, true); |
222 | page_table_unlock(AS, true); |
224 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
223 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
225 | do_fast_instruction_access_mmu_miss_fault(istate, |
224 | do_fast_instruction_access_mmu_miss_fault(istate, |
226 | __FUNCTION__); |
225 | __FUNCTION__); |
227 | } |
226 | } |
228 | } |
227 | } |
229 | } |
228 | } |
230 | 229 | ||
231 | /** DTLB miss handler. |
230 | /** DTLB miss handler. |
232 | * |
231 | * |
233 | * Note that some faults (e.g. kernel faults) were already resolved by the |
232 | * Note that some faults (e.g. kernel faults) were already resolved by the |
234 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
233 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
235 | */ |
234 | */ |
236 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
235 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
237 | { |
236 | { |
238 | tlb_tag_access_reg_t tag; |
237 | tlb_tag_access_reg_t tag; |
239 | uintptr_t va; |
238 | uintptr_t va; |
240 | pte_t *t; |
239 | pte_t *t; |
241 | 240 | ||
242 | tag.value = dtlb_tag_access_read(); |
241 | tag.value = dtlb_tag_access_read(); |
243 | va = tag.vpn << PAGE_WIDTH; |
242 | va = tag.vpn << PAGE_WIDTH; |
244 | 243 | ||
245 | if (tag.context == ASID_KERNEL) { |
244 | if (tag.context == ASID_KERNEL) { |
246 | if (!tag.vpn) { |
245 | if (!tag.vpn) { |
247 | /* NULL access in kernel */ |
246 | /* NULL access in kernel */ |
248 | do_fast_data_access_mmu_miss_fault(istate, tag, |
247 | do_fast_data_access_mmu_miss_fault(istate, tag, |
249 | __FUNCTION__); |
248 | __FUNCTION__); |
250 | } |
249 | } |
251 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
250 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
252 | "kernel page fault."); |
251 | "kernel page fault."); |
253 | } |
252 | } |
254 | 253 | ||
255 | page_table_lock(AS, true); |
254 | page_table_lock(AS, true); |
256 | t = page_mapping_find(AS, va); |
255 | t = page_mapping_find(AS, va); |
257 | if (t) { |
256 | if (t) { |
258 | /* |
257 | /* |
259 | * The mapping was found in the software page hash table. |
258 | * The mapping was found in the software page hash table. |
260 | * Insert it into DTLB. |
259 | * Insert it into DTLB. |
261 | */ |
260 | */ |
262 | t->a = true; |
261 | t->a = true; |
263 | dtlb_pte_copy(t, true); |
262 | dtlb_pte_copy(t, true); |
264 | #ifdef CONFIG_TSB |
263 | #ifdef CONFIG_TSB |
265 | dtsb_pte_copy(t, true); |
264 | dtsb_pte_copy(t, true); |
266 | #endif |
265 | #endif |
267 | page_table_unlock(AS, true); |
266 | page_table_unlock(AS, true); |
268 | } else { |
267 | } else { |
269 | /* |
268 | /* |
270 | * Forward the page fault to the address space page fault handler. |
269 | * Forward the page fault to the address space page fault handler. |
271 | */ |
270 | */ |
272 | page_table_unlock(AS, true); |
271 | page_table_unlock(AS, true); |
273 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
272 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
274 | do_fast_data_access_mmu_miss_fault(istate, tag, |
273 | do_fast_data_access_mmu_miss_fault(istate, tag, |
275 | __FUNCTION__); |
274 | __FUNCTION__); |
276 | } |
275 | } |
277 | } |
276 | } |
278 | } |
277 | } |
279 | 278 | ||
280 | /** DTLB protection fault handler. */ |
279 | /** DTLB protection fault handler. */ |
281 | void fast_data_access_protection(int n, istate_t *istate) |
280 | void fast_data_access_protection(int n, istate_t *istate) |
282 | { |
281 | { |
283 | tlb_tag_access_reg_t tag; |
282 | tlb_tag_access_reg_t tag; |
284 | uintptr_t va; |
283 | uintptr_t va; |
285 | pte_t *t; |
284 | pte_t *t; |
286 | 285 | ||
287 | tag.value = dtlb_tag_access_read(); |
286 | tag.value = dtlb_tag_access_read(); |
288 | va = tag.vpn << PAGE_WIDTH; |
287 | va = tag.vpn << PAGE_WIDTH; |
289 | 288 | ||
290 | page_table_lock(AS, true); |
289 | page_table_lock(AS, true); |
291 | t = page_mapping_find(AS, va); |
290 | t = page_mapping_find(AS, va); |
292 | if (t && PTE_WRITABLE(t)) { |
291 | if (t && PTE_WRITABLE(t)) { |
293 | /* |
292 | /* |
294 | * The mapping was found in the software page hash table and is |
293 | * The mapping was found in the software page hash table and is |
295 | * writable. Demap the old mapping and insert an updated mapping |
294 | * writable. Demap the old mapping and insert an updated mapping |
296 | * into DTLB. |
295 | * into DTLB. |
297 | */ |
296 | */ |
298 | t->a = true; |
297 | t->a = true; |
299 | t->d = true; |
298 | t->d = true; |
300 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va); |
299 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va); |
301 | dtlb_pte_copy(t, false); |
300 | dtlb_pte_copy(t, false); |
302 | #ifdef CONFIG_TSB |
301 | #ifdef CONFIG_TSB |
303 | dtsb_pte_copy(t, false); |
302 | dtsb_pte_copy(t, false); |
304 | #endif |
303 | #endif |
305 | page_table_unlock(AS, true); |
304 | page_table_unlock(AS, true); |
306 | } else { |
305 | } else { |
307 | /* |
306 | /* |
308 | * Forward the page fault to the address space page fault |
307 | * Forward the page fault to the address space page fault |
309 | * handler. |
308 | * handler. |
310 | */ |
309 | */ |
311 | page_table_unlock(AS, true); |
310 | page_table_unlock(AS, true); |
312 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
311 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
313 | do_fast_data_access_protection_fault(istate, tag, |
312 | do_fast_data_access_protection_fault(istate, tag, |
314 | __FUNCTION__); |
313 | __FUNCTION__); |
315 | } |
314 | } |
316 | } |
315 | } |
317 | } |
316 | } |
318 | 317 | ||
319 | /** Print contents of both TLBs. */ |
318 | /** Print contents of both TLBs. */ |
320 | void tlb_print(void) |
319 | void tlb_print(void) |
321 | { |
320 | { |
322 | int i; |
321 | int i; |
323 | tlb_data_t d; |
322 | tlb_data_t d; |
324 | tlb_tag_read_reg_t t; |
323 | tlb_tag_read_reg_t t; |
325 | 324 | ||
326 | printf("I-TLB contents:\n"); |
325 | printf("I-TLB contents:\n"); |
327 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
326 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
328 | d.value = itlb_data_access_read(i); |
327 | d.value = itlb_data_access_read(i); |
329 | t.value = itlb_tag_read_read(i); |
328 | t.value = itlb_tag_read_read(i); |
330 | 329 | ||
331 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
330 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
332 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
331 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
333 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
332 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
334 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
333 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
335 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
334 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
336 | } |
335 | } |
337 | 336 | ||
338 | printf("D-TLB contents:\n"); |
337 | printf("D-TLB contents:\n"); |
339 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
338 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
340 | d.value = dtlb_data_access_read(i); |
339 | d.value = dtlb_data_access_read(i); |
341 | t.value = dtlb_tag_read_read(i); |
340 | t.value = dtlb_tag_read_read(i); |
342 | 341 | ||
343 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
342 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
344 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
343 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
345 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
344 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
346 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
345 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
347 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
346 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
348 | } |
347 | } |
349 | 348 | ||
350 | } |
349 | } |
351 | 350 | ||
352 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char |
351 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char |
353 | *str) |
352 | *str) |
354 | { |
353 | { |
355 | fault_if_from_uspace(istate, "%s\n", str); |
354 | fault_if_from_uspace(istate, "%s\n", str); |
356 | dump_istate(istate); |
355 | dump_istate(istate); |
357 | panic("%s\n", str); |
356 | panic("%s\n", str); |
358 | } |
357 | } |
359 | 358 | ||
360 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t |
359 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t |
361 | tag, const char *str) |
360 | tag, const char *str) |
362 | { |
361 | { |
363 | uintptr_t va; |
362 | uintptr_t va; |
364 | 363 | ||
365 | va = tag.vpn << PAGE_WIDTH; |
364 | va = tag.vpn << PAGE_WIDTH; |
366 | 365 | ||
367 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
366 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
368 | tag.context); |
367 | tag.context); |
369 | dump_istate(istate); |
368 | dump_istate(istate); |
370 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
369 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
371 | panic("%s\n", str); |
370 | panic("%s\n", str); |
372 | } |
371 | } |
373 | 372 | ||
374 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t |
373 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t |
375 | tag, const char *str) |
374 | tag, const char *str) |
376 | { |
375 | { |
377 | uintptr_t va; |
376 | uintptr_t va; |
378 | 377 | ||
379 | va = tag.vpn << PAGE_WIDTH; |
378 | va = tag.vpn << PAGE_WIDTH; |
380 | 379 | ||
381 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
380 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
382 | tag.context); |
381 | tag.context); |
383 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
382 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
384 | dump_istate(istate); |
383 | dump_istate(istate); |
385 | panic("%s\n", str); |
384 | panic("%s\n", str); |
386 | } |
385 | } |
387 | 386 | ||
388 | void dump_sfsr_and_sfar(void) |
387 | void dump_sfsr_and_sfar(void) |
389 | { |
388 | { |
390 | tlb_sfsr_reg_t sfsr; |
389 | tlb_sfsr_reg_t sfsr; |
391 | uintptr_t sfar; |
390 | uintptr_t sfar; |
392 | 391 | ||
393 | sfsr.value = dtlb_sfsr_read(); |
392 | sfsr.value = dtlb_sfsr_read(); |
394 | sfar = dtlb_sfar_read(); |
393 | sfar = dtlb_sfar_read(); |
395 | 394 | ||
396 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
395 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
397 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
396 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
398 | sfsr.ow, sfsr.fv); |
397 | sfsr.ow, sfsr.fv); |
399 | printf("DTLB SFAR: address=%p\n", sfar); |
398 | printf("DTLB SFAR: address=%p\n", sfar); |
400 | 399 | ||
401 | dtlb_sfsr_write(0); |
400 | dtlb_sfsr_write(0); |
402 | } |
401 | } |
403 | 402 | ||
404 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
403 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
405 | void tlb_invalidate_all(void) |
404 | void tlb_invalidate_all(void) |
406 | { |
405 | { |
407 | int i; |
406 | int i; |
408 | tlb_data_t d; |
407 | tlb_data_t d; |
409 | tlb_tag_read_reg_t t; |
408 | tlb_tag_read_reg_t t; |
410 | 409 | ||
411 | /* |
410 | /* |
412 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
411 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
413 | * |
412 | * |
414 | * The kernel doesn't use global mappings so any locked global mappings |
413 | * The kernel doesn't use global mappings so any locked global mappings |
415 | * found must have been created by someone else. Their only purpose now |
414 | * found must have been created by someone else. Their only purpose now |
416 | * is to collide with proper mappings. Invalidate immediately. It should |
415 | * is to collide with proper mappings. Invalidate immediately. It should |
417 | * be safe to invalidate them as late as now. |
416 | * be safe to invalidate them as late as now. |
418 | */ |
417 | */ |
419 | 418 | ||
420 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
419 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
421 | d.value = itlb_data_access_read(i); |
420 | d.value = itlb_data_access_read(i); |
422 | if (!d.l || d.g) { |
421 | if (!d.l || d.g) { |
423 | t.value = itlb_tag_read_read(i); |
422 | t.value = itlb_tag_read_read(i); |
424 | d.v = false; |
423 | d.v = false; |
425 | itlb_tag_access_write(t.value); |
424 | itlb_tag_access_write(t.value); |
426 | itlb_data_access_write(i, d.value); |
425 | itlb_data_access_write(i, d.value); |
427 | } |
426 | } |
428 | } |
427 | } |
429 | 428 | ||
430 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
429 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
431 | d.value = dtlb_data_access_read(i); |
430 | d.value = dtlb_data_access_read(i); |
432 | if (!d.l || d.g) { |
431 | if (!d.l || d.g) { |
433 | t.value = dtlb_tag_read_read(i); |
432 | t.value = dtlb_tag_read_read(i); |
434 | d.v = false; |
433 | d.v = false; |
435 | dtlb_tag_access_write(t.value); |
434 | dtlb_tag_access_write(t.value); |
436 | dtlb_data_access_write(i, d.value); |
435 | dtlb_data_access_write(i, d.value); |
437 | } |
436 | } |
438 | } |
437 | } |
439 | 438 | ||
440 | } |
439 | } |
441 | 440 | ||
442 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
441 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
443 | * (Context). |
442 | * (Context). |
444 | * |
443 | * |
445 | * @param asid Address Space ID. |
444 | * @param asid Address Space ID. |
446 | */ |
445 | */ |
447 | void tlb_invalidate_asid(asid_t asid) |
446 | void tlb_invalidate_asid(asid_t asid) |
448 | { |
447 | { |
449 | tlb_context_reg_t pc_save, ctx; |
448 | tlb_context_reg_t pc_save, ctx; |
450 | 449 | ||
451 | /* switch to nucleus because we are mapped by the primary context */ |
450 | /* switch to nucleus because we are mapped by the primary context */ |
452 | nucleus_enter(); |
451 | nucleus_enter(); |
453 | 452 | ||
454 | ctx.v = pc_save.v = mmu_primary_context_read(); |
453 | ctx.v = pc_save.v = mmu_primary_context_read(); |
455 | ctx.context = asid; |
454 | ctx.context = asid; |
456 | mmu_primary_context_write(ctx.v); |
455 | mmu_primary_context_write(ctx.v); |
457 | 456 | ||
458 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
457 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
459 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
458 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
460 | 459 | ||
461 | mmu_primary_context_write(pc_save.v); |
460 | mmu_primary_context_write(pc_save.v); |
462 | 461 | ||
463 | nucleus_leave(); |
462 | nucleus_leave(); |
464 | } |
463 | } |
465 | 464 | ||
466 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
465 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
467 | * address space. |
466 | * address space. |
468 | * |
467 | * |
469 | * @param asid Address Space ID. |
468 | * @param asid Address Space ID. |
470 | * @param page First page which to sweep out from ITLB and DTLB. |
469 | * @param page First page which to sweep out from ITLB and DTLB. |
471 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
470 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
472 | */ |
471 | */ |
473 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
472 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
474 | { |
473 | { |
475 | int i; |
474 | int i; |
476 | tlb_context_reg_t pc_save, ctx; |
475 | tlb_context_reg_t pc_save, ctx; |
477 | 476 | ||
478 | /* switch to nucleus because we are mapped by the primary context */ |
477 | /* switch to nucleus because we are mapped by the primary context */ |
479 | nucleus_enter(); |
478 | nucleus_enter(); |
480 | 479 | ||
481 | ctx.v = pc_save.v = mmu_primary_context_read(); |
480 | ctx.v = pc_save.v = mmu_primary_context_read(); |
482 | ctx.context = asid; |
481 | ctx.context = asid; |
483 | mmu_primary_context_write(ctx.v); |
482 | mmu_primary_context_write(ctx.v); |
484 | 483 | ||
485 | for (i = 0; i < cnt; i++) { |
484 | for (i = 0; i < cnt; i++) { |
486 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * |
485 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * |
487 | PAGE_SIZE); |
486 | PAGE_SIZE); |
488 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * |
487 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * |
489 | PAGE_SIZE); |
488 | PAGE_SIZE); |
490 | } |
489 | } |
491 | 490 | ||
492 | mmu_primary_context_write(pc_save.v); |
491 | mmu_primary_context_write(pc_save.v); |
493 | 492 | ||
494 | nucleus_leave(); |
493 | nucleus_leave(); |
495 | } |
494 | } |
496 | 495 | ||
497 | /** @} |
496 | /** @} |
498 | */ |
497 | */ |
499 | 498 |