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1
/*
1
/*
2
 * Copyright (C) 2005 Jakub Jermar
2
 * Copyright (C) 2005 Jakub Jermar
3
 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
 /** @addtogroup sparc64mm 
29
/** @addtogroup sparc64mm  
30
 * @{
30
 * @{
31
 */
31
 */
32
/** @file
32
/** @file
33
 */
33
 */
34
 
34
 
35
#include <arch/mm/tlb.h>
35
#include <arch/mm/tlb.h>
36
#include <mm/tlb.h>
36
#include <mm/tlb.h>
37
#include <arch/mm/frame.h>
37
#include <arch/mm/frame.h>
38
#include <arch/mm/page.h>
38
#include <arch/mm/page.h>
39
#include <arch/mm/mmu.h>
39
#include <arch/mm/mmu.h>
40
#include <mm/asid.h>
40
#include <mm/asid.h>
41
#include <print.h>
41
#include <print.h>
42
#include <arch/types.h>
42
#include <arch/types.h>
43
#include <typedefs.h>
43
#include <typedefs.h>
44
#include <config.h>
44
#include <config.h>
45
#include <arch/trap/trap.h>
45
#include <arch/trap/trap.h>
46
#include <panic.h>
46
#include <panic.h>
47
#include <arch/asm.h>
47
#include <arch/asm.h>
48
#include <symtab.h>
48
#include <symtab.h>
49
 
49
 
50
#include <arch/drivers/fb.h>
50
#include <arch/drivers/fb.h>
51
#include <arch/drivers/i8042.h>
51
#include <arch/drivers/i8042.h>
52
 
52
 
53
char *context_encoding[] = {
53
char *context_encoding[] = {
54
    "Primary",
54
    "Primary",
55
    "Secondary",
55
    "Secondary",
56
    "Nucleus",
56
    "Nucleus",
57
    "Reserved"
57
    "Reserved"
58
};
58
};
59
 
59
 
60
/** Initialize ITLB and DTLB.
-
 
61
 *
-
 
62
 * The goal of this function is to disable MMU
-
 
63
 * so that both TLBs can be purged and new
-
 
64
 * kernel 4M locked entry can be installed.
-
 
65
 * After TLB is initialized, MMU is enabled
-
 
66
 * again.
-
 
67
 *
-
 
68
 * Switching MMU off imposes the requirement for
-
 
69
 * the kernel to run in identity mapped environment.
-
 
70
 */
-
 
71
void tlb_arch_init(void)
60
void tlb_arch_init(void)
72
{
61
{
73
    tlb_tag_access_reg_t tag;
-
 
74
    tlb_data_t data;
-
 
75
    frame_address_t fr;
-
 
76
    page_address_t pg;
-
 
77
 
-
 
78
    fr.address = config.base;
-
 
79
    pg.address = config.base;
-
 
80
 
-
 
81
    immu_disable();
-
 
82
    dmmu_disable();
-
 
83
 
-
 
84
    /*
-
 
85
     * Demap everything, especially OpenFirmware.
-
 
86
     */
-
 
87
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
-
 
88
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
-
 
89
   
-
 
90
    /*
-
 
91
     * We do identity mapping of 4M-page at 4M.
-
 
92
     */
-
 
93
    tag.value = ASID_KERNEL;
-
 
94
    tag.vpn = pg.vpn;
-
 
95
 
-
 
96
    itlb_tag_access_write(tag.value);
-
 
97
    dtlb_tag_access_write(tag.value);
-
 
98
 
-
 
99
    data.value = 0;
-
 
100
    data.v = true;
-
 
101
    data.size = PAGESIZE_4M;
-
 
102
    data.pfn = fr.pfn;
-
 
103
    data.l = true;
-
 
104
    data.cp = 1;
-
 
105
    data.cv = 1;
-
 
106
    data.p = true;
-
 
107
    data.w = true;
-
 
108
    data.g = true;
-
 
109
 
-
 
110
    itlb_data_in_write(data.value);
-
 
111
    dtlb_data_in_write(data.value);
-
 
112
 
-
 
113
    /*
-
 
114
     * Register window traps can occur before MMU is enabled again.
-
 
115
     * This ensures that any such traps will be handled from
-
 
116
     * kernel identity mapped trap handler.
-
 
117
     */
-
 
118
    trap_switch_trap_table();
-
 
119
   
-
 
120
    tlb_invalidate_all();
-
 
121
 
-
 
122
    dmmu_enable();
-
 
123
    immu_enable();
-
 
124
}
62
}
125
 
63
 
126
/** Insert privileged mapping into DMMU TLB.
64
/** Insert privileged mapping into DMMU TLB.
127
 *
65
 *
128
 * @param page Virtual page address.
66
 * @param page Virtual page address.
129
 * @param frame Physical frame address.
67
 * @param frame Physical frame address.
130
 * @param pagesize Page size.
68
 * @param pagesize Page size.
131
 * @param locked True for permanent mappings, false otherwise.
69
 * @param locked True for permanent mappings, false otherwise.
132
 * @param cacheable True if the mapping is cacheable, false otherwise.
70
 * @param cacheable True if the mapping is cacheable, false otherwise.
133
 */
71
 */
134
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
72
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
135
{
73
{
136
    tlb_tag_access_reg_t tag;
74
    tlb_tag_access_reg_t tag;
137
    tlb_data_t data;
75
    tlb_data_t data;
138
    page_address_t pg;
76
    page_address_t pg;
139
    frame_address_t fr;
77
    frame_address_t fr;
140
 
78
 
141
    pg.address = page;
79
    pg.address = page;
142
    fr.address = frame;
80
    fr.address = frame;
143
 
81
 
144
    tag.value = ASID_KERNEL;
82
    tag.value = ASID_KERNEL;
145
    tag.vpn = pg.vpn;
83
    tag.vpn = pg.vpn;
146
 
84
 
147
    dtlb_tag_access_write(tag.value);
85
    dtlb_tag_access_write(tag.value);
148
 
86
 
149
    data.value = 0;
87
    data.value = 0;
150
    data.v = true;
88
    data.v = true;
151
    data.size = pagesize;
89
    data.size = pagesize;
152
    data.pfn = fr.pfn;
90
    data.pfn = fr.pfn;
153
    data.l = locked;
91
    data.l = locked;
154
    data.cp = cacheable;
92
    data.cp = cacheable;
155
    data.cv = cacheable;
93
    data.cv = cacheable;
156
    data.p = true;
94
    data.p = true;
157
    data.w = true;
95
    data.w = true;
158
    data.g = true;
96
    data.g = true;
159
 
97
 
160
    dtlb_data_in_write(data.value);
98
    dtlb_data_in_write(data.value);
161
}
99
}
162
 
100
 
163
/** ITLB miss handler. */
101
/** ITLB miss handler. */
164
void fast_instruction_access_mmu_miss(void)
102
void fast_instruction_access_mmu_miss(void)
165
{
103
{
166
    panic("%s\n", __FUNCTION__);
104
    panic("%s\n", __FUNCTION__);
167
}
105
}
168
 
106
 
169
/** DTLB miss handler. */
107
/** DTLB miss handler. */
170
void fast_data_access_mmu_miss(void)
108
void fast_data_access_mmu_miss(void)
171
{
109
{
172
    tlb_tag_access_reg_t tag;
110
    tlb_tag_access_reg_t tag;
173
    uintptr_t tpc;
111
    uintptr_t tpc;
174
    char *tpc_str;
112
    char *tpc_str;
175
 
113
 
176
    tag.value = dtlb_tag_access_read();
114
    tag.value = dtlb_tag_access_read();
177
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
115
    if (tag.context != ASID_KERNEL || tag.vpn == 0) {
178
        tpc = tpc_read();
116
        tpc = tpc_read();
179
        tpc_str = get_symtab_entry(tpc);
117
        tpc_str = get_symtab_entry(tpc);
180
 
118
 
181
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
119
        printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
182
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
120
        printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
183
        panic("%s\n", __FUNCTION__);
121
        panic("%s\n", __FUNCTION__);
184
    }
122
    }
185
 
123
 
186
    /*
124
    /*
187
     * Identity map piece of faulting kernel address space.
125
     * Identity map piece of faulting kernel address space.
188
     */
126
     */
189
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
127
    dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
190
}
128
}
191
 
129
 
192
/** DTLB protection fault handler. */
130
/** DTLB protection fault handler. */
193
void fast_data_access_protection(void)
131
void fast_data_access_protection(void)
194
{
132
{
195
    panic("%s\n", __FUNCTION__);
133
    panic("%s\n", __FUNCTION__);
196
}
134
}
197
 
135
 
198
/** Print contents of both TLBs. */
136
/** Print contents of both TLBs. */
199
void tlb_print(void)
137
void tlb_print(void)
200
{
138
{
201
    int i;
139
    int i;
202
    tlb_data_t d;
140
    tlb_data_t d;
203
    tlb_tag_read_reg_t t;
141
    tlb_tag_read_reg_t t;
204
   
142
   
205
    printf("I-TLB contents:\n");
143
    printf("I-TLB contents:\n");
206
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
144
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
207
        d.value = itlb_data_access_read(i);
145
        d.value = itlb_data_access_read(i);
208
        t.value = itlb_tag_read_read(i);
146
        t.value = itlb_tag_read_read(i);
209
       
147
       
210
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
148
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
211
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
149
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
212
    }
150
    }
213
 
151
 
214
    printf("D-TLB contents:\n");
152
    printf("D-TLB contents:\n");
215
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
153
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
216
        d.value = dtlb_data_access_read(i);
154
        d.value = dtlb_data_access_read(i);
217
        t.value = dtlb_tag_read_read(i);
155
        t.value = dtlb_tag_read_read(i);
218
       
156
       
219
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
157
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
220
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
158
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
221
    }
159
    }
222
 
160
 
223
}
161
}
224
 
162
 
225
/** Invalidate all unlocked ITLB and DTLB entries. */
163
/** Invalidate all unlocked ITLB and DTLB entries. */
226
void tlb_invalidate_all(void)
164
void tlb_invalidate_all(void)
227
{
165
{
228
    int i;
166
    int i;
229
    tlb_data_t d;
167
    tlb_data_t d;
230
    tlb_tag_read_reg_t t;
168
    tlb_tag_read_reg_t t;
231
 
169
 
232
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
170
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
233
        d.value = itlb_data_access_read(i);
171
        d.value = itlb_data_access_read(i);
234
        if (!d.l) {
172
        if (!d.l) {
235
            t.value = itlb_tag_read_read(i);
173
            t.value = itlb_tag_read_read(i);
236
            d.v = false;
174
            d.v = false;
237
            itlb_tag_access_write(t.value);
175
            itlb_tag_access_write(t.value);
238
            itlb_data_access_write(i, d.value);
176
            itlb_data_access_write(i, d.value);
239
        }
177
        }
240
    }
178
    }
241
   
179
   
242
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
180
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
243
        d.value = dtlb_data_access_read(i);
181
        d.value = dtlb_data_access_read(i);
244
        if (!d.l) {
182
        if (!d.l) {
245
            t.value = dtlb_tag_read_read(i);
183
            t.value = dtlb_tag_read_read(i);
246
            d.v = false;
184
            d.v = false;
247
            dtlb_tag_access_write(t.value);
185
            dtlb_tag_access_write(t.value);
248
            dtlb_data_access_write(i, d.value);
186
            dtlb_data_access_write(i, d.value);
249
        }
187
        }
250
    }
188
    }
251
   
189
   
252
}
190
}
253
 
191
 
254
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
192
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
255
 *
193
 *
256
 * @param asid Address Space ID.
194
 * @param asid Address Space ID.
257
 */
195
 */
258
void tlb_invalidate_asid(asid_t asid)
196
void tlb_invalidate_asid(asid_t asid)
259
{
197
{
260
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
198
    /* TODO: write asid to some Context register and encode the register in second parameter below. */
261
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
199
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
262
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
200
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
263
}
201
}
264
 
202
 
265
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
203
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
266
 *
204
 *
267
 * @param asid Address Space ID.
205
 * @param asid Address Space ID.
268
 * @param page First page which to sweep out from ITLB and DTLB.
206
 * @param page First page which to sweep out from ITLB and DTLB.
269
 * @param cnt Number of ITLB and DTLB entries to invalidate.
207
 * @param cnt Number of ITLB and DTLB entries to invalidate.
270
 */
208
 */
271
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
209
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
272
{
210
{
273
    int i;
211
    int i;
274
   
212
   
275
    for (i = 0; i < cnt; i++) {
213
    for (i = 0; i < cnt; i++) {
276
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
214
        /* TODO: write asid to some Context register and encode the register in second parameter below. */
277
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
215
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
278
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
216
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
279
    }
217
    }
280
}
218
}
281
 
219
 
282
 /** @}
220
/** @}
283
 */
221
 */
284
 
-
 
285
 
222