WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, bool ro);
static void itlb_pte_copy(pte_t *t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const
    char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
     tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate,
    tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * Invalidate all non-locked DTLB and ITLB entries.
     */
    tlb_invalidate_all();
 
    /*
     * Clear both SFSRs.
     */
    dtlb_sfsr_write(0);
    itlb_sfsr_write(0);
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool
    locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t Page Table Entry to be copied.
 * @param ro If true, the entry will be created read-only, regardless of its w
 *  field.
 */
void dtlb_pte_copy(pte_t *t, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    dtlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
   
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t Page Table Entry to be copied.
 */
void itlb_pte_copy(pte_t *t)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t);
#ifdef CONFIG_TSB
        itsb_pte_copy(t);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate,
                __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved by the
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
 
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
            "kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is
         * writable. Demap the old mapping and insert an updated mapping
         * into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
        dtlb_pte_copy(t, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault
         * handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag,
                __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
            "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
            "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
            t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
            d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char
    *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t
    tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
        tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t
    tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
        tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void dump_sfsr_and_sfar(void)
{
    tlb_sfsr_reg_t sfsr;
    uintptr_t sfar;
 
    sfsr.value = dtlb_sfsr_read();
    sfar = dtlb_sfar_read();
   
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
        "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
        sfsr.ow, sfsr.fv);
    printf("DTLB SFAR: address=%p\n", sfar);
   
    dtlb_sfsr_write(0);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
 * (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified
 * address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
            PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
            PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 2009	Rev 2048
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <typedefs.h>	47	#include <typedefs.h>
48	#include <config.h>	48	#include <config.h>
49	#include <arch/trap/trap.h>	49	#include <arch/trap/trap.h>
50	#include <arch/trap/exception.h>	50	#include <arch/trap/exception.h>
51	#include <panic.h>	51	#include <panic.h>
52	#include <arch/asm.h>	52	#include <arch/asm.h>
53		53
54	#ifdef CONFIG_TSB	54	#ifdef CONFIG_TSB
55	#include <arch/mm/tsb.h>	55	#include <arch/mm/tsb.h>
56	#endif	56	#endif
57		57
58	static void dtlb_pte_copy(pte_t *t, bool ro);	58	static void dtlb_pte_copy(pte_t *t, bool ro);
59	static void itlb_pte_copy(pte_t *t);	59	static void itlb_pte_copy(pte_t *t);
60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);	60	static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const
-		61	char *str);
61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	62	static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-		63	tlb_tag_access_reg_t tag, const char *str);
62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	64	static void do_fast_data_access_protection_fault(istate_t *istate,
-		65	tlb_tag_access_reg_t tag, const char *str);
63		66
64	char *context_encoding[] = {	67	char *context_encoding[] = {
65	"Primary",	68	"Primary",
66	"Secondary",	69	"Secondary",
67	"Nucleus",	70	"Nucleus",
68	"Reserved"	71	"Reserved"
69	};	72	};
70		73
71	void tlb_arch_init(void)	74	void tlb_arch_init(void)
72	{	75	{
73	/*	76	/*
74	* Invalidate all non-locked DTLB and ITLB entries.	77	* Invalidate all non-locked DTLB and ITLB entries.
75	*/	78	*/
76	tlb_invalidate_all();	79	tlb_invalidate_all();
77		80
78	/*	81	/*
79	* Clear both SFSRs.	82	* Clear both SFSRs.
80	*/	83	*/
81	dtlb_sfsr_write(0);	84	dtlb_sfsr_write(0);
82	itlb_sfsr_write(0);	85	itlb_sfsr_write(0);
83	}	86	}
84		87
85	/** Insert privileged mapping into DMMU TLB.	88	/** Insert privileged mapping into DMMU TLB.
86	*	89	*
87	* @param page Virtual page address.	90	* @param page Virtual page address.
88	* @param frame Physical frame address.	91	* @param frame Physical frame address.
89	* @param pagesize Page size.	92	* @param pagesize Page size.
90	* @param locked True for permanent mappings, false otherwise.	93	* @param locked True for permanent mappings, false otherwise.
91	* @param cacheable True if the mapping is cacheable, false otherwise.	94	* @param cacheable True if the mapping is cacheable, false otherwise.
92	*/	95	*/
93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	96	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool
-		97	locked, bool cacheable)
94	{	98	{
95	tlb_tag_access_reg_t tag;	99	tlb_tag_access_reg_t tag;
96	tlb_data_t data;	100	tlb_data_t data;
97	page_address_t pg;	101	page_address_t pg;
98	frame_address_t fr;	102	frame_address_t fr;
99		103
100	pg.address = page;	104	pg.address = page;
101	fr.address = frame;	105	fr.address = frame;
102		106
103	tag.value = ASID_KERNEL;	107	tag.value = ASID_KERNEL;
104	tag.vpn = pg.vpn;	108	tag.vpn = pg.vpn;
105		109
106	dtlb_tag_access_write(tag.value);	110	dtlb_tag_access_write(tag.value);
107		111
108	data.value = 0;	112	data.value = 0;
109	data.v = true;	113	data.v = true;
110	data.size = pagesize;	114	data.size = pagesize;
111	data.pfn = fr.pfn;	115	data.pfn = fr.pfn;
112	data.l = locked;	116	data.l = locked;
113	data.cp = cacheable;	117	data.cp = cacheable;
114	#ifdef CONFIG_VIRT_IDX_DCACHE	118	#ifdef CONFIG_VIRT_IDX_DCACHE
115	data.cv = cacheable;	119	data.cv = cacheable;
116	#endif /* CONFIG_VIRT_IDX_DCACHE */	120	#endif /* CONFIG_VIRT_IDX_DCACHE */
117	data.p = true;	121	data.p = true;
118	data.w = true;	122	data.w = true;
119	data.g = false;	123	data.g = false;
120		124
121	dtlb_data_in_write(data.value);	125	dtlb_data_in_write(data.value);
122	}	126	}
123		127
124	/** Copy PTE to TLB.	128	/** Copy PTE to TLB.
125	*	129	*
126	* @param t Page Table Entry to be copied.	130	* @param t Page Table Entry to be copied.
127	* @param ro If true, the entry will be created read-only, regardless of its w field.	131	* @param ro If true, the entry will be created read-only, regardless of its w
-		132	* field.
128	*/	133	*/
129	void dtlb_pte_copy(pte_t *t, bool ro)	134	void dtlb_pte_copy(pte_t *t, bool ro)
130	{	135	{
131	tlb_tag_access_reg_t tag;	136	tlb_tag_access_reg_t tag;
132	tlb_data_t data;	137	tlb_data_t data;
133	page_address_t pg;	138	page_address_t pg;
134	frame_address_t fr;	139	frame_address_t fr;
135		140
136	pg.address = t->page;	141	pg.address = t->page;
137	fr.address = t->frame;	142	fr.address = t->frame;
138		143
139	tag.value = 0;	144	tag.value = 0;
140	tag.context = t->as->asid;	145	tag.context = t->as->asid;
141	tag.vpn = pg.vpn;	146	tag.vpn = pg.vpn;
142		147
143	dtlb_tag_access_write(tag.value);	148	dtlb_tag_access_write(tag.value);
144		149
145	data.value = 0;	150	data.value = 0;
146	data.v = true;	151	data.v = true;
147	data.size = PAGESIZE_8K;	152	data.size = PAGESIZE_8K;
148	data.pfn = fr.pfn;	153	data.pfn = fr.pfn;
149	data.l = false;	154	data.l = false;
150	data.cp = t->c;	155	data.cp = t->c;
151	#ifdef CONFIG_VIRT_IDX_DCACHE	156	#ifdef CONFIG_VIRT_IDX_DCACHE
152	data.cv = t->c;	157	data.cv = t->c;
153	#endif /* CONFIG_VIRT_IDX_DCACHE */	158	#endif /* CONFIG_VIRT_IDX_DCACHE */
154	data.p = t->k; /* p like privileged */	159	data.p = t->k; /* p like privileged */
155	data.w = ro ? false : t->w;	160	data.w = ro ? false : t->w;
156	data.g = t->g;	161	data.g = t->g;
157		162
158	dtlb_data_in_write(data.value);	163	dtlb_data_in_write(data.value);
159	}	164	}
160		165
161	/** Copy PTE to ITLB.	166	/** Copy PTE to ITLB.
162	*	167	*
163	* @param t Page Table Entry to be copied.	168	* @param t Page Table Entry to be copied.
164	*/	169	*/
165	void itlb_pte_copy(pte_t *t)	170	void itlb_pte_copy(pte_t *t)
166	{	171	{
167	tlb_tag_access_reg_t tag;	172	tlb_tag_access_reg_t tag;
168	tlb_data_t data;	173	tlb_data_t data;
169	page_address_t pg;	174	page_address_t pg;
170	frame_address_t fr;	175	frame_address_t fr;
171		176
172	pg.address = t->page;	177	pg.address = t->page;
173	fr.address = t->frame;	178	fr.address = t->frame;
174		179
175	tag.value = 0;	180	tag.value = 0;
176	tag.context = t->as->asid;	181	tag.context = t->as->asid;
177	tag.vpn = pg.vpn;	182	tag.vpn = pg.vpn;
178		183
179	itlb_tag_access_write(tag.value);	184	itlb_tag_access_write(tag.value);
180		185
181	data.value = 0;	186	data.value = 0;
182	data.v = true;	187	data.v = true;
183	data.size = PAGESIZE_8K;	188	data.size = PAGESIZE_8K;
184	data.pfn = fr.pfn;	189	data.pfn = fr.pfn;
185	data.l = false;	190	data.l = false;
186	data.cp = t->c;	191	data.cp = t->c;
187	data.p = t->k; /* p like privileged */	192	data.p = t->k; /* p like privileged */
188	data.w = false;	193	data.w = false;
189	data.g = t->g;	194	data.g = t->g;
190		195
191	itlb_data_in_write(data.value);	196	itlb_data_in_write(data.value);
192	}	197	}
193		198
194	/** ITLB miss handler. */	199	/** ITLB miss handler. */
195	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	200	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
196	{	201	{
197	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	202	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
198	pte_t *t;	203	pte_t *t;
199		204
200	page_table_lock(AS, true);	205	page_table_lock(AS, true);
201	t = page_mapping_find(AS, va);	206	t = page_mapping_find(AS, va);
202	if (t && PTE_EXECUTABLE(t)) {	207	if (t && PTE_EXECUTABLE(t)) {
203	/*	208	/*
204	* The mapping was found in the software page hash table.	209	* The mapping was found in the software page hash table.
205	* Insert it into ITLB.	210	* Insert it into ITLB.
206	*/	211	*/
207	t->a = true;	212	t->a = true;
208	itlb_pte_copy(t);	213	itlb_pte_copy(t);
209	#ifdef CONFIG_TSB	214	#ifdef CONFIG_TSB
210	itsb_pte_copy(t);	215	itsb_pte_copy(t);
211	#endif	216	#endif
212	page_table_unlock(AS, true);	217	page_table_unlock(AS, true);
213	} else {	218	} else {
214	/*	219	/*
215	* Forward the page fault to the address space page fault handler.	220	* Forward the page fault to the address space page fault
-		221	* handler.
216	*/	222	*/
217	page_table_unlock(AS, true);	223	page_table_unlock(AS, true);
218	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	224	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
219	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);	225	do_fast_instruction_access_mmu_miss_fault(istate,
-		226	__FUNCTION__);
220	}	227	}
221	}	228	}
222	}	229	}
223		230
224	/** DTLB miss handler.	231	/** DTLB miss handler.
225	*	232	*
226	* Note that some faults (e.g. kernel faults) were already resolved	233	* Note that some faults (e.g. kernel faults) were already resolved by the
227	* by the low-level, assembly language part of the fast_data_access_mmu_miss	234	* low-level, assembly language part of the fast_data_access_mmu_miss handler.
228	* handler.	-
229	*/	235	*/
230	void fast_data_access_mmu_miss(int n, istate_t *istate)	236	void fast_data_access_mmu_miss(int n, istate_t *istate)
231	{	237	{
232	tlb_tag_access_reg_t tag;	238	tlb_tag_access_reg_t tag;
233	uintptr_t va;	239	uintptr_t va;
234	pte_t *t;	240	pte_t *t;
235		241
236	tag.value = dtlb_tag_access_read();	242	tag.value = dtlb_tag_access_read();
237	va = tag.vpn << PAGE_WIDTH;	243	va = tag.vpn << PAGE_WIDTH;
238		244
239	if (tag.context == ASID_KERNEL) {	245	if (tag.context == ASID_KERNEL) {
240	if (!tag.vpn) {	246	if (!tag.vpn) {
241	/* NULL access in kernel */	247	/* NULL access in kernel */
242	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	248	do_fast_data_access_mmu_miss_fault(istate, tag,
-		249	__FUNCTION__);
243	}	250	}
244	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");	251	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
-		252	"kernel page fault.");
245	}	253	}
246		254
247	page_table_lock(AS, true);	255	page_table_lock(AS, true);
248	t = page_mapping_find(AS, va);	256	t = page_mapping_find(AS, va);
249	if (t) {	257	if (t) {
250	/*	258	/*
251	* The mapping was found in the software page hash table.	259	* The mapping was found in the software page hash table.
252	* Insert it into DTLB.	260	* Insert it into DTLB.
253	*/	261	*/
254	t->a = true;	262	t->a = true;
255	dtlb_pte_copy(t, true);	263	dtlb_pte_copy(t, true);
256	#ifdef CONFIG_TSB	264	#ifdef CONFIG_TSB
257	dtsb_pte_copy(t, true);	265	dtsb_pte_copy(t, true);
258	#endif	266	#endif
259	page_table_unlock(AS, true);	267	page_table_unlock(AS, true);
260	} else {	268	} else {
261	/*	269	/*
262	* Forward the page fault to the address space page fault handler.	270	* Forward the page fault to the address space page fault handler.
263	*/	271	*/
264	page_table_unlock(AS, true);	272	page_table_unlock(AS, true);
265	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	273	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
266	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	274	do_fast_data_access_mmu_miss_fault(istate, tag,
-		275	__FUNCTION__);
267	}	276	}
268	}	277	}
269	}	278	}
270		279
271	/** DTLB protection fault handler. */	280	/** DTLB protection fault handler. */
272	void fast_data_access_protection(int n, istate_t *istate)	281	void fast_data_access_protection(int n, istate_t *istate)
273	{	282	{
274	tlb_tag_access_reg_t tag;	283	tlb_tag_access_reg_t tag;
275	uintptr_t va;	284	uintptr_t va;
276	pte_t *t;	285	pte_t *t;
277		286
278	tag.value = dtlb_tag_access_read();	287	tag.value = dtlb_tag_access_read();
279	va = tag.vpn << PAGE_WIDTH;	288	va = tag.vpn << PAGE_WIDTH;
280		289
281	page_table_lock(AS, true);	290	page_table_lock(AS, true);
282	t = page_mapping_find(AS, va);	291	t = page_mapping_find(AS, va);
283	if (t && PTE_WRITABLE(t)) {	292	if (t && PTE_WRITABLE(t)) {
284	/*	293	/*
285	* The mapping was found in the software page hash table and is writable.	294	* The mapping was found in the software page hash table and is
286	* Demap the old mapping and insert an updated mapping into DTLB.	295	* writable. Demap the old mapping and insert an updated mapping
-		296	* into DTLB.
287	*/	297	*/
288	t->a = true;	298	t->a = true;
289	t->d = true;	299	t->d = true;
290	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	300	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
291	dtlb_pte_copy(t, false);	301	dtlb_pte_copy(t, false);
292	#ifdef CONFIG_TSB	302	#ifdef CONFIG_TSB
293	dtsb_pte_copy(t, false);	303	dtsb_pte_copy(t, false);
294	#endif	304	#endif
295	page_table_unlock(AS, true);	305	page_table_unlock(AS, true);
296	} else {	306	} else {
297	/*	307	/*
298	* Forward the page fault to the address space page fault handler.	308	* Forward the page fault to the address space page fault
-		309	* handler.
299	*/	310	*/
300	page_table_unlock(AS, true);	311	page_table_unlock(AS, true);
301	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	312	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
302	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);	313	do_fast_data_access_protection_fault(istate, tag,
-		314	__FUNCTION__);
303	}	315	}
304	}	316	}
305	}	317	}
306		318
307	/** Print contents of both TLBs. */	319	/** Print contents of both TLBs. */
308	void tlb_print(void)	320	void tlb_print(void)
309	{	321	{
310	int i;	322	int i;
311	tlb_data_t d;	323	tlb_data_t d;
312	tlb_tag_read_reg_t t;	324	tlb_tag_read_reg_t t;
313		325
314	printf("I-TLB contents:\n");	326	printf("I-TLB contents:\n");
315	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	327	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
316	d.value = itlb_data_access_read(i);	328	d.value = itlb_data_access_read(i);
317	t.value = itlb_tag_read_read(i);	329	t.value = itlb_tag_read_read(i);
318		330
319	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	331	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-		332	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-		333	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
320	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	334	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-		335	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
321	}	336	}
322		337
323	printf("D-TLB contents:\n");	338	printf("D-TLB contents:\n");
324	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	339	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
325	d.value = dtlb_data_access_read(i);	340	d.value = dtlb_data_access_read(i);
326	t.value = dtlb_tag_read_read(i);	341	t.value = dtlb_tag_read_read(i);
327		342
328	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	343	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
-		344	"ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
-		345	"cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
329	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	346	t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
-		347	d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
330	}	348	}
331		349
332	}	350	}
333		351
334	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)	352	void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char
-		353	*str)
335	{	354	{
336	fault_if_from_uspace(istate, "%s\n", str);	355	fault_if_from_uspace(istate, "%s\n", str);
337	dump_istate(istate);	356	dump_istate(istate);
338	panic("%s\n", str);	357	panic("%s\n", str);
339	}	358	}
340		359
341	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	360	void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t
-		361	tag, const char *str)
342	{	362	{
343	uintptr_t va;	363	uintptr_t va;
344		364
345	va = tag.vpn << PAGE_WIDTH;	365	va = tag.vpn << PAGE_WIDTH;
346		366
347	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	367	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
-		368	tag.context);
348	dump_istate(istate);	369	dump_istate(istate);
349	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	370	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
350	panic("%s\n", str);	371	panic("%s\n", str);
351	}	372	}
352		373
353	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	374	void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t
-		375	tag, const char *str)
354	{	376	{
355	uintptr_t va;	377	uintptr_t va;
356		378
357	va = tag.vpn << PAGE_WIDTH;	379	va = tag.vpn << PAGE_WIDTH;
358		380
359	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	381	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
-		382	tag.context);
360	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	383	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
361	dump_istate(istate);	384	dump_istate(istate);
362	panic("%s\n", str);	385	panic("%s\n", str);
363	}	386	}
364		387
365	void dump_sfsr_and_sfar(void)	388	void dump_sfsr_and_sfar(void)
366	{	389	{
367	tlb_sfsr_reg_t sfsr;	390	tlb_sfsr_reg_t sfsr;
368	uintptr_t sfar;	391	uintptr_t sfar;
369		392
370	sfsr.value = dtlb_sfsr_read();	393	sfsr.value = dtlb_sfsr_read();
371	sfar = dtlb_sfar_read();	394	sfar = dtlb_sfar_read();
372		395
373	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",	396	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
374	sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);	397	"fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
-		398	sfsr.ow, sfsr.fv);
375	printf("DTLB SFAR: address=%p\n", sfar);	399	printf("DTLB SFAR: address=%p\n", sfar);
376		400
377	dtlb_sfsr_write(0);	401	dtlb_sfsr_write(0);
378	}	402	}
379		403
380	/** Invalidate all unlocked ITLB and DTLB entries. */	404	/** Invalidate all unlocked ITLB and DTLB entries. */
381	void tlb_invalidate_all(void)	405	void tlb_invalidate_all(void)
382	{	406	{
383	int i;	407	int i;
384	tlb_data_t d;	408	tlb_data_t d;
385	tlb_tag_read_reg_t t;	409	tlb_tag_read_reg_t t;
386		410
387	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	411	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
388	d.value = itlb_data_access_read(i);	412	d.value = itlb_data_access_read(i);
389	if (!d.l) {	413	if (!d.l) {
390	t.value = itlb_tag_read_read(i);	414	t.value = itlb_tag_read_read(i);
391	d.v = false;	415	d.v = false;
392	itlb_tag_access_write(t.value);	416	itlb_tag_access_write(t.value);
393	itlb_data_access_write(i, d.value);	417	itlb_data_access_write(i, d.value);
394	}	418	}
395	}	419	}
396		420
397	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	421	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
398	d.value = dtlb_data_access_read(i);	422	d.value = dtlb_data_access_read(i);
399	if (!d.l) {	423	if (!d.l) {
400	t.value = dtlb_tag_read_read(i);	424	t.value = dtlb_tag_read_read(i);
401	d.v = false;	425	d.v = false;
402	dtlb_tag_access_write(t.value);	426	dtlb_tag_access_write(t.value);
403	dtlb_data_access_write(i, d.value);	427	dtlb_data_access_write(i, d.value);
404	}	428	}
405	}	429	}
406		430
407	}	431	}
408		432
409	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	433	/** Invalidate all ITLB and DTLB entries that belong to specified ASID
-		434	* (Context).
410	*	435	*
411	* @param asid Address Space ID.	436	* @param asid Address Space ID.
412	*/	437	*/
413	void tlb_invalidate_asid(asid_t asid)	438	void tlb_invalidate_asid(asid_t asid)
414	{	439	{
415	tlb_context_reg_t pc_save, ctx;	440	tlb_context_reg_t pc_save, ctx;
416		441
417	/* switch to nucleus because we are mapped by the primary context */	442	/* switch to nucleus because we are mapped by the primary context */
418	nucleus_enter();	443	nucleus_enter();
419		444
420	ctx.v = pc_save.v = mmu_primary_context_read();	445	ctx.v = pc_save.v = mmu_primary_context_read();
421	ctx.context = asid;	446	ctx.context = asid;
422	mmu_primary_context_write(ctx.v);	447	mmu_primary_context_write(ctx.v);
423		448
424	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	449	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
425	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	450	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
426		451
427	mmu_primary_context_write(pc_save.v);	452	mmu_primary_context_write(pc_save.v);
428		453
429	nucleus_leave();	454	nucleus_leave();
430	}	455	}
431		456
432	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	457	/** Invalidate all ITLB and DTLB entries for specified page range in specified
-		458	* address space.
433	*	459	*
434	* @param asid Address Space ID.	460	* @param asid Address Space ID.
435	* @param page First page which to sweep out from ITLB and DTLB.	461	* @param page First page which to sweep out from ITLB and DTLB.
436	* @param cnt Number of ITLB and DTLB entries to invalidate.	462	* @param cnt Number of ITLB and DTLB entries to invalidate.
437	*/	463	*/
438	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	464	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
439	{	465	{
440	int i;	466	int i;
441	tlb_context_reg_t pc_save, ctx;	467	tlb_context_reg_t pc_save, ctx;
442		468
443	/* switch to nucleus because we are mapped by the primary context */	469	/* switch to nucleus because we are mapped by the primary context */
444	nucleus_enter();	470	nucleus_enter();
445		471
446	ctx.v = pc_save.v = mmu_primary_context_read();	472	ctx.v = pc_save.v = mmu_primary_context_read();
447	ctx.context = asid;	473	ctx.context = asid;
448	mmu_primary_context_write(ctx.v);	474	mmu_primary_context_write(ctx.v);
449		475
450	for (i = 0; i < cnt; i++) {	476	for (i = 0; i < cnt; i++) {
451	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	477	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
-		478	PAGE_SIZE);
452	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	479	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
-		480	PAGE_SIZE);
453	}	481	}
454		482
455	mmu_primary_context_write(pc_save.v);	483	mmu_primary_context_write(pc_save.v);
456		484
457	nucleus_leave();	485	nucleus_leave();
458	}	486	}
459		487
460	/** @}	488	/** @}
461	*/	489	*/
462		490

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(root)/trunk/kernel/arch/sparc64/src/mm/tlb.c – Rev 2009 → 2048