WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, bool ro);
static void itlb_pte_copy(pte_t *t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * Invalidate all non-locked DTLB and ITLB entries.
     */
    tlb_invalidate_all();
 
    /*
     * Clear both SFSRs.
     */
    dtlb_sfsr_write(0);
    itlb_sfsr_write(0);
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t Page Table Entry to be copied.
 * @param ro If true, the entry will be created read-only, regardless of its w field.
 */
void dtlb_pte_copy(pte_t *t, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    dtlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_DCACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_DCACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
   
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t Page Table Entry to be copied.
 */
void itlb_pte_copy(pte_t *t)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
 
 
 
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t);
#ifdef CONFIG_TSB
        itsb_pte_copy(t);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved
 * by the low-level, assembly language part of the fast_data_access_mmu_miss
 * handler.
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is writable.
         * Demap the old mapping and insert an updated mapping into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
        dtlb_pte_copy(t, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void dump_sfsr_and_sfar(void)
{
    tlb_sfsr_reg_t sfsr;
    uintptr_t sfar;
 
    sfsr.value = dtlb_sfsr_read();
    sfar = dtlb_sfar_read();
   
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
        sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
    printf("DTLB SFAR: address=%p\n", sfar);
   
    dtlb_sfsr_write(0);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 1996	Rev 2009
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <typedefs.h>	47	#include <typedefs.h>
48	#include <config.h>	48	#include <config.h>
49	#include <arch/trap/trap.h>	49	#include <arch/trap/trap.h>
50	#include <arch/trap/exception.h>	50	#include <arch/trap/exception.h>
51	#include <panic.h>	51	#include <panic.h>
52	#include <arch/asm.h>	52	#include <arch/asm.h>
53		53
54	#ifdef CONFIG_TSB	54	#ifdef CONFIG_TSB
55	#include <arch/mm/tsb.h>	55	#include <arch/mm/tsb.h>
56	#endif	56	#endif
57		57
58	static void dtlb_pte_copy(pte_t *t, bool ro);	58	static void dtlb_pte_copy(pte_t *t, bool ro);
59	static void itlb_pte_copy(pte_t *t);	59	static void itlb_pte_copy(pte_t *t);
60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);	60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);
61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
63		63
64	char *context_encoding[] = {	64	char *context_encoding[] = {
65	"Primary",	65	"Primary",
66	"Secondary",	66	"Secondary",
67	"Nucleus",	67	"Nucleus",
68	"Reserved"	68	"Reserved"
69	};	69	};
70		70
71	void tlb_arch_init(void)	71	void tlb_arch_init(void)
72	{	72	{
73	/*	73	/*
74	* Invalidate all non-locked DTLB and ITLB entries.	74	* Invalidate all non-locked DTLB and ITLB entries.
75	*/	75	*/
76	tlb_invalidate_all();	76	tlb_invalidate_all();
77		77
78	/*	78	/*
79	* Clear both SFSRs.	79	* Clear both SFSRs.
80	*/	80	*/
81	dtlb_sfsr_write(0);	81	dtlb_sfsr_write(0);
82	itlb_sfsr_write(0);	82	itlb_sfsr_write(0);
83	}	83	}
84		84
85	/** Insert privileged mapping into DMMU TLB.	85	/** Insert privileged mapping into DMMU TLB.
86	*	86	*
87	* @param page Virtual page address.	87	* @param page Virtual page address.
88	* @param frame Physical frame address.	88	* @param frame Physical frame address.
89	* @param pagesize Page size.	89	* @param pagesize Page size.
90	* @param locked True for permanent mappings, false otherwise.	90	* @param locked True for permanent mappings, false otherwise.
91	* @param cacheable True if the mapping is cacheable, false otherwise.	91	* @param cacheable True if the mapping is cacheable, false otherwise.
92	*/	92	*/
93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
94	{	94	{
95	tlb_tag_access_reg_t tag;	95	tlb_tag_access_reg_t tag;
96	tlb_data_t data;	96	tlb_data_t data;
97	page_address_t pg;	97	page_address_t pg;
98	frame_address_t fr;	98	frame_address_t fr;
99		99
100	pg.address = page;	100	pg.address = page;
101	fr.address = frame;	101	fr.address = frame;
102		102
103	tag.value = ASID_KERNEL;	103	tag.value = ASID_KERNEL;
104	tag.vpn = pg.vpn;	104	tag.vpn = pg.vpn;
105		105
106	dtlb_tag_access_write(tag.value);	106	dtlb_tag_access_write(tag.value);
107		107
108	data.value = 0;	108	data.value = 0;
109	data.v = true;	109	data.v = true;
110	data.size = pagesize;	110	data.size = pagesize;
111	data.pfn = fr.pfn;	111	data.pfn = fr.pfn;
112	data.l = locked;	112	data.l = locked;
113	data.cp = cacheable;	113	data.cp = cacheable;
114	#ifdef CONFIG_VIRT_IDX_CACHE	114	#ifdef CONFIG_VIRT_IDX_DCACHE
115	data.cv = cacheable;	115	data.cv = cacheable;
116	#endif /* CONFIG_VIRT_IDX_CACHE */	116	#endif /* CONFIG_VIRT_IDX_DCACHE */
117	data.p = true;	117	data.p = true;
118	data.w = true;	118	data.w = true;
119	data.g = false;	119	data.g = false;
120		120
121	dtlb_data_in_write(data.value);	121	dtlb_data_in_write(data.value);
122	}	122	}
123		123
124	/** Copy PTE to TLB.	124	/** Copy PTE to TLB.
125	*	125	*
126	* @param t Page Table Entry to be copied.	126	* @param t Page Table Entry to be copied.
127	* @param ro If true, the entry will be created read-only, regardless of its w field.	127	* @param ro If true, the entry will be created read-only, regardless of its w field.
128	*/	128	*/
129	void dtlb_pte_copy(pte_t *t, bool ro)	129	void dtlb_pte_copy(pte_t *t, bool ro)
130	{	130	{
131	tlb_tag_access_reg_t tag;	131	tlb_tag_access_reg_t tag;
132	tlb_data_t data;	132	tlb_data_t data;
133	page_address_t pg;	133	page_address_t pg;
134	frame_address_t fr;	134	frame_address_t fr;
135		135
136	pg.address = t->page;	136	pg.address = t->page;
137	fr.address = t->frame;	137	fr.address = t->frame;
138		138
139	tag.value = 0;	139	tag.value = 0;
140	tag.context = t->as->asid;	140	tag.context = t->as->asid;
141	tag.vpn = pg.vpn;	141	tag.vpn = pg.vpn;
142		142
143	dtlb_tag_access_write(tag.value);	143	dtlb_tag_access_write(tag.value);
144		144
145	data.value = 0;	145	data.value = 0;
146	data.v = true;	146	data.v = true;
147	data.size = PAGESIZE_8K;	147	data.size = PAGESIZE_8K;
148	data.pfn = fr.pfn;	148	data.pfn = fr.pfn;
149	data.l = false;	149	data.l = false;
150	data.cp = t->c;	150	data.cp = t->c;
151	#ifdef CONFIG_VIRT_IDX_CACHE	151	#ifdef CONFIG_VIRT_IDX_DCACHE
152	data.cv = t->c;	152	data.cv = t->c;
153	#endif /* CONFIG_VIRT_IDX_CACHE */	153	#endif /* CONFIG_VIRT_IDX_DCACHE */
154	data.p = t->k; /* p like privileged */	154	data.p = t->k; /* p like privileged */
155	data.w = ro ? false : t->w;	155	data.w = ro ? false : t->w;
156	data.g = t->g;	156	data.g = t->g;
157		157
158	dtlb_data_in_write(data.value);	158	dtlb_data_in_write(data.value);
159	}	159	}
160		160
161	/** Copy PTE to ITLB.	161	/** Copy PTE to ITLB.
162	*	162	*
163	* @param t Page Table Entry to be copied.	163	* @param t Page Table Entry to be copied.
164	*/	164	*/
165	void itlb_pte_copy(pte_t *t)	165	void itlb_pte_copy(pte_t *t)
166	{	166	{
167	tlb_tag_access_reg_t tag;	167	tlb_tag_access_reg_t tag;
168	tlb_data_t data;	168	tlb_data_t data;
169	page_address_t pg;	169	page_address_t pg;
170	frame_address_t fr;	170	frame_address_t fr;
171		171
172	pg.address = t->page;	172	pg.address = t->page;
173	fr.address = t->frame;	173	fr.address = t->frame;
174		174
175	tag.value = 0;	175	tag.value = 0;
176	tag.context = t->as->asid;	176	tag.context = t->as->asid;
177	tag.vpn = pg.vpn;	177	tag.vpn = pg.vpn;
178		178
179	itlb_tag_access_write(tag.value);	179	itlb_tag_access_write(tag.value);
180		180
181	data.value = 0;	181	data.value = 0;
182	data.v = true;	182	data.v = true;
183	data.size = PAGESIZE_8K;	183	data.size = PAGESIZE_8K;
184	data.pfn = fr.pfn;	184	data.pfn = fr.pfn;
185	data.l = false;	185	data.l = false;
186	data.cp = t->c;	186	data.cp = t->c;
187	#ifdef CONFIG_VIRT_IDX_CACHE	-
188	data.cv = t->c;	-
189	#endif /* CONFIG_VIRT_IDX_CACHE */	-
190	data.p = t->k; /* p like privileged */	187	data.p = t->k; /* p like privileged */
191	data.w = false;	188	data.w = false;
192	data.g = t->g;	189	data.g = t->g;
193		190
194	itlb_data_in_write(data.value);	191	itlb_data_in_write(data.value);
195	}	192	}
196		193
197	/** ITLB miss handler. */	194	/** ITLB miss handler. */
198	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	195	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
199	{	196	{
200	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	197	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
201	pte_t *t;	198	pte_t *t;
202		199
203	page_table_lock(AS, true);	200	page_table_lock(AS, true);
204	t = page_mapping_find(AS, va);	201	t = page_mapping_find(AS, va);
205	if (t && PTE_EXECUTABLE(t)) {	202	if (t && PTE_EXECUTABLE(t)) {
206	/*	203	/*
207	* The mapping was found in the software page hash table.	204	* The mapping was found in the software page hash table.
208	* Insert it into ITLB.	205	* Insert it into ITLB.
209	*/	206	*/
210	t->a = true;	207	t->a = true;
211	itlb_pte_copy(t);	208	itlb_pte_copy(t);
212	#ifdef CONFIG_TSB	209	#ifdef CONFIG_TSB
213	itsb_pte_copy(t);	210	itsb_pte_copy(t);
214	#endif	211	#endif
215	page_table_unlock(AS, true);	212	page_table_unlock(AS, true);
216	} else {	213	} else {
217	/*	214	/*
218	* Forward the page fault to the address space page fault handler.	215	* Forward the page fault to the address space page fault handler.
219	*/	216	*/
220	page_table_unlock(AS, true);	217	page_table_unlock(AS, true);
221	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	218	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
222	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);	219	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
223	}	220	}
224	}	221	}
225	}	222	}
226		223
227	/** DTLB miss handler.	224	/** DTLB miss handler.
228	*	225	*
229	* Note that some faults (e.g. kernel faults) were already resolved	226	* Note that some faults (e.g. kernel faults) were already resolved
230	* by the low-level, assembly language part of the fast_data_access_mmu_miss	227	* by the low-level, assembly language part of the fast_data_access_mmu_miss
231	* handler.	228	* handler.
232	*/	229	*/
233	void fast_data_access_mmu_miss(int n, istate_t *istate)	230	void fast_data_access_mmu_miss(int n, istate_t *istate)
234	{	231	{
235	tlb_tag_access_reg_t tag;	232	tlb_tag_access_reg_t tag;
236	uintptr_t va;	233	uintptr_t va;
237	pte_t *t;	234	pte_t *t;
238		235
239	tag.value = dtlb_tag_access_read();	236	tag.value = dtlb_tag_access_read();
240	va = tag.vpn << PAGE_WIDTH;	237	va = tag.vpn << PAGE_WIDTH;
241		238
242	if (tag.context == ASID_KERNEL) {	239	if (tag.context == ASID_KERNEL) {
243	if (!tag.vpn) {	240	if (!tag.vpn) {
244	/* NULL access in kernel */	241	/* NULL access in kernel */
245	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	242	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
246	}	243	}
247	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");	244	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
248	}	245	}
249		246
250	page_table_lock(AS, true);	247	page_table_lock(AS, true);
251	t = page_mapping_find(AS, va);	248	t = page_mapping_find(AS, va);
252	if (t) {	249	if (t) {
253	/*	250	/*
254	* The mapping was found in the software page hash table.	251	* The mapping was found in the software page hash table.
255	* Insert it into DTLB.	252	* Insert it into DTLB.
256	*/	253	*/
257	t->a = true;	254	t->a = true;
258	dtlb_pte_copy(t, true);	255	dtlb_pte_copy(t, true);
259	#ifdef CONFIG_TSB	256	#ifdef CONFIG_TSB
260	dtsb_pte_copy(t, true);	257	dtsb_pte_copy(t, true);
261	#endif	258	#endif
262	page_table_unlock(AS, true);	259	page_table_unlock(AS, true);
263	} else {	260	} else {
264	/*	261	/*
265	* Forward the page fault to the address space page fault handler.	262	* Forward the page fault to the address space page fault handler.
266	*/	263	*/
267	page_table_unlock(AS, true);	264	page_table_unlock(AS, true);
268	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	265	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
269	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	266	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
270	}	267	}
271	}	268	}
272	}	269	}
273		270
274	/** DTLB protection fault handler. */	271	/** DTLB protection fault handler. */
275	void fast_data_access_protection(int n, istate_t *istate)	272	void fast_data_access_protection(int n, istate_t *istate)
276	{	273	{
277	tlb_tag_access_reg_t tag;	274	tlb_tag_access_reg_t tag;
278	uintptr_t va;	275	uintptr_t va;
279	pte_t *t;	276	pte_t *t;
280		277
281	tag.value = dtlb_tag_access_read();	278	tag.value = dtlb_tag_access_read();
282	va = tag.vpn << PAGE_WIDTH;	279	va = tag.vpn << PAGE_WIDTH;
283		280
284	page_table_lock(AS, true);	281	page_table_lock(AS, true);
285	t = page_mapping_find(AS, va);	282	t = page_mapping_find(AS, va);
286	if (t && PTE_WRITABLE(t)) {	283	if (t && PTE_WRITABLE(t)) {
287	/*	284	/*
288	* The mapping was found in the software page hash table and is writable.	285	* The mapping was found in the software page hash table and is writable.
289	* Demap the old mapping and insert an updated mapping into DTLB.	286	* Demap the old mapping and insert an updated mapping into DTLB.
290	*/	287	*/
291	t->a = true;	288	t->a = true;
292	t->d = true;	289	t->d = true;
293	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	290	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
294	dtlb_pte_copy(t, false);	291	dtlb_pte_copy(t, false);
295	#ifdef CONFIG_TSB	292	#ifdef CONFIG_TSB
296	dtsb_pte_copy(t, false);	293	dtsb_pte_copy(t, false);
297	#endif	294	#endif
298	page_table_unlock(AS, true);	295	page_table_unlock(AS, true);
299	} else {	296	} else {
300	/*	297	/*
301	* Forward the page fault to the address space page fault handler.	298	* Forward the page fault to the address space page fault handler.
302	*/	299	*/
303	page_table_unlock(AS, true);	300	page_table_unlock(AS, true);
304	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	301	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
305	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);	302	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
306	}	303	}
307	}	304	}
308	}	305	}
309		306
310	/** Print contents of both TLBs. */	307	/** Print contents of both TLBs. */
311	void tlb_print(void)	308	void tlb_print(void)
312	{	309	{
313	int i;	310	int i;
314	tlb_data_t d;	311	tlb_data_t d;
315	tlb_tag_read_reg_t t;	312	tlb_tag_read_reg_t t;
316		313
317	printf("I-TLB contents:\n");	314	printf("I-TLB contents:\n");
318	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	315	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
319	d.value = itlb_data_access_read(i);	316	d.value = itlb_data_access_read(i);
320	t.value = itlb_tag_read_read(i);	317	t.value = itlb_tag_read_read(i);
321		318
322	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	319	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
323	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	320	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
324	}	321	}
325		322
326	printf("D-TLB contents:\n");	323	printf("D-TLB contents:\n");
327	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	324	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
328	d.value = dtlb_data_access_read(i);	325	d.value = dtlb_data_access_read(i);
329	t.value = dtlb_tag_read_read(i);	326	t.value = dtlb_tag_read_read(i);
330		327
331	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	328	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
332	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	329	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
333	}	330	}
334		331
335	}	332	}
336		333
337	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)	334	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)
338	{	335	{
339	fault_if_from_uspace(istate, "%s\n", str);	336	fault_if_from_uspace(istate, "%s\n", str);
340	dump_istate(istate);	337	dump_istate(istate);
341	panic("%s\n", str);	338	panic("%s\n", str);
342	}	339	}
343		340
344	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	341	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
345	{	342	{
346	uintptr_t va;	343	uintptr_t va;
347		344
348	va = tag.vpn << PAGE_WIDTH;	345	va = tag.vpn << PAGE_WIDTH;
349		346
350	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	347	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
351	dump_istate(istate);	348	dump_istate(istate);
352	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	349	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
353	panic("%s\n", str);	350	panic("%s\n", str);
354	}	351	}
355		352
356	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	353	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
357	{	354	{
358	uintptr_t va;	355	uintptr_t va;
359		356
360	va = tag.vpn << PAGE_WIDTH;	357	va = tag.vpn << PAGE_WIDTH;
361		358
362	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	359	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
363	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	360	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
364	dump_istate(istate);	361	dump_istate(istate);
365	panic("%s\n", str);	362	panic("%s\n", str);
366	}	363	}
367		364
368	void dump_sfsr_and_sfar(void)	365	void dump_sfsr_and_sfar(void)
369	{	366	{
370	tlb_sfsr_reg_t sfsr;	367	tlb_sfsr_reg_t sfsr;
371	uintptr_t sfar;	368	uintptr_t sfar;
372		369
373	sfsr.value = dtlb_sfsr_read();	370	sfsr.value = dtlb_sfsr_read();
374	sfar = dtlb_sfar_read();	371	sfar = dtlb_sfar_read();
375		372
376	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",	373	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
377	sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);	374	sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
378	printf("DTLB SFAR: address=%p\n", sfar);	375	printf("DTLB SFAR: address=%p\n", sfar);
379		376
380	dtlb_sfsr_write(0);	377	dtlb_sfsr_write(0);
381	}	378	}
382		379
383	/** Invalidate all unlocked ITLB and DTLB entries. */	380	/** Invalidate all unlocked ITLB and DTLB entries. */
384	void tlb_invalidate_all(void)	381	void tlb_invalidate_all(void)
385	{	382	{
386	int i;	383	int i;
387	tlb_data_t d;	384	tlb_data_t d;
388	tlb_tag_read_reg_t t;	385	tlb_tag_read_reg_t t;
389		386
390	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	387	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
391	d.value = itlb_data_access_read(i);	388	d.value = itlb_data_access_read(i);
392	if (!d.l) {	389	if (!d.l) {
393	t.value = itlb_tag_read_read(i);	390	t.value = itlb_tag_read_read(i);
394	d.v = false;	391	d.v = false;
395	itlb_tag_access_write(t.value);	392	itlb_tag_access_write(t.value);
396	itlb_data_access_write(i, d.value);	393	itlb_data_access_write(i, d.value);
397	}	394	}
398	}	395	}
399		396
400	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	397	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
401	d.value = dtlb_data_access_read(i);	398	d.value = dtlb_data_access_read(i);
402	if (!d.l) {	399	if (!d.l) {
403	t.value = dtlb_tag_read_read(i);	400	t.value = dtlb_tag_read_read(i);
404	d.v = false;	401	d.v = false;
405	dtlb_tag_access_write(t.value);	402	dtlb_tag_access_write(t.value);
406	dtlb_data_access_write(i, d.value);	403	dtlb_data_access_write(i, d.value);
407	}	404	}
408	}	405	}
409		406
410	}	407	}
411		408
412	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	409	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
413	*	410	*
414	* @param asid Address Space ID.	411	* @param asid Address Space ID.
415	*/	412	*/
416	void tlb_invalidate_asid(asid_t asid)	413	void tlb_invalidate_asid(asid_t asid)
417	{	414	{
418	tlb_context_reg_t pc_save, ctx;	415	tlb_context_reg_t pc_save, ctx;
419		416
420	/* switch to nucleus because we are mapped by the primary context */	417	/* switch to nucleus because we are mapped by the primary context */
421	nucleus_enter();	418	nucleus_enter();
422		419
423	ctx.v = pc_save.v = mmu_primary_context_read();	420	ctx.v = pc_save.v = mmu_primary_context_read();
424	ctx.context = asid;	421	ctx.context = asid;
425	mmu_primary_context_write(ctx.v);	422	mmu_primary_context_write(ctx.v);
426		423
427	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	424	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
428	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	425	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
429		426
430	mmu_primary_context_write(pc_save.v);	427	mmu_primary_context_write(pc_save.v);
431		428
432	nucleus_leave();	429	nucleus_leave();
433	}	430	}
434		431
435	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	432	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
436	*	433	*
437	* @param asid Address Space ID.	434	* @param asid Address Space ID.
438	* @param page First page which to sweep out from ITLB and DTLB.	435	* @param page First page which to sweep out from ITLB and DTLB.
439	* @param cnt Number of ITLB and DTLB entries to invalidate.	436	* @param cnt Number of ITLB and DTLB entries to invalidate.
440	*/	437	*/
441	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	438	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
442	{	439	{
443	int i;	440	int i;
444	tlb_context_reg_t pc_save, ctx;	441	tlb_context_reg_t pc_save, ctx;
445		442
446	/* switch to nucleus because we are mapped by the primary context */	443	/* switch to nucleus because we are mapped by the primary context */
447	nucleus_enter();	444	nucleus_enter();
448		445
449	ctx.v = pc_save.v = mmu_primary_context_read();	446	ctx.v = pc_save.v = mmu_primary_context_read();
450	ctx.context = asid;	447	ctx.context = asid;
451	mmu_primary_context_write(ctx.v);	448	mmu_primary_context_write(ctx.v);
452		449
453	for (i = 0; i < cnt; i++) {	450	for (i = 0; i < cnt; i++) {
454	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	451	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
455	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	452	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
456	}	453	}
457		454
458	mmu_primary_context_write(pc_save.v);	455	mmu_primary_context_write(pc_save.v);
459		456
460	nucleus_leave();	457	nucleus_leave();
461	}	458	}
462		459
463	/** @}	460	/** @}
464	*/	461	*/
465		462

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/mm/tlb.c @ 2048 – Rev 1996 → 2009