WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
static void dtlb_pte_copy(pte_t *t, bool ro);
static void itlb_pte_copy(pte_t *t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * Invalidate all non-locked DTLB and ITLB entries.
     */
    tlb_invalidate_all();
 
    /*
     * Clear both SFSRs.
     */
    dtlb_sfsr_write(0);
    itlb_sfsr_write(0);
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_CACHE
    data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_CACHE */
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t Page Table Entry to be copied.
 * @param ro If true, the entry will be created read-only, regardless of its w field.
 */
void dtlb_pte_copy(pte_t *t, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    dtlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
   
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to ITLB.
 *
 * @param t Page Table Entry to be copied.
 */
void itlb_pte_copy(pte_t *t)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
    data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t);
#ifdef CONFIG_TSB
        itsb_pte_copy(t);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved
 * by the low-level, assembly language part of the fast_data_access_mmu_miss
 * handler.
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, true);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, true);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is writable.
         * Demap the old mapping and insert an updated mapping into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
        dtlb_pte_copy(t, false);
#ifdef CONFIG_TSB
        dtsb_pte_copy(t, false);
#endif
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
{
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void dump_sfsr_and_sfar(void)
{
    tlb_sfsr_reg_t sfsr;
    uintptr_t sfar;
 
    sfsr.value = dtlb_sfsr_read();
    sfar = dtlb_sfar_read();
   
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
        sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
    printf("DTLB SFAR: address=%p\n", sfar);
   
    dtlb_sfsr_write(0);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 1946	Rev 1996
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <typedefs.h>	47	#include <typedefs.h>
48	#include <config.h>	48	#include <config.h>
49	#include <arch/trap/trap.h>	49	#include <arch/trap/trap.h>
50	#include <arch/trap/exception.h>	50	#include <arch/trap/exception.h>
51	#include <panic.h>	51	#include <panic.h>
52	#include <arch/asm.h>	52	#include <arch/asm.h>
53		53
54	#ifdef CONFIG_TSB	54	#ifdef CONFIG_TSB
55	#include <arch/mm/tsb.h>	55	#include <arch/mm/tsb.h>
56	#endif	56	#endif
57		57
58	static void dtlb_pte_copy(pte_t *t, bool ro);	58	static void dtlb_pte_copy(pte_t *t, bool ro);
59	static void itlb_pte_copy(pte_t *t);	59	static void itlb_pte_copy(pte_t *t);
60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);	60	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);
61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	61	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	62	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
63		63
64	char *context_encoding[] = {	64	char *context_encoding[] = {
65	"Primary",	65	"Primary",
66	"Secondary",	66	"Secondary",
67	"Nucleus",	67	"Nucleus",
68	"Reserved"	68	"Reserved"
69	};	69	};
70		70
71	void tlb_arch_init(void)	71	void tlb_arch_init(void)
72	{	72	{
73	/*	73	/*
74	* Invalidate all non-locked DTLB and ITLB entries.	74	* Invalidate all non-locked DTLB and ITLB entries.
75	*/	75	*/
76	tlb_invalidate_all();	76	tlb_invalidate_all();
77		77
78	/*	78	/*
79	* Clear both SFSRs.	79	* Clear both SFSRs.
80	*/	80	*/
81	dtlb_sfsr_write(0);	81	dtlb_sfsr_write(0);
82	itlb_sfsr_write(0);	82	itlb_sfsr_write(0);
83	}	83	}
84		84
85	/** Insert privileged mapping into DMMU TLB.	85	/** Insert privileged mapping into DMMU TLB.
86	*	86	*
87	* @param page Virtual page address.	87	* @param page Virtual page address.
88	* @param frame Physical frame address.	88	* @param frame Physical frame address.
89	* @param pagesize Page size.	89	* @param pagesize Page size.
90	* @param locked True for permanent mappings, false otherwise.	90	* @param locked True for permanent mappings, false otherwise.
91	* @param cacheable True if the mapping is cacheable, false otherwise.	91	* @param cacheable True if the mapping is cacheable, false otherwise.
92	*/	92	*/
93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	93	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
94	{	94	{
95	tlb_tag_access_reg_t tag;	95	tlb_tag_access_reg_t tag;
96	tlb_data_t data;	96	tlb_data_t data;
97	page_address_t pg;	97	page_address_t pg;
98	frame_address_t fr;	98	frame_address_t fr;
99		99
100	pg.address = page;	100	pg.address = page;
101	fr.address = frame;	101	fr.address = frame;
102		102
103	tag.value = ASID_KERNEL;	103	tag.value = ASID_KERNEL;
104	tag.vpn = pg.vpn;	104	tag.vpn = pg.vpn;
105		105
106	dtlb_tag_access_write(tag.value);	106	dtlb_tag_access_write(tag.value);
107		107
108	data.value = 0;	108	data.value = 0;
109	data.v = true;	109	data.v = true;
110	data.size = pagesize;	110	data.size = pagesize;
111	data.pfn = fr.pfn;	111	data.pfn = fr.pfn;
112	data.l = locked;	112	data.l = locked;
113	data.cp = cacheable;	113	data.cp = cacheable;
-		114	#ifdef CONFIG_VIRT_IDX_CACHE
114	data.cv = cacheable;	115	data.cv = cacheable;
-		116	#endif /* CONFIG_VIRT_IDX_CACHE */
115	data.p = true;	117	data.p = true;
116	data.w = true;	118	data.w = true;
117	data.g = false;	119	data.g = false;
118		120
119	dtlb_data_in_write(data.value);	121	dtlb_data_in_write(data.value);
120	}	122	}
121		123
122	/** Copy PTE to TLB.	124	/** Copy PTE to TLB.
123	*	125	*
124	* @param t Page Table Entry to be copied.	126	* @param t Page Table Entry to be copied.
125	* @param ro If true, the entry will be created read-only, regardless of its w field.	127	* @param ro If true, the entry will be created read-only, regardless of its w field.
126	*/	128	*/
127	void dtlb_pte_copy(pte_t *t, bool ro)	129	void dtlb_pte_copy(pte_t *t, bool ro)
128	{	130	{
129	tlb_tag_access_reg_t tag;	131	tlb_tag_access_reg_t tag;
130	tlb_data_t data;	132	tlb_data_t data;
131	page_address_t pg;	133	page_address_t pg;
132	frame_address_t fr;	134	frame_address_t fr;
133		135
134	pg.address = t->page;	136	pg.address = t->page;
135	fr.address = t->frame;	137	fr.address = t->frame;
136		138
137	tag.value = 0;	139	tag.value = 0;
138	tag.context = t->as->asid;	140	tag.context = t->as->asid;
139	tag.vpn = pg.vpn;	141	tag.vpn = pg.vpn;
140		142
141	dtlb_tag_access_write(tag.value);	143	dtlb_tag_access_write(tag.value);
142		144
143	data.value = 0;	145	data.value = 0;
144	data.v = true;	146	data.v = true;
145	data.size = PAGESIZE_8K;	147	data.size = PAGESIZE_8K;
146	data.pfn = fr.pfn;	148	data.pfn = fr.pfn;
147	data.l = false;	149	data.l = false;
148	data.cp = t->c;	150	data.cp = t->c;
-		151	#ifdef CONFIG_VIRT_IDX_CACHE
149	data.cv = t->c;	152	data.cv = t->c;
-		153	#endif /* CONFIG_VIRT_IDX_CACHE */
150	data.p = t->k; /* p like privileged */	154	data.p = t->k; /* p like privileged */
151	data.w = ro ? false : t->w;	155	data.w = ro ? false : t->w;
152	data.g = t->g;	156	data.g = t->g;
153		157
154	dtlb_data_in_write(data.value);	158	dtlb_data_in_write(data.value);
155	}	159	}
156		160
157	/** Copy PTE to ITLB.	161	/** Copy PTE to ITLB.
158	*	162	*
159	* @param t Page Table Entry to be copied.	163	* @param t Page Table Entry to be copied.
160	*/	164	*/
161	void itlb_pte_copy(pte_t *t)	165	void itlb_pte_copy(pte_t *t)
162	{	166	{
163	tlb_tag_access_reg_t tag;	167	tlb_tag_access_reg_t tag;
164	tlb_data_t data;	168	tlb_data_t data;
165	page_address_t pg;	169	page_address_t pg;
166	frame_address_t fr;	170	frame_address_t fr;
167		171
168	pg.address = t->page;	172	pg.address = t->page;
169	fr.address = t->frame;	173	fr.address = t->frame;
170		174
171	tag.value = 0;	175	tag.value = 0;
172	tag.context = t->as->asid;	176	tag.context = t->as->asid;
173	tag.vpn = pg.vpn;	177	tag.vpn = pg.vpn;
174		178
175	itlb_tag_access_write(tag.value);	179	itlb_tag_access_write(tag.value);
176		180
177	data.value = 0;	181	data.value = 0;
178	data.v = true;	182	data.v = true;
179	data.size = PAGESIZE_8K;	183	data.size = PAGESIZE_8K;
180	data.pfn = fr.pfn;	184	data.pfn = fr.pfn;
181	data.l = false;	185	data.l = false;
182	data.cp = t->c;	186	data.cp = t->c;
-		187	#ifdef CONFIG_VIRT_IDX_CACHE
183	data.cv = t->c;	188	data.cv = t->c;
-		189	#endif /* CONFIG_VIRT_IDX_CACHE */
184	data.p = t->k; /* p like privileged */	190	data.p = t->k; /* p like privileged */
185	data.w = false;	191	data.w = false;
186	data.g = t->g;	192	data.g = t->g;
187		193
188	itlb_data_in_write(data.value);	194	itlb_data_in_write(data.value);
189	}	195	}
190		196
191	/** ITLB miss handler. */	197	/** ITLB miss handler. */
192	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	198	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
193	{	199	{
194	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	200	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
195	pte_t *t;	201	pte_t *t;
196		202
197	page_table_lock(AS, true);	203	page_table_lock(AS, true);
198	t = page_mapping_find(AS, va);	204	t = page_mapping_find(AS, va);
199	if (t && PTE_EXECUTABLE(t)) {	205	if (t && PTE_EXECUTABLE(t)) {
200	/*	206	/*
201	* The mapping was found in the software page hash table.	207	* The mapping was found in the software page hash table.
202	* Insert it into ITLB.	208	* Insert it into ITLB.
203	*/	209	*/
204	t->a = true;	210	t->a = true;
205	itlb_pte_copy(t);	211	itlb_pte_copy(t);
206	#ifdef CONFIG_TSB	212	#ifdef CONFIG_TSB
207	itsb_pte_copy(t);	213	itsb_pte_copy(t);
208	#endif	214	#endif
209	page_table_unlock(AS, true);	215	page_table_unlock(AS, true);
210	} else {	216	} else {
211	/*	217	/*
212	* Forward the page fault to the address space page fault handler.	218	* Forward the page fault to the address space page fault handler.
213	*/	219	*/
214	page_table_unlock(AS, true);	220	page_table_unlock(AS, true);
215	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	221	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
216	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);	222	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
217	}	223	}
218	}	224	}
219	}	225	}
220		226
221	/** DTLB miss handler.	227	/** DTLB miss handler.
222	*	228	*
223	* Note that some faults (e.g. kernel faults) were already resolved	229	* Note that some faults (e.g. kernel faults) were already resolved
224	* by the low-level, assembly language part of the fast_data_access_mmu_miss	230	* by the low-level, assembly language part of the fast_data_access_mmu_miss
225	* handler.	231	* handler.
226	*/	232	*/
227	void fast_data_access_mmu_miss(int n, istate_t *istate)	233	void fast_data_access_mmu_miss(int n, istate_t *istate)
228	{	234	{
229	tlb_tag_access_reg_t tag;	235	tlb_tag_access_reg_t tag;
230	uintptr_t va;	236	uintptr_t va;
231	pte_t *t;	237	pte_t *t;
232		238
233	tag.value = dtlb_tag_access_read();	239	tag.value = dtlb_tag_access_read();
234	va = tag.vpn << PAGE_WIDTH;	240	va = tag.vpn << PAGE_WIDTH;
235		241
236	if (tag.context == ASID_KERNEL) {	242	if (tag.context == ASID_KERNEL) {
237	if (!tag.vpn) {	243	if (!tag.vpn) {
238	/* NULL access in kernel */	244	/* NULL access in kernel */
239	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	245	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
240	}	246	}
241	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");	247	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
242	}	248	}
243		249
244	page_table_lock(AS, true);	250	page_table_lock(AS, true);
245	t = page_mapping_find(AS, va);	251	t = page_mapping_find(AS, va);
246	if (t) {	252	if (t) {
247	/*	253	/*
248	* The mapping was found in the software page hash table.	254	* The mapping was found in the software page hash table.
249	* Insert it into DTLB.	255	* Insert it into DTLB.
250	*/	256	*/
251	t->a = true;	257	t->a = true;
252	dtlb_pte_copy(t, true);	258	dtlb_pte_copy(t, true);
253	#ifdef CONFIG_TSB	259	#ifdef CONFIG_TSB
254	dtsb_pte_copy(t, true);	260	dtsb_pte_copy(t, true);
255	#endif	261	#endif
256	page_table_unlock(AS, true);	262	page_table_unlock(AS, true);
257	} else {	263	} else {
258	/*	264	/*
259	* Forward the page fault to the address space page fault handler.	265	* Forward the page fault to the address space page fault handler.
260	*/	266	*/
261	page_table_unlock(AS, true);	267	page_table_unlock(AS, true);
262	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	268	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
263	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	269	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
264	}	270	}
265	}	271	}
266	}	272	}
267		273
268	/** DTLB protection fault handler. */	274	/** DTLB protection fault handler. */
269	void fast_data_access_protection(int n, istate_t *istate)	275	void fast_data_access_protection(int n, istate_t *istate)
270	{	276	{
271	tlb_tag_access_reg_t tag;	277	tlb_tag_access_reg_t tag;
272	uintptr_t va;	278	uintptr_t va;
273	pte_t *t;	279	pte_t *t;
274		280
275	tag.value = dtlb_tag_access_read();	281	tag.value = dtlb_tag_access_read();
276	va = tag.vpn << PAGE_WIDTH;	282	va = tag.vpn << PAGE_WIDTH;
277		283
278	page_table_lock(AS, true);	284	page_table_lock(AS, true);
279	t = page_mapping_find(AS, va);	285	t = page_mapping_find(AS, va);
280	if (t && PTE_WRITABLE(t)) {	286	if (t && PTE_WRITABLE(t)) {
281	/*	287	/*
282	* The mapping was found in the software page hash table and is writable.	288	* The mapping was found in the software page hash table and is writable.
283	* Demap the old mapping and insert an updated mapping into DTLB.	289	* Demap the old mapping and insert an updated mapping into DTLB.
284	*/	290	*/
285	t->a = true;	291	t->a = true;
286	t->d = true;	292	t->d = true;
287	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	293	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
288	dtlb_pte_copy(t, false);	294	dtlb_pte_copy(t, false);
289	#ifdef CONFIG_TSB	295	#ifdef CONFIG_TSB
290	dtsb_pte_copy(t, false);	296	dtsb_pte_copy(t, false);
291	#endif	297	#endif
292	page_table_unlock(AS, true);	298	page_table_unlock(AS, true);
293	} else {	299	} else {
294	/*	300	/*
295	* Forward the page fault to the address space page fault handler.	301	* Forward the page fault to the address space page fault handler.
296	*/	302	*/
297	page_table_unlock(AS, true);	303	page_table_unlock(AS, true);
298	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	304	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
299	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);	305	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
300	}	306	}
301	}	307	}
302	}	308	}
303		309
304	/** Print contents of both TLBs. */	310	/** Print contents of both TLBs. */
305	void tlb_print(void)	311	void tlb_print(void)
306	{	312	{
307	int i;	313	int i;
308	tlb_data_t d;	314	tlb_data_t d;
309	tlb_tag_read_reg_t t;	315	tlb_tag_read_reg_t t;
310		316
311	printf("I-TLB contents:\n");	317	printf("I-TLB contents:\n");
312	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	318	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
313	d.value = itlb_data_access_read(i);	319	d.value = itlb_data_access_read(i);
314	t.value = itlb_tag_read_read(i);	320	t.value = itlb_tag_read_read(i);
315		321
316	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	322	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
317	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	323	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
318	}	324	}
319		325
320	printf("D-TLB contents:\n");	326	printf("D-TLB contents:\n");
321	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	327	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
322	d.value = dtlb_data_access_read(i);	328	d.value = dtlb_data_access_read(i);
323	t.value = dtlb_tag_read_read(i);	329	t.value = dtlb_tag_read_read(i);
324		330
325	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	331	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
326	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	332	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
327	}	333	}
328		334
329	}	335	}
330		336
331	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)	337	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)
332	{	338	{
333	fault_if_from_uspace(istate, "%s\n", str);	339	fault_if_from_uspace(istate, "%s\n", str);
334	dump_istate(istate);	340	dump_istate(istate);
335	panic("%s\n", str);	341	panic("%s\n", str);
336	}	342	}
337		343
338	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	344	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
339	{	345	{
340	uintptr_t va;	346	uintptr_t va;
341		347
342	va = tag.vpn << PAGE_WIDTH;	348	va = tag.vpn << PAGE_WIDTH;
343		349
344	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	350	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
345	dump_istate(istate);	351	dump_istate(istate);
346	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	352	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
347	panic("%s\n", str);	353	panic("%s\n", str);
348	}	354	}
349		355
350	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	356	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
351	{	357	{
352	uintptr_t va;	358	uintptr_t va;
353		359
354	va = tag.vpn << PAGE_WIDTH;	360	va = tag.vpn << PAGE_WIDTH;
355		361
356	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	362	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
357	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	363	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
358	dump_istate(istate);	364	dump_istate(istate);
359	panic("%s\n", str);	365	panic("%s\n", str);
360	}	366	}
361		367
362	void dump_sfsr_and_sfar(void)	368	void dump_sfsr_and_sfar(void)
363	{	369	{
364	tlb_sfsr_reg_t sfsr;	370	tlb_sfsr_reg_t sfsr;
365	uintptr_t sfar;	371	uintptr_t sfar;
366		372
367	sfsr.value = dtlb_sfsr_read();	373	sfsr.value = dtlb_sfsr_read();
368	sfar = dtlb_sfar_read();	374	sfar = dtlb_sfar_read();
369		375
370	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",	376	printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
371	sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);	377	sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
372	printf("DTLB SFAR: address=%p\n", sfar);	378	printf("DTLB SFAR: address=%p\n", sfar);
373		379
374	dtlb_sfsr_write(0);	380	dtlb_sfsr_write(0);
375	}	381	}
376		382
377	/** Invalidate all unlocked ITLB and DTLB entries. */	383	/** Invalidate all unlocked ITLB and DTLB entries. */
378	void tlb_invalidate_all(void)	384	void tlb_invalidate_all(void)
379	{	385	{
380	int i;	386	int i;
381	tlb_data_t d;	387	tlb_data_t d;
382	tlb_tag_read_reg_t t;	388	tlb_tag_read_reg_t t;
383		389
384	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	390	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
385	d.value = itlb_data_access_read(i);	391	d.value = itlb_data_access_read(i);
386	if (!d.l) {	392	if (!d.l) {
387	t.value = itlb_tag_read_read(i);	393	t.value = itlb_tag_read_read(i);
388	d.v = false;	394	d.v = false;
389	itlb_tag_access_write(t.value);	395	itlb_tag_access_write(t.value);
390	itlb_data_access_write(i, d.value);	396	itlb_data_access_write(i, d.value);
391	}	397	}
392	}	398	}
393		399
394	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	400	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
395	d.value = dtlb_data_access_read(i);	401	d.value = dtlb_data_access_read(i);
396	if (!d.l) {	402	if (!d.l) {
397	t.value = dtlb_tag_read_read(i);	403	t.value = dtlb_tag_read_read(i);
398	d.v = false;	404	d.v = false;
399	dtlb_tag_access_write(t.value);	405	dtlb_tag_access_write(t.value);
400	dtlb_data_access_write(i, d.value);	406	dtlb_data_access_write(i, d.value);
401	}	407	}
402	}	408	}
403		409
404	}	410	}
405		411
406	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	412	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
407	*	413	*
408	* @param asid Address Space ID.	414	* @param asid Address Space ID.
409	*/	415	*/
410	void tlb_invalidate_asid(asid_t asid)	416	void tlb_invalidate_asid(asid_t asid)
411	{	417	{
412	tlb_context_reg_t pc_save, ctx;	418	tlb_context_reg_t pc_save, ctx;
413		419
414	/* switch to nucleus because we are mapped by the primary context */	420	/* switch to nucleus because we are mapped by the primary context */
415	nucleus_enter();	421	nucleus_enter();
416		422
417	ctx.v = pc_save.v = mmu_primary_context_read();	423	ctx.v = pc_save.v = mmu_primary_context_read();
418	ctx.context = asid;	424	ctx.context = asid;
419	mmu_primary_context_write(ctx.v);	425	mmu_primary_context_write(ctx.v);
420		426
421	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	427	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
422	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	428	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
423		429
424	mmu_primary_context_write(pc_save.v);	430	mmu_primary_context_write(pc_save.v);
425		431
426	nucleus_leave();	432	nucleus_leave();
427	}	433	}
428		434
429	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	435	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
430	*	436	*
431	* @param asid Address Space ID.	437	* @param asid Address Space ID.
432	* @param page First page which to sweep out from ITLB and DTLB.	438	* @param page First page which to sweep out from ITLB and DTLB.
433	* @param cnt Number of ITLB and DTLB entries to invalidate.	439	* @param cnt Number of ITLB and DTLB entries to invalidate.
434	*/	440	*/
435	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	441	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
436	{	442	{
437	int i;	443	int i;
438	tlb_context_reg_t pc_save, ctx;	444	tlb_context_reg_t pc_save, ctx;
439		445
440	/* switch to nucleus because we are mapped by the primary context */	446	/* switch to nucleus because we are mapped by the primary context */
441	nucleus_enter();	447	nucleus_enter();
442		448
443	ctx.v = pc_save.v = mmu_primary_context_read();	449	ctx.v = pc_save.v = mmu_primary_context_read();
444	ctx.context = asid;	450	ctx.context = asid;
445	mmu_primary_context_write(ctx.v);	451	mmu_primary_context_write(ctx.v);
446		452
447	for (i = 0; i < cnt; i++) {	453	for (i = 0; i < cnt; i++) {
448	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	454	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
449	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	455	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
450	}	456	}
451		457
452	mmu_primary_context_write(pc_save.v);	458	mmu_primary_context_write(pc_save.v);
453		459
454	nucleus_leave();	460	nucleus_leave();
455	}	461	}
456		462
457	/** @}	463	/** @}
458	*/	464	*/
459		465

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(root)/trunk/kernel/arch/sparc64/src/mm/tlb.c – Rev 1946 → 1996