WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tlb.c


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <mm/asid.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <arch/trap/exception.h>
#include <panic.h>
#include <arch/asm.h>
 
 
static void dtlb_pte_copy(pte_t *t, bool ro);
static void itlb_pte_copy(pte_t *t);
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
 
char *context_encoding[] = {
    "Primary",
    "Secondary",
    "Nucleus",
    "Reserved"
};
 
void tlb_arch_init(void)
{
    /*
     * TLBs are actually initialized early
     * in start.S.
     */
}
 
/** Insert privileged mapping into DMMU TLB.
 *
 * @param page Virtual page address.
 * @param frame Physical frame address.
 * @param pagesize Page size.
 * @param locked True for permanent mappings, false otherwise.
 * @param cacheable True if the mapping is cacheable, false otherwise.
 */
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = page;
    fr.address = frame;
 
    tag.value = ASID_KERNEL;
    tag.vpn = pg.vpn;
 
    dtlb_tag_access_write(tag.value);
 
    data.value = 0;
    data.v = true;
    data.size = pagesize;
    data.pfn = fr.pfn;
    data.l = locked;
    data.cp = cacheable;
    data.cv = cacheable;
    data.p = true;
    data.w = true;
    data.g = false;
 
    dtlb_data_in_write(data.value);
}
 
/** Copy PTE to TLB.
 *
 * @param t Page Table Entry to be copied.
 * @param ro If true, the entry will be created read-only, regardless of its w field.
 */
void dtlb_pte_copy(pte_t *t, bool ro)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    dtlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.cv = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = ro ? false : t->w;
    data.g = t->g;
   
    dtlb_data_in_write(data.value);
}
 
void itlb_pte_copy(pte_t *t)
{
    tlb_tag_access_reg_t tag;
    tlb_data_t data;
    page_address_t pg;
    frame_address_t fr;
 
    pg.address = t->page;
    fr.address = t->frame;
 
    tag.value = 0;
    tag.context = t->as->asid;
    tag.vpn = pg.vpn;
   
    itlb_tag_access_write(tag.value);
   
    data.value = 0;
    data.v = true;
    data.size = PAGESIZE_8K;
    data.pfn = fr.pfn;
    data.l = false;
    data.cp = t->c;
    data.cv = t->c;
    data.p = t->k;      /* p like privileged */
    data.w = false;
    data.g = t->g;
   
    itlb_data_in_write(data.value);
}
 
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
{
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
    pte_t *t;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_EXECUTABLE(t)) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into ITLB.
         */
        t->a = true;
        itlb_pte_copy(t);
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
            do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
        }
    }
}
 
/** DTLB miss handler.
 *
 * Note that some faults (e.g. kernel faults) were already resolved
 * by the low-level, assembly language part of the fast_data_access_mmu_miss
 * handler.
 */
void fast_data_access_mmu_miss(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    if (tag.context == ASID_KERNEL) {
        if (!tag.vpn) {
            /* NULL access in kernel */
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
    }
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t) {
        /*
         * The mapping was found in the software page hash table.
         * Insert it into DTLB.
         */
        t->a = true;
        dtlb_pte_copy(t, true);
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** DTLB protection fault handler. */
void fast_data_access_protection(int n, istate_t *istate)
{
    tlb_tag_access_reg_t tag;
    uintptr_t va;
    pte_t *t;
 
    tag.value = dtlb_tag_access_read();
    va = tag.vpn << PAGE_WIDTH;
 
    page_table_lock(AS, true);
    t = page_mapping_find(AS, va);
    if (t && PTE_WRITABLE(t)) {
        /*
         * The mapping was found in the software page hash table and is writable.
         * Demap the old mapping and insert an updated mapping into DTLB.
         */
        t->a = true;
        t->d = true;
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
        dtlb_pte_copy(t, false);
        page_table_unlock(AS, true);
    } else {
        /*
         * Forward the page fault to the address space page fault handler.
         */    
        page_table_unlock(AS, true);
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
            do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
        }
    }
}
 
/** Print contents of both TLBs. */
void tlb_print(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
   
    printf("I-TLB contents:\n");
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        t.value = itlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
    printf("D-TLB contents:\n");
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        t.value = dtlb_tag_read_read(i);
       
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
    }
 
}
 
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
{
 
 
    fault_if_from_uspace(istate, "%s\n", str);
    dump_istate(istate);
    panic("%s\n", str);
}
 
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    dump_istate(istate);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
 
    panic("%s\n", str);
}
 
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
{
    uintptr_t va;
 
 
    va = tag.vpn << PAGE_WIDTH;
 
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
    dump_istate(istate);
    panic("%s\n", str);
}
 
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
    int i;
    tlb_data_t d;
    tlb_tag_read_reg_t t;
 
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
        d.value = itlb_data_access_read(i);
        if (!d.l) {
            t.value = itlb_tag_read_read(i);
            d.v = false;
            itlb_tag_access_write(t.value);
            itlb_data_access_write(i, d.value);
        }
    }
   
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
        d.value = dtlb_data_access_read(i);
        if (!d.l) {
            t.value = dtlb_tag_read_read(i);
            d.v = false;
            dtlb_tag_access_write(t.value);
            dtlb_data_access_write(i, d.value);
        }
    }
   
}
 
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
 *
 * @param asid Address Space ID.
 */
void tlb_invalidate_asid(asid_t asid)
{
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
 *
 * @param asid Address Space ID.
 * @param page First page which to sweep out from ITLB and DTLB.
 * @param cnt Number of ITLB and DTLB entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    tlb_context_reg_t pc_save, ctx;
   
    /* switch to nucleus because we are mapped by the primary context */
    nucleus_enter();
   
    ctx.v = pc_save.v = mmu_primary_context_read();
    ctx.context = asid;
    mmu_primary_context_write(ctx.v);
   
    for (i = 0; i < cnt; i++) {
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
    }
   
    mmu_primary_context_write(pc_save.v);
   
    nucleus_leave();
}
 
/** @}
 */
 

Rev 1870	Rev 1880
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/tlb.h>	36	#include <mm/tlb.h>
37	#include <mm/as.h>	37	#include <mm/as.h>
38	#include <mm/asid.h>	38	#include <mm/asid.h>
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40	#include <arch/mm/page.h>	40	#include <arch/mm/page.h>
41	#include <arch/mm/mmu.h>	41	#include <arch/mm/mmu.h>
42	#include <arch/interrupt.h>	42	#include <arch/interrupt.h>
43	#include <interrupt.h>	43	#include <interrupt.h>
44	#include <arch.h>	44	#include <arch.h>
45	#include <print.h>	45	#include <print.h>
46	#include <arch/types.h>	46	#include <arch/types.h>
47	#include <typedefs.h>	47	#include <typedefs.h>
48	#include <config.h>	48	#include <config.h>
49	#include <arch/trap/trap.h>	49	#include <arch/trap/trap.h>
-		50	#include <arch/trap/exception.h>
50	#include <panic.h>	51	#include <panic.h>
51	#include <arch/asm.h>	52	#include <arch/asm.h>
52	#include <symtab.h>	-
53		53
54	static void dtlb_pte_copy(pte_t *t, bool ro);	54	static void dtlb_pte_copy(pte_t *t, bool ro);
55	static void itlb_pte_copy(pte_t *t);	55	static void itlb_pte_copy(pte_t *t);
56	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);	56	static void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str);
57	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	57	static void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
58	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);	58	static void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str);
59		59
60	char *context_encoding[] = {	60	char *context_encoding[] = {
61	"Primary",	61	"Primary",
62	"Secondary",	62	"Secondary",
63	"Nucleus",	63	"Nucleus",
64	"Reserved"	64	"Reserved"
65	};	65	};
66		66
67	void tlb_arch_init(void)	67	void tlb_arch_init(void)
68	{	68	{
69	/*	69	/*
70	* TLBs are actually initialized early	70	* TLBs are actually initialized early
71	* in start.S.	71	* in start.S.
72	*/	72	*/
73	}	73	}
74		74
75	/** Insert privileged mapping into DMMU TLB.	75	/** Insert privileged mapping into DMMU TLB.
76	*	76	*
77	* @param page Virtual page address.	77	* @param page Virtual page address.
78	* @param frame Physical frame address.	78	* @param frame Physical frame address.
79	* @param pagesize Page size.	79	* @param pagesize Page size.
80	* @param locked True for permanent mappings, false otherwise.	80	* @param locked True for permanent mappings, false otherwise.
81	* @param cacheable True if the mapping is cacheable, false otherwise.	81	* @param cacheable True if the mapping is cacheable, false otherwise.
82	*/	82	*/
83	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)	83	void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
84	{	84	{
85	tlb_tag_access_reg_t tag;	85	tlb_tag_access_reg_t tag;
86	tlb_data_t data;	86	tlb_data_t data;
87	page_address_t pg;	87	page_address_t pg;
88	frame_address_t fr;	88	frame_address_t fr;
89		89
90	pg.address = page;	90	pg.address = page;
91	fr.address = frame;	91	fr.address = frame;
92		92
93	tag.value = ASID_KERNEL;	93	tag.value = ASID_KERNEL;
94	tag.vpn = pg.vpn;	94	tag.vpn = pg.vpn;
95		95
96	dtlb_tag_access_write(tag.value);	96	dtlb_tag_access_write(tag.value);
97		97
98	data.value = 0;	98	data.value = 0;
99	data.v = true;	99	data.v = true;
100	data.size = pagesize;	100	data.size = pagesize;
101	data.pfn = fr.pfn;	101	data.pfn = fr.pfn;
102	data.l = locked;	102	data.l = locked;
103	data.cp = cacheable;	103	data.cp = cacheable;
104	data.cv = cacheable;	104	data.cv = cacheable;
105	data.p = true;	105	data.p = true;
106	data.w = true;	106	data.w = true;
107	data.g = false;	107	data.g = false;
108		108
109	dtlb_data_in_write(data.value);	109	dtlb_data_in_write(data.value);
110	}	110	}
111		111
112	/** Copy PTE to TLB.	112	/** Copy PTE to TLB.
113	*	113	*
114	* @param t Page Table Entry to be copied.	114	* @param t Page Table Entry to be copied.
115	* @param ro If true, the entry will be created read-only, regardless of its w field.	115	* @param ro If true, the entry will be created read-only, regardless of its w field.
116	*/	116	*/
117	void dtlb_pte_copy(pte_t *t, bool ro)	117	void dtlb_pte_copy(pte_t *t, bool ro)
118	{	118	{
119	tlb_tag_access_reg_t tag;	119	tlb_tag_access_reg_t tag;
120	tlb_data_t data;	120	tlb_data_t data;
121	page_address_t pg;	121	page_address_t pg;
122	frame_address_t fr;	122	frame_address_t fr;
123		123
124	pg.address = t->page;	124	pg.address = t->page;
125	fr.address = t->frame;	125	fr.address = t->frame;
126		126
127	tag.value = 0;	127	tag.value = 0;
128	tag.context = t->as->asid;	128	tag.context = t->as->asid;
129	tag.vpn = pg.vpn;	129	tag.vpn = pg.vpn;
130		130
131	dtlb_tag_access_write(tag.value);	131	dtlb_tag_access_write(tag.value);
132		132
133	data.value = 0;	133	data.value = 0;
134	data.v = true;	134	data.v = true;
135	data.size = PAGESIZE_8K;	135	data.size = PAGESIZE_8K;
136	data.pfn = fr.pfn;	136	data.pfn = fr.pfn;
137	data.l = false;	137	data.l = false;
138	data.cp = t->c;	138	data.cp = t->c;
139	data.cv = t->c;	139	data.cv = t->c;
140	data.p = t->k; /* p like privileged */	140	data.p = t->k; /* p like privileged */
141	data.w = ro ? false : t->w;	141	data.w = ro ? false : t->w;
142	data.g = t->g;	142	data.g = t->g;
143		143
144	dtlb_data_in_write(data.value);	144	dtlb_data_in_write(data.value);
145	}	145	}
146		146
147	void itlb_pte_copy(pte_t *t)	147	void itlb_pte_copy(pte_t *t)
148	{	148	{
149	tlb_tag_access_reg_t tag;	149	tlb_tag_access_reg_t tag;
150	tlb_data_t data;	150	tlb_data_t data;
151	page_address_t pg;	151	page_address_t pg;
152	frame_address_t fr;	152	frame_address_t fr;
153		153
154	pg.address = t->page;	154	pg.address = t->page;
155	fr.address = t->frame;	155	fr.address = t->frame;
156		156
157	tag.value = 0;	157	tag.value = 0;
158	tag.context = t->as->asid;	158	tag.context = t->as->asid;
159	tag.vpn = pg.vpn;	159	tag.vpn = pg.vpn;
160		160
161	itlb_tag_access_write(tag.value);	161	itlb_tag_access_write(tag.value);
162		162
163	data.value = 0;	163	data.value = 0;
164	data.v = true;	164	data.v = true;
165	data.size = PAGESIZE_8K;	165	data.size = PAGESIZE_8K;
166	data.pfn = fr.pfn;	166	data.pfn = fr.pfn;
167	data.l = false;	167	data.l = false;
168	data.cp = t->c;	168	data.cp = t->c;
169	data.cv = t->c;	169	data.cv = t->c;
170	data.p = t->k; /* p like privileged */	170	data.p = t->k; /* p like privileged */
171	data.w = false;	171	data.w = false;
172	data.g = t->g;	172	data.g = t->g;
173		173
174	itlb_data_in_write(data.value);	174	itlb_data_in_write(data.value);
175	}	175	}
176		176
177	/** ITLB miss handler. */	177	/** ITLB miss handler. */
178	void fast_instruction_access_mmu_miss(int n, istate_t *istate)	178	void fast_instruction_access_mmu_miss(int n, istate_t *istate)
179	{	179	{
180	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);	180	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
181	pte_t *t;	181	pte_t *t;
182		182
183	page_table_lock(AS, true);	183	page_table_lock(AS, true);
184	t = page_mapping_find(AS, va);	184	t = page_mapping_find(AS, va);
185	if (t && PTE_EXECUTABLE(t)) {	185	if (t && PTE_EXECUTABLE(t)) {
186	/*	186	/*
187	* The mapping was found in the software page hash table.	187	* The mapping was found in the software page hash table.
188	* Insert it into ITLB.	188	* Insert it into ITLB.
189	*/	189	*/
190	t->a = true;	190	t->a = true;
191	itlb_pte_copy(t);	191	itlb_pte_copy(t);
192	page_table_unlock(AS, true);	192	page_table_unlock(AS, true);
193	} else {	193	} else {
194	/*	194	/*
195	* Forward the page fault to the address space page fault handler.	195	* Forward the page fault to the address space page fault handler.
196	*/	196	*/
197	page_table_unlock(AS, true);	197	page_table_unlock(AS, true);
198	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {	198	if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
199	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);	199	do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
200	}	200	}
201	}	201	}
202	}	202	}
203		203
204	/** DTLB miss handler.	204	/** DTLB miss handler.
205	*	205	*
206	* Note that some faults (e.g. kernel faults) were already resolved	206	* Note that some faults (e.g. kernel faults) were already resolved
207	* by the low-level, assembly language part of the fast_data_access_mmu_miss	207	* by the low-level, assembly language part of the fast_data_access_mmu_miss
208	* handler.	208	* handler.
209	*/	209	*/
210	void fast_data_access_mmu_miss(int n, istate_t *istate)	210	void fast_data_access_mmu_miss(int n, istate_t *istate)
211	{	211	{
212	tlb_tag_access_reg_t tag;	212	tlb_tag_access_reg_t tag;
213	uintptr_t va;	213	uintptr_t va;
214	pte_t *t;	214	pte_t *t;
215		215
216	tag.value = dtlb_tag_access_read();	216	tag.value = dtlb_tag_access_read();
217	va = tag.vpn << PAGE_WIDTH;	217	va = tag.vpn << PAGE_WIDTH;
218		218
219	if (tag.context == ASID_KERNEL) {	219	if (tag.context == ASID_KERNEL) {
220	if (!tag.vpn) {	220	if (!tag.vpn) {
221	/* NULL access in kernel */	221	/* NULL access in kernel */
222	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	222	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
223	}	223	}
224	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");	224	do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
225	}	225	}
226		226
227	page_table_lock(AS, true);	227	page_table_lock(AS, true);
228	t = page_mapping_find(AS, va);	228	t = page_mapping_find(AS, va);
229	if (t) {	229	if (t) {
230	/*	230	/*
231	* The mapping was found in the software page hash table.	231	* The mapping was found in the software page hash table.
232	* Insert it into DTLB.	232	* Insert it into DTLB.
233	*/	233	*/
234	t->a = true;	234	t->a = true;
235	dtlb_pte_copy(t, true);	235	dtlb_pte_copy(t, true);
236	page_table_unlock(AS, true);	236	page_table_unlock(AS, true);
237	} else {	237	} else {
238	/*	238	/*
239	* Forward the page fault to the address space page fault handler.	239	* Forward the page fault to the address space page fault handler.
240	*/	240	*/
241	page_table_unlock(AS, true);	241	page_table_unlock(AS, true);
242	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {	242	if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
243	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);	243	do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
244	}	244	}
245	}	245	}
246	}	246	}
247		247
248	/** DTLB protection fault handler. */	248	/** DTLB protection fault handler. */
249	void fast_data_access_protection(int n, istate_t *istate)	249	void fast_data_access_protection(int n, istate_t *istate)
250	{	250	{
251	tlb_tag_access_reg_t tag;	251	tlb_tag_access_reg_t tag;
252	uintptr_t va;	252	uintptr_t va;
253	pte_t *t;	253	pte_t *t;
254		254
255	tag.value = dtlb_tag_access_read();	255	tag.value = dtlb_tag_access_read();
256	va = tag.vpn << PAGE_WIDTH;	256	va = tag.vpn << PAGE_WIDTH;
257		257
258	page_table_lock(AS, true);	258	page_table_lock(AS, true);
259	t = page_mapping_find(AS, va);	259	t = page_mapping_find(AS, va);
260	if (t && PTE_WRITABLE(t)) {	260	if (t && PTE_WRITABLE(t)) {
261	/*	261	/*
262	* The mapping was found in the software page hash table and is writable.	262	* The mapping was found in the software page hash table and is writable.
263	* Demap the old mapping and insert an updated mapping into DTLB.	263	* Demap the old mapping and insert an updated mapping into DTLB.
264	*/	264	*/
265	t->a = true;	265	t->a = true;
266	t->d = true;	266	t->d = true;
267	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);	267	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
268	dtlb_pte_copy(t, false);	268	dtlb_pte_copy(t, false);
269	page_table_unlock(AS, true);	269	page_table_unlock(AS, true);
270	} else {	270	} else {
271	/*	271	/*
272	* Forward the page fault to the address space page fault handler.	272	* Forward the page fault to the address space page fault handler.
273	*/	273	*/
274	page_table_unlock(AS, true);	274	page_table_unlock(AS, true);
275	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {	275	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
276	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);	276	do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
277	}	277	}
278	}	278	}
279	}	279	}
280		280
281	/** Print contents of both TLBs. */	281	/** Print contents of both TLBs. */
282	void tlb_print(void)	282	void tlb_print(void)
283	{	283	{
284	int i;	284	int i;
285	tlb_data_t d;	285	tlb_data_t d;
286	tlb_tag_read_reg_t t;	286	tlb_tag_read_reg_t t;
287		287
288	printf("I-TLB contents:\n");	288	printf("I-TLB contents:\n");
289	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	289	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
290	d.value = itlb_data_access_read(i);	290	d.value = itlb_data_access_read(i);
291	t.value = itlb_tag_read_read(i);	291	t.value = itlb_tag_read_read(i);
292		292
293	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	293	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
294	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	294	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
295	}	295	}
296		296
297	printf("D-TLB contents:\n");	297	printf("D-TLB contents:\n");
298	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	298	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
299	d.value = dtlb_data_access_read(i);	299	d.value = dtlb_data_access_read(i);
300	t.value = dtlb_tag_read_read(i);	300	t.value = dtlb_tag_read_read(i);
301		301
302	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",	302	printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
303	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);	303	i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
304	}	304	}
305		305
306	}	306	}
307		307
308	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)	308	void do_fast_instruction_access_mmu_miss_fault(istate_t istate, const char str)
309	{	309	{
310	char *tpc_str = get_symtab_entry(istate->tpc);	-
311		-
312	fault_if_from_uspace(istate, "%s\n", str);	310	fault_if_from_uspace(istate, "%s\n", str);
313	printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);	311	dump_istate(istate);
314	panic("%s\n", str);	312	panic("%s\n", str);
315	}	313	}
316		314
317	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	315	void do_fast_data_access_mmu_miss_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
318	{	316	{
319	uintptr_t va;	317	uintptr_t va;
320	char *tpc_str = get_symtab_entry(istate->tpc);	-
321		318
322	va = tag.vpn << PAGE_WIDTH;	319	va = tag.vpn << PAGE_WIDTH;
323		320
324	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	321	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
-		322	dump_istate(istate);
325	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	323	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
326	printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);	-
327	panic("%s\n", str);	324	panic("%s\n", str);
328	}	325	}
329		326
330	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)	327	void do_fast_data_access_protection_fault(istate_t istate, tlb_tag_access_reg_t tag, const char str)
331	{	328	{
332	uintptr_t va;	329	uintptr_t va;
333	char *tpc_str = get_symtab_entry(istate->tpc);	-
334		330
335	va = tag.vpn << PAGE_WIDTH;	331	va = tag.vpn << PAGE_WIDTH;
336		332
337	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);	333	fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
338	printf("Faulting page: %p, ASID=%d\n", va, tag.context);	334	printf("Faulting page: %p, ASID=%d\n", va, tag.context);
339	printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);	335	dump_istate(istate);
340	panic("%s\n", str);	336	panic("%s\n", str);
341	}	337	}
342		338
343	/** Invalidate all unlocked ITLB and DTLB entries. */	339	/** Invalidate all unlocked ITLB and DTLB entries. */
344	void tlb_invalidate_all(void)	340	void tlb_invalidate_all(void)
345	{	341	{
346	int i;	342	int i;
347	tlb_data_t d;	343	tlb_data_t d;
348	tlb_tag_read_reg_t t;	344	tlb_tag_read_reg_t t;
349		345
350	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {	346	for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
351	d.value = itlb_data_access_read(i);	347	d.value = itlb_data_access_read(i);
352	if (!d.l) {	348	if (!d.l) {
353	t.value = itlb_tag_read_read(i);	349	t.value = itlb_tag_read_read(i);
354	d.v = false;	350	d.v = false;
355	itlb_tag_access_write(t.value);	351	itlb_tag_access_write(t.value);
356	itlb_data_access_write(i, d.value);	352	itlb_data_access_write(i, d.value);
357	}	353	}
358	}	354	}
359		355
360	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {	356	for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
361	d.value = dtlb_data_access_read(i);	357	d.value = dtlb_data_access_read(i);
362	if (!d.l) {	358	if (!d.l) {
363	t.value = dtlb_tag_read_read(i);	359	t.value = dtlb_tag_read_read(i);
364	d.v = false;	360	d.v = false;
365	dtlb_tag_access_write(t.value);	361	dtlb_tag_access_write(t.value);
366	dtlb_data_access_write(i, d.value);	362	dtlb_data_access_write(i, d.value);
367	}	363	}
368	}	364	}
369		365
370	}	366	}
371		367
372	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).	368	/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
373	*	369	*
374	* @param asid Address Space ID.	370	* @param asid Address Space ID.
375	*/	371	*/
376	void tlb_invalidate_asid(asid_t asid)	372	void tlb_invalidate_asid(asid_t asid)
377	{	373	{
378	tlb_context_reg_t pc_save, ctx;	374	tlb_context_reg_t pc_save, ctx;
379		375
380	/* switch to nucleus because we are mapped by the primary context */	376	/* switch to nucleus because we are mapped by the primary context */
381	nucleus_enter();	377	nucleus_enter();
382		378
383	ctx.v = pc_save.v = mmu_primary_context_read();	379	ctx.v = pc_save.v = mmu_primary_context_read();
384	ctx.context = asid;	380	ctx.context = asid;
385	mmu_primary_context_write(ctx.v);	381	mmu_primary_context_write(ctx.v);
386		382
387	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	383	itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
388	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);	384	dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
389		385
390	mmu_primary_context_write(pc_save.v);	386	mmu_primary_context_write(pc_save.v);
391		387
392	nucleus_leave();	388	nucleus_leave();
393	}	389	}
394		390
395	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.	391	/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
396	*	392	*
397	* @param asid Address Space ID.	393	* @param asid Address Space ID.
398	* @param page First page which to sweep out from ITLB and DTLB.	394	* @param page First page which to sweep out from ITLB and DTLB.
399	* @param cnt Number of ITLB and DTLB entries to invalidate.	395	* @param cnt Number of ITLB and DTLB entries to invalidate.
400	*/	396	*/
401	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	397	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
402	{	398	{
403	int i;	399	int i;
404	tlb_context_reg_t pc_save, ctx;	400	tlb_context_reg_t pc_save, ctx;
405		401
406	/* switch to nucleus because we are mapped by the primary context */	402	/* switch to nucleus because we are mapped by the primary context */
407	nucleus_enter();	403	nucleus_enter();
408		404
409	ctx.v = pc_save.v = mmu_primary_context_read();	405	ctx.v = pc_save.v = mmu_primary_context_read();
410	ctx.context = asid;	406	ctx.context = asid;
411	mmu_primary_context_write(ctx.v);	407	mmu_primary_context_write(ctx.v);
412		408
413	for (i = 0; i < cnt; i++) {	409	for (i = 0; i < cnt; i++) {
414	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	410	itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
415	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);	411	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
416	}	412	}
417		413
418	mmu_primary_context_write(pc_save.v);	414	mmu_primary_context_write(pc_save.v);
419		415
420	nucleus_leave();	416	nucleus_leave();
421	}	417	}
422		418
423	/** @}	419	/** @}
424	*/	420	*/
425		421

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(root)/trunk/kernel/arch/sparc64/src/mm/tlb.c – Rev 1870 → 1880