WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/as.c


/*
 * Copyright (C) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/as.h>
#include <arch/mm/tlb.h>
#include <genarch/mm/as_ht.h>
#include <genarch/mm/asid_fifo.h>
#include <debug.h>
#include <config.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#include <arch/memstr.h>
#include <synch/mutex.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <bitops.h>
#include <macros.h>
#endif /* CONFIG_TSB */
 
/** Architecture dependent address space init. */
void as_arch_init(void)
{
    if (config.cpu_active == 1) {
        as_operations = &as_ht_operations;
        asid_fifo_init();
    }
}
 
int as_constructor_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
        sizeof(tsb_entry_t)) >> FRAME_WIDTH);
    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
 
    if (!tsb)
        return -1;
 
    as->arch.itsb = (tsb_entry_t *) tsb;
    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
        sizeof(tsb_entry_t));
    memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT)
        * sizeof(tsb_entry_t), 0);
#endif
    return 0;
}
 
int as_destructor_arch(as_t *as)
{
#ifdef CONFIG_TSB
    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
        sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    frame_free(KA2PA((uintptr_t) as->arch.itsb));
    return cnt;
#else
    return 0;
#endif
}
 
int as_create_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    ipl_t ipl;
 
    ipl = interrupts_disable();
    mutex_lock_active(&as->lock);   /* completely unnecessary, but polite */
    tsb_invalidate(as, 0, (count_t) -1);
    mutex_unlock(&as->lock);
    interrupts_restore(ipl);
#endif
    return 0;
}
 
/** Perform sparc64-specific tasks when an address space becomes active on the
 * processor.
 *
 * Install ASID and map TSBs.
 *
 * @param as Address space.
 */
void as_install_arch(as_t *as)
{
    tlb_context_reg_t ctx;
   
    /*
     * Note that we don't lock the address space.
     * That's correct - we can afford it here
     * because we only read members that are
     * currently read-only.
     */
   
    /*
     * Write ASID to secondary context register.
     * The primary context register has to be set
     * from TL>0 so it will be filled from the
     * secondary context register from the TL=1
     * code just before switch to userspace.
     */
    ctx.v = 0;
    ctx.context = as->asid;
    mmu_secondary_context_write(ctx.v);
 
#ifdef CONFIG_TSB   
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to map both TSBs explicitly.
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
        dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
    }
       
    /*
     * Setup TSB Base registers.
     */
    tsb_base_reg_t tsb_base;
       
    tsb_base.value = 0;
    tsb_base.size = TSB_SIZE;
    tsb_base.split = 0;
 
    tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;
    itsb_base_write(tsb_base.value);
    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;
    dtsb_base_write(tsb_base.value);
#endif
}
 
/** Perform sparc64-specific tasks when an address space is removed from the
 * processor.
 *
 * Demap TSBs.
 *
 * @param as Address space.
 */
void as_deinstall_arch(as_t *as)
{
 
    /*
     * Note that we don't lock the address space.
     * That's correct - we can afford it here
     * because we only read members that are
     * currently read-only.
     */
 
#ifdef CONFIG_TSB
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to demap the entry installed by as_install_arch().
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
    }
#endif
}
 
/** @}
 */
 

Rev 2015	Rev 2048
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/as.h>	35	#include <arch/mm/as.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <genarch/mm/as_ht.h>	37	#include <genarch/mm/as_ht.h>
38	#include <genarch/mm/asid_fifo.h>	38	#include <genarch/mm/asid_fifo.h>
39	#include <debug.h>	39	#include <debug.h>
40	#include <config.h>	40	#include <config.h>
41		41
42	#ifdef CONFIG_TSB	42	#ifdef CONFIG_TSB
43	#include <arch/mm/tsb.h>	43	#include <arch/mm/tsb.h>
44	#include <arch/memstr.h>	44	#include <arch/memstr.h>
45	#include <synch/mutex.h>	45	#include <synch/mutex.h>
46	#include <arch/asm.h>	46	#include <arch/asm.h>
47	#include <mm/frame.h>	47	#include <mm/frame.h>
48	#include <bitops.h>	48	#include <bitops.h>
49	#include <macros.h>	49	#include <macros.h>
50	#endif /* CONFIG_TSB */	50	#endif /* CONFIG_TSB */
51		51
52	/** Architecture dependent address space init. */	52	/** Architecture dependent address space init. */
53	void as_arch_init(void)	53	void as_arch_init(void)
54	{	54	{
55	if (config.cpu_active == 1) {	55	if (config.cpu_active == 1) {
56	as_operations = &as_ht_operations;	56	as_operations = &as_ht_operations;
57	asid_fifo_init();	57	asid_fifo_init();
58	}	58	}
59	}	59	}
60		60
61	int as_constructor_arch(as_t *as, int flags)	61	int as_constructor_arch(as_t *as, int flags)
62	{	62	{
63	#ifdef CONFIG_TSB	63	#ifdef CONFIG_TSB
64	int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH);	64	int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-		65	sizeof(tsb_entry_t)) >> FRAME_WIDTH);
65	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);	66	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);
66		67
67	if (!tsb)	68	if (!tsb)
68	return -1;	69	return -1;
69		70
70	as->arch.itsb = (tsb_entry_t *) tsb;	71	as->arch.itsb = (tsb_entry_t *) tsb;
71	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT sizeof(tsb_entry_t));	72	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT
-		73	sizeof(tsb_entry_t));
72	memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0);	74	memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT)
-		75	* sizeof(tsb_entry_t), 0);
73	#endif	76	#endif
74	return 0;	77	return 0;
75	}	78	}
76		79
77	int as_destructor_arch(as_t *as)	80	int as_destructor_arch(as_t *as)
78	{	81	{
79	#ifdef CONFIG_TSB	82	#ifdef CONFIG_TSB
80	count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH;	83	count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-		84	sizeof(tsb_entry_t)) >> FRAME_WIDTH;
81	frame_free(KA2PA((uintptr_t) as->arch.itsb));	85	frame_free(KA2PA((uintptr_t) as->arch.itsb));
82	return cnt;	86	return cnt;
83	#else	87	#else
84	return 0;	88	return 0;
85	#endif	89	#endif
86	}	90	}
87		91
88	int as_create_arch(as_t *as, int flags)	92	int as_create_arch(as_t *as, int flags)
89	{	93	{
90	#ifdef CONFIG_TSB	94	#ifdef CONFIG_TSB
91	ipl_t ipl;	95	ipl_t ipl;
92		96
93	ipl = interrupts_disable();	97	ipl = interrupts_disable();
94	mutex_lock_active(&as->lock); /* completely unnecessary, but polite */	98	mutex_lock_active(&as->lock); /* completely unnecessary, but polite */
95	tsb_invalidate(as, 0, (count_t) -1);	99	tsb_invalidate(as, 0, (count_t) -1);
96	mutex_unlock(&as->lock);	100	mutex_unlock(&as->lock);
97	interrupts_restore(ipl);	101	interrupts_restore(ipl);
98	#endif	102	#endif
99	return 0;	103	return 0;
100	}	104	}
101		105
102	/** Perform sparc64-specific tasks when an address space becomes active on the processor.	106	/** Perform sparc64-specific tasks when an address space becomes active on the
-		107	* processor.
103	*	108	*
104	* Install ASID and map TSBs.	109	* Install ASID and map TSBs.
105	*	110	*
106	* @param as Address space.	111	* @param as Address space.
107	*/	112	*/
108	void as_install_arch(as_t *as)	113	void as_install_arch(as_t *as)
109	{	114	{
110	tlb_context_reg_t ctx;	115	tlb_context_reg_t ctx;
111		116
112	/*	117	/*
113	* Note that we don't lock the address space.	118	* Note that we don't lock the address space.
114	* That's correct - we can afford it here	119	* That's correct - we can afford it here
115	* because we only read members that are	120	* because we only read members that are
116	* currently read-only.	121	* currently read-only.
117	*/	122	*/
118		123
119	/*	124	/*
120	* Write ASID to secondary context register.	125	* Write ASID to secondary context register.
121	* The primary context register has to be set	126	* The primary context register has to be set
122	* from TL>0 so it will be filled from the	127	* from TL>0 so it will be filled from the
123	* secondary context register from the TL=1	128	* secondary context register from the TL=1
124	* code just before switch to userspace.	129	* code just before switch to userspace.
125	*/	130	*/
126	ctx.v = 0;	131	ctx.v = 0;
127	ctx.context = as->asid;	132	ctx.context = as->asid;
128	mmu_secondary_context_write(ctx.v);	133	mmu_secondary_context_write(ctx.v);
129		134
130	#ifdef CONFIG_TSB	135	#ifdef CONFIG_TSB
131	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	136	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
132		137
133	ASSERT(as->arch.itsb && as->arch.dtsb);	138	ASSERT(as->arch.itsb && as->arch.dtsb);
134		139
135	uintptr_t tsb = (uintptr_t) as->arch.itsb;	140	uintptr_t tsb = (uintptr_t) as->arch.itsb;
136		141
137	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	142	if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
138	/*	143	/*
139	* TSBs were allocated from memory not covered	144	* TSBs were allocated from memory not covered
140	* by the locked 4M kernel DTLB entry. We need	145	* by the locked 4M kernel DTLB entry. We need
141	* to map both TSBs explicitly.	146	* to map both TSBs explicitly.
142	*/	147	*/
143	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	148	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
144	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);	149	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
145	}	150	}
146		151
147	/*	152	/*
148	* Setup TSB Base registers.	153	* Setup TSB Base registers.
149	*/	154	*/
150	tsb_base_reg_t tsb_base;	155	tsb_base_reg_t tsb_base;
151		156
152	tsb_base.value = 0;	157	tsb_base.value = 0;
153	tsb_base.size = TSB_SIZE;	158	tsb_base.size = TSB_SIZE;
154	tsb_base.split = 0;	159	tsb_base.split = 0;
155		160
156	tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;	161	tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;
157	itsb_base_write(tsb_base.value);	162	itsb_base_write(tsb_base.value);
158	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;	163	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;
159	dtsb_base_write(tsb_base.value);	164	dtsb_base_write(tsb_base.value);
160	#endif	165	#endif
161	}	166	}
162		167
163	/** Perform sparc64-specific tasks when an address space is removed from the processor.	168	/** Perform sparc64-specific tasks when an address space is removed from the
-		169	* processor.
164	*	170	*
165	* Demap TSBs.	171	* Demap TSBs.
166	*	172	*
167	* @param as Address space.	173	* @param as Address space.
168	*/	174	*/
169	void as_deinstall_arch(as_t *as)	175	void as_deinstall_arch(as_t *as)
170	{	176	{
171		177
172	/*	178	/*
173	* Note that we don't lock the address space.	179	* Note that we don't lock the address space.
174	* That's correct - we can afford it here	180	* That's correct - we can afford it here
175	* because we only read members that are	181	* because we only read members that are
176	* currently read-only.	182	* currently read-only.
177	*/	183	*/
178		184
179	#ifdef CONFIG_TSB	185	#ifdef CONFIG_TSB
180	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	186	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
181		187
182	ASSERT(as->arch.itsb && as->arch.dtsb);	188	ASSERT(as->arch.itsb && as->arch.dtsb);
183		189
184	uintptr_t tsb = (uintptr_t) as->arch.itsb;	190	uintptr_t tsb = (uintptr_t) as->arch.itsb;
185		191
186	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	192	if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
187	/*	193	/*
188	* TSBs were allocated from memory not covered	194	* TSBs were allocated from memory not covered
189	* by the locked 4M kernel DTLB entry. We need	195	* by the locked 4M kernel DTLB entry. We need
190	* to demap the entry installed by as_install_arch().	196	* to demap the entry installed by as_install_arch().
191	*/	197	*/
192	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	198	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
193	}	199	}
194	#endif	200	#endif
195	}	201	}
196		202
197	/** @}	203	/** @}
198	*/	204	*/
199		205

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(root)/trunk/kernel/arch/sparc64/src/mm/as.c – Rev 2015 → 2048