WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/as.c


/*
 * Copyright (C) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/as.h>
#include <arch/mm/tlb.h>
#include <genarch/mm/as_ht.h>
#include <genarch/mm/asid_fifo.h>
#include <debug.h>
#include <config.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#include <arch/memstr.h>
#include <synch/mutex.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <bitops.h>
#include <macros.h>
#endif /* CONFIG_TSB */
 
#ifdef CONFIG_VIRT_IDX_DCACHE
#include <arch/mm/cache.h>
#endif /* CONFIG_VIRT_IDX_DCACHE */
 
/** Architecture dependent address space init. */
void as_arch_init(void)
{
    if (config.cpu_active == 1) {
        as_operations = &as_ht_operations;
        asid_fifo_init();
    }
}
 
int as_constructor_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH);
    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
 
    if (!tsb)
        return -1;
 
    as->arch.itsb = (tsb_entry_t *) tsb;
    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * sizeof(tsb_entry_t));
    memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0);
#endif
    return 0;
}
 
int as_destructor_arch(as_t *as)
{
#ifdef CONFIG_TSB
    count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH;
    frame_free(KA2PA((uintptr_t) as->arch.itsb));
    return cnt;
#else
    return 0;
#endif
}
 
int as_create_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    ipl_t ipl;
 
    ipl = interrupts_disable();
    mutex_lock_active(&as->lock);   /* completely unnecessary, but polite */
    tsb_invalidate(as, 0, (count_t) -1);
    mutex_unlock(&as->lock);
    interrupts_restore(ipl);
#endif
    return 0;
}
 
/** Perform sparc64-specific tasks when an address space becomes active on the processor.
 *
 * Install ASID and map TSBs.
 *
 * @param as Address space.
 */
void as_install_arch(as_t *as)
{
    tlb_context_reg_t ctx;
   
    /*
     * Note that we don't lock the address space.
     * That's correct - we can afford it here
     * because we only read members that are
     * currently read-only.
     */
   
    /*
     * Write ASID to secondary context register.
     * The primary context register has to be set
     * from TL>0 so it will be filled from the
     * secondary context register from the TL=1
     * code just before switch to userspace.
     */
    ctx.v = 0;
    ctx.context = as->asid;
    mmu_secondary_context_write(ctx.v);
 
#ifdef CONFIG_TSB   
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to map both TSBs explicitly.
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
        dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
    }
       
    /*
     * Setup TSB Base registers.
     */
    tsb_base_reg_t tsb_base;
       
    tsb_base.value = 0;
    tsb_base.size = TSB_SIZE;
    tsb_base.split = 0;
 
    tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;
    itsb_base_write(tsb_base.value);
    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;
    dtsb_base_write(tsb_base.value);
#endif
#ifdef CONFIG_VIRT_IDX_DCACHE
    if (as->dcache_flush_on_install) {
        /*
         * Some mappings in this address space are illegal address
         * aliases. Upon their creation, the dcache_flush_on_install
         * flag was set.
         *
         * We are now obliged to flush the D-cache in order to guarantee
         * that there will be at most one cache line for each address
         * alias.
         *
         * This flush performs a cleanup after another address space in
         * which the alias might have existed.
         */
        dcache_flush();
    }
#endif /* CONFIG_VIRT_IDX_DCACHE */
}
 
/** Perform sparc64-specific tasks when an address space is removed from the processor.
 *
 * Demap TSBs.
 *
 * @param as Address space.
 */
void as_deinstall_arch(as_t *as)
{
 
    /*
     * Note that we don't lock the address space.
     * That's correct - we can afford it here
     * because we only read members that are
     * currently read-only.
     */
 
#ifdef CONFIG_TSB
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to demap the entry installed by as_install_arch().
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
    }
#endif
#ifdef CONFIG_VIRT_IDX_DCACHE
    if (as->dcache_flush_on_deinstall) {
        /*
         * Some mappings in this address space are illegal address
         * aliases. Upon their creation, the dcache_flush_on_deinstall
         * flag was set.
         *
         * We are now obliged to flush the D-cache in order to guarantee
         * that there will be at most one cache line for each address
         * alias.
         *
         * This flush performs a cleanup after this address space. It is
         * necessary because other address spaces that contain the same
         * alias are not necessarily aware of the need to carry out the
         * cache flush. The only address spaces that are aware of it are
         * those that created the illegal alias.
         */
        dcache_flush();
    }
#endif /* CONFIG_VIRT_IDX_DCACHE */
}
 
/** @}
 */
 

Rev 2009	Rev 2010
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/as.h>	35	#include <arch/mm/as.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <genarch/mm/as_ht.h>	37	#include <genarch/mm/as_ht.h>
38	#include <genarch/mm/asid_fifo.h>	38	#include <genarch/mm/asid_fifo.h>
39	#include <debug.h>	39	#include <debug.h>
40	#include <config.h>	40	#include <config.h>
41		41
42	#ifdef CONFIG_TSB	42	#ifdef CONFIG_TSB
43	#include <arch/mm/tsb.h>	43	#include <arch/mm/tsb.h>
44	#include <arch/memstr.h>	44	#include <arch/memstr.h>
45	#include <synch/mutex.h>	45	#include <synch/mutex.h>
46	#include <arch/asm.h>	46	#include <arch/asm.h>
47	#include <mm/frame.h>	47	#include <mm/frame.h>
48	#include <bitops.h>	48	#include <bitops.h>
49	#include <macros.h>	49	#include <macros.h>
50	#endif /* CONFIG_TSB */	50	#endif /* CONFIG_TSB */
51		51
52	#ifdef CONFIG_VIRT_IDX_DCACHE	52	#ifdef CONFIG_VIRT_IDX_DCACHE
53	#include <arch/mm/cache.h>	53	#include <arch/mm/cache.h>
54	#endif /* CONFIG_VIRT_IDX_DCACHE */	54	#endif /* CONFIG_VIRT_IDX_DCACHE */
55		55
56	/** Architecture dependent address space init. */	56	/** Architecture dependent address space init. */
57	void as_arch_init(void)	57	void as_arch_init(void)
58	{	58	{
59	if (config.cpu_active == 1) {	59	if (config.cpu_active == 1) {
60	as_operations = &as_ht_operations;	60	as_operations = &as_ht_operations;
61	asid_fifo_init();	61	asid_fifo_init();
62	}	62	}
63	}	63	}
64		64
65	int as_constructor_arch(as_t *as, int flags)	65	int as_constructor_arch(as_t *as, int flags)
66	{	66	{
67	#ifdef CONFIG_TSB	67	#ifdef CONFIG_TSB
68	int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH);	68	int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH);
69	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);	69	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);
70		70
71	if (!tsb)	71	if (!tsb)
72	return -1;	72	return -1;
73		73
74	as->arch.itsb = (tsb_entry_t *) tsb;	74	as->arch.itsb = (tsb_entry_t *) tsb;
75	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT sizeof(tsb_entry_t));	75	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT sizeof(tsb_entry_t));
76	memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0);	76	memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0);
77	#endif	77	#endif
78	return 0;	78	return 0;
79	}	79	}
80		80
81	int as_destructor_arch(as_t *as)	81	int as_destructor_arch(as_t *as)
82	{	82	{
83	#ifdef CONFIG_TSB	83	#ifdef CONFIG_TSB
84	count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH;	84	count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH;
85	frame_free(KA2PA((uintptr_t) as->arch.itsb));	85	frame_free(KA2PA((uintptr_t) as->arch.itsb));
86	return cnt;	86	return cnt;
87	#else	87	#else
88	return 0;	88	return 0;
89	#endif	89	#endif
90	}	90	}
91		91
92	int as_create_arch(as_t *as, int flags)	92	int as_create_arch(as_t *as, int flags)
93	{	93	{
94	#ifdef CONFIG_TSB	94	#ifdef CONFIG_TSB
95	ipl_t ipl;	95	ipl_t ipl;
96		96
97	ipl = interrupts_disable();	97	ipl = interrupts_disable();
98	mutex_lock_active(&as->lock); /* completely unnecessary, but polite */	98	mutex_lock_active(&as->lock); /* completely unnecessary, but polite */
99	tsb_invalidate(as, 0, (count_t) -1);	99	tsb_invalidate(as, 0, (count_t) -1);
100	mutex_unlock(&as->lock);	100	mutex_unlock(&as->lock);
101	interrupts_restore(ipl);	101	interrupts_restore(ipl);
102	#endif	102	#endif
103	return 0;	103	return 0;
104	}	104	}
105		105
106	/** Perform sparc64-specific tasks when an address space becomes active on the processor.	106	/** Perform sparc64-specific tasks when an address space becomes active on the processor.
107	*	107	*
108	* Install ASID and map TSBs.	108	* Install ASID and map TSBs.
109	*	109	*
110	* @param as Address space.	110	* @param as Address space.
111	*/	111	*/
112	void as_install_arch(as_t *as)	112	void as_install_arch(as_t *as)
113	{	113	{
114	tlb_context_reg_t ctx;	114	tlb_context_reg_t ctx;
115		115
116	/*	116	/*
117	* Note that we don't lock the address space.	117	* Note that we don't lock the address space.
118	* That's correct - we can afford it here	118	* That's correct - we can afford it here
119	* because we only read members that are	119	* because we only read members that are
120	* currently read-only.	120	* currently read-only.
121	*/	121	*/
122		122
123	/*	123	/*
124	* Write ASID to secondary context register.	124	* Write ASID to secondary context register.
125	* The primary context register has to be set	125	* The primary context register has to be set
126	* from TL>0 so it will be filled from the	126	* from TL>0 so it will be filled from the
127	* secondary context register from the TL=1	127	* secondary context register from the TL=1
128	* code just before switch to userspace.	128	* code just before switch to userspace.
129	*/	129	*/
130	ctx.v = 0;	130	ctx.v = 0;
131	ctx.context = as->asid;	131	ctx.context = as->asid;
132	mmu_secondary_context_write(ctx.v);	132	mmu_secondary_context_write(ctx.v);
133		133
134	#ifdef CONFIG_TSB	134	#ifdef CONFIG_TSB
135	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	135	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
136		136
137	ASSERT(as->arch.itsb && as->arch.dtsb);	137	ASSERT(as->arch.itsb && as->arch.dtsb);
138		138
139	uintptr_t tsb = (uintptr_t) as->arch.itsb;	139	uintptr_t tsb = (uintptr_t) as->arch.itsb;
140		140
141	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	141	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
142	/*	142	/*
143	* TSBs were allocated from memory not covered	143	* TSBs were allocated from memory not covered
144	* by the locked 4M kernel DTLB entry. We need	144	* by the locked 4M kernel DTLB entry. We need
145	* to map both TSBs explicitly.	145	* to map both TSBs explicitly.
146	*/	146	*/
147	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	147	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
148	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);	148	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
149	}	149	}
150		150
151	/*	151	/*
152	* Setup TSB Base registers.	152	* Setup TSB Base registers.
153	*/	153	*/
154	tsb_base_reg_t tsb_base;	154	tsb_base_reg_t tsb_base;
155		155
156	tsb_base.value = 0;	156	tsb_base.value = 0;
157	tsb_base.size = TSB_SIZE;	157	tsb_base.size = TSB_SIZE;
158	tsb_base.split = 0;	158	tsb_base.split = 0;
159		159
160	tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;	160	tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;
161	itsb_base_write(tsb_base.value);	161	itsb_base_write(tsb_base.value);
162	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;	162	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;
163	dtsb_base_write(tsb_base.value);	163	dtsb_base_write(tsb_base.value);
164	#endif	164	#endif
165	#ifdef CONFIG_VIRT_IDX_DCACHE	165	#ifdef CONFIG_VIRT_IDX_DCACHE
166	if (as->dcache_flush_on_install) {	166	if (as->dcache_flush_on_install) {
167	/*	167	/*
168	* Some mappings in this address space are illegal address	168	* Some mappings in this address space are illegal address
169	* aliases. Upon their creation, the flush_dcache_on_install	169	* aliases. Upon their creation, the dcache_flush_on_install
170	* flag was set.	170	* flag was set.
171	*	171	*
172	* We are now obliged to flush the D-cache in order to guarantee	172	* We are now obliged to flush the D-cache in order to guarantee
173	* that there will be at most one cache line for each address	173	* that there will be at most one cache line for each address
174	* alias.	174	* alias.
175	*	175	*
176	* This flush performs a cleanup after another address space in	176	* This flush performs a cleanup after another address space in
177	* which the alias might have existed.	177	* which the alias might have existed.
178	*/	178	*/
179	dcache_flush();	179	dcache_flush();
180	}	180	}
181	#endif /* CONFIG_VIRT_IDX_DCACHE */	181	#endif /* CONFIG_VIRT_IDX_DCACHE */
182	}	182	}
183		183
184	/** Perform sparc64-specific tasks when an address space is removed from the processor.	184	/** Perform sparc64-specific tasks when an address space is removed from the processor.
185	*	185	*
186	* Demap TSBs.	186	* Demap TSBs.
187	*	187	*
188	* @param as Address space.	188	* @param as Address space.
189	*/	189	*/
190	void as_deinstall_arch(as_t *as)	190	void as_deinstall_arch(as_t *as)
191	{	191	{
192		192
193	/*	193	/*
194	* Note that we don't lock the address space.	194	* Note that we don't lock the address space.
195	* That's correct - we can afford it here	195	* That's correct - we can afford it here
196	* because we only read members that are	196	* because we only read members that are
197	* currently read-only.	197	* currently read-only.
198	*/	198	*/
199		199
200	#ifdef CONFIG_TSB	200	#ifdef CONFIG_TSB
201	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	201	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
202		202
203	ASSERT(as->arch.itsb && as->arch.dtsb);	203	ASSERT(as->arch.itsb && as->arch.dtsb);
204		204
205	uintptr_t tsb = (uintptr_t) as->arch.itsb;	205	uintptr_t tsb = (uintptr_t) as->arch.itsb;
206		206
207	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	207	if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
208	/*	208	/*
209	* TSBs were allocated from memory not covered	209	* TSBs were allocated from memory not covered
210	* by the locked 4M kernel DTLB entry. We need	210	* by the locked 4M kernel DTLB entry. We need
211	* to demap the entry installed by as_install_arch().	211	* to demap the entry installed by as_install_arch().
212	*/	212	*/
213	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	213	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
214	}	214	}
215	#endif	215	#endif
216	#ifdef CONFIG_VIRT_IDX_DCACHE	216	#ifdef CONFIG_VIRT_IDX_DCACHE
217	if (as->dcache_flush_on_deinstall) {	217	if (as->dcache_flush_on_deinstall) {
218	/*	218	/*
219	* Some mappings in this address space are illegal address	219	* Some mappings in this address space are illegal address
220	* aliases. Upon their creation, the flush_dcache_on_deinstall	220	* aliases. Upon their creation, the dcache_flush_on_deinstall
221	* flag was set.	221	* flag was set.
222	*	222	*
223	* We are now obliged to flush the D-cache in order to guarantee	223	* We are now obliged to flush the D-cache in order to guarantee
224	* that there will be at most one cache line for each address	224	* that there will be at most one cache line for each address
225	* alias.	225	* alias.
226	*	226	*
227	* This flush performs a cleanup after this address space. It is	227	* This flush performs a cleanup after this address space. It is
228	* necessary because other address spaces that contain the same	228	* necessary because other address spaces that contain the same
229	* alias are not necessarily aware of the need to carry out the	229	* alias are not necessarily aware of the need to carry out the
230	* cache flush. The only address spaces that are aware of it are	230	* cache flush. The only address spaces that are aware of it are
231	* those that created the illegal alias.	231	* those that created the illegal alias.
232	*/	232	*/
233	dcache_flush();	233	dcache_flush();
234	}	234	}
235	#endif /* CONFIG_VIRT_IDX_DCACHE */	235	#endif /* CONFIG_VIRT_IDX_DCACHE */
236	}	236	}
237		237
238	/** @}	238	/** @}
239	*/	239	*/
240		240

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(root)/trunk/kernel/arch/sparc64/src/mm/as.c – Rev 2009 → 2010