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1 | /* |
1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
2 | * Copyright (c) 2006 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** |
32 | /** |
33 | * @file |
33 | * @file |
34 | * @brief PCI driver. |
34 | * @brief PCI driver. |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #include <arch/drivers/pci.h> |
37 | #include <arch/drivers/pci.h> |
38 | #include <genarch/ofw/ofw_tree.h> |
38 | #include <genarch/ofw/ofw_tree.h> |
39 | #include <arch/trap/interrupt.h> |
39 | #include <arch/trap/interrupt.h> |
40 | #include <arch/mm/page.h> |
40 | #include <arch/mm/page.h> |
41 | #include <mm/slab.h> |
41 | #include <mm/slab.h> |
42 | #include <arch/types.h> |
42 | #include <arch/types.h> |
43 | #include <typedefs.h> |
43 | #include <typedefs.h> |
44 | #include <debug.h> |
44 | #include <debug.h> |
45 | #include <print.h> |
45 | #include <print.h> |
46 | #include <func.h> |
46 | #include <func.h> |
47 | #include <arch/asm.h> |
47 | #include <arch/asm.h> |
48 | 48 | ||
49 | #define PCI_SABRE_REGS_REG 0 |
49 | #define PCI_SABRE_REGS_REG 0 |
50 | 50 | ||
51 | #define PCI_SABRE_IMAP_BASE 0x200 |
51 | #define PCI_SABRE_IMAP_BASE 0x200 |
52 | #define PCI_SABRE_ICLR_BASE 0x300 |
52 | #define PCI_SABRE_ICLR_BASE 0x300 |
53 | 53 | ||
54 | #define PCI_PSYCHO_REGS_REG 2 |
54 | #define PCI_PSYCHO_REGS_REG 2 |
55 | 55 | ||
56 | #define PCI_PSYCHO_IMAP_BASE 0x200 |
56 | #define PCI_PSYCHO_IMAP_BASE 0x200 |
57 | #define PCI_PSYCHO_ICLR_BASE 0x300 |
57 | #define PCI_PSYCHO_ICLR_BASE 0x300 |
58 | 58 | ||
59 | static pci_t *pci_sabre_init(ofw_tree_node_t *node); |
59 | static pci_t *pci_sabre_init(ofw_tree_node_t *node); |
60 | static void pci_sabre_enable_interrupt(pci_t *pci, int inr); |
60 | static void pci_sabre_enable_interrupt(pci_t *pci, int inr); |
61 | static void pci_sabre_clear_interrupt(pci_t *pci, int inr); |
61 | static void pci_sabre_clear_interrupt(pci_t *pci, int inr); |
62 | 62 | ||
63 | static pci_t *pci_psycho_init(ofw_tree_node_t *node); |
63 | static pci_t *pci_psycho_init(ofw_tree_node_t *node); |
64 | static void pci_psycho_enable_interrupt(pci_t *pci, int inr); |
64 | static void pci_psycho_enable_interrupt(pci_t *pci, int inr); |
65 | static void pci_psycho_clear_interrupt(pci_t *pci, int inr); |
65 | static void pci_psycho_clear_interrupt(pci_t *pci, int inr); |
66 | 66 | ||
67 | /** PCI operations for Sabre model. */ |
67 | /** PCI operations for Sabre model. */ |
68 | static pci_operations_t pci_sabre_ops = { |
68 | static pci_operations_t pci_sabre_ops = { |
69 | .enable_interrupt = pci_sabre_enable_interrupt, |
69 | .enable_interrupt = pci_sabre_enable_interrupt, |
70 | .clear_interrupt = pci_sabre_clear_interrupt |
70 | .clear_interrupt = pci_sabre_clear_interrupt |
71 | }; |
71 | }; |
72 | /** PCI operations for Psycho model. */ |
72 | /** PCI operations for Psycho model. */ |
73 | static pci_operations_t pci_psycho_ops = { |
73 | static pci_operations_t pci_psycho_ops = { |
74 | .enable_interrupt = pci_psycho_enable_interrupt, |
74 | .enable_interrupt = pci_psycho_enable_interrupt, |
75 | .clear_interrupt = pci_psycho_clear_interrupt |
75 | .clear_interrupt = pci_psycho_clear_interrupt |
76 | }; |
76 | }; |
77 | 77 | ||
78 | /** Initialize PCI controller (model Sabre). |
78 | /** Initialize PCI controller (model Sabre). |
79 | * |
79 | * |
80 | * @param node OpenFirmware device tree node of the Sabre. |
80 | * @param node OpenFirmware device tree node of the Sabre. |
81 | * |
81 | * |
82 | * @return Address of the initialized PCI structure. |
82 | * @return Address of the initialized PCI structure. |
83 | */ |
83 | */ |
84 | pci_t *pci_sabre_init(ofw_tree_node_t *node) |
84 | pci_t *pci_sabre_init(ofw_tree_node_t *node) |
85 | { |
85 | { |
86 | pci_t *pci; |
86 | pci_t *pci; |
87 | ofw_tree_property_t *prop; |
87 | ofw_tree_property_t *prop; |
88 | 88 | ||
89 | /* |
89 | /* |
90 | * Get registers. |
90 | * Get registers. |
91 | */ |
91 | */ |
92 | prop = ofw_tree_getprop(node, "reg"); |
92 | prop = ofw_tree_getprop(node, "reg"); |
93 | if (!prop || !prop->value) |
93 | if (!prop || !prop->value) |
94 | return NULL; |
94 | return NULL; |
95 | 95 | ||
96 | ofw_upa_reg_t *reg = prop->value; |
96 | ofw_upa_reg_t *reg = prop->value; |
97 | count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
97 | count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
98 | 98 | ||
99 | if (regs < PCI_SABRE_REGS_REG + 1) |
99 | if (regs < PCI_SABRE_REGS_REG + 1) |
100 | return NULL; |
100 | return NULL; |
101 | 101 | ||
102 | uintptr_t paddr; |
102 | uintptr_t paddr; |
103 | if (!ofw_upa_apply_ranges(node->parent, ®[PCI_SABRE_REGS_REG], &paddr)) |
103 | if (!ofw_upa_apply_ranges(node->parent, ®[PCI_SABRE_REGS_REG], &paddr)) |
104 | return NULL; |
104 | return NULL; |
105 | 105 | ||
106 | pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC); |
106 | pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC); |
107 | if (!pci) |
107 | if (!pci) |
108 | return NULL; |
108 | return NULL; |
109 | 109 | ||
110 | pci->model = PCI_SABRE; |
110 | pci->model = PCI_SABRE; |
111 | pci->op = &pci_sabre_ops; |
111 | pci->op = &pci_sabre_ops; |
112 | pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size); |
112 | pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size); |
113 | 113 | ||
114 | return pci; |
114 | return pci; |
115 | } |
115 | } |
116 | 116 | ||
117 | 117 | ||
118 | /** Initialize the Psycho PCI controller. |
118 | /** Initialize the Psycho PCI controller. |
119 | * |
119 | * |
120 | * @param node OpenFirmware device tree node of the Psycho. |
120 | * @param node OpenFirmware device tree node of the Psycho. |
121 | * |
121 | * |
122 | * @return Address of the initialized PCI structure. |
122 | * @return Address of the initialized PCI structure. |
123 | */ |
123 | */ |
124 | pci_t *pci_psycho_init(ofw_tree_node_t *node) |
124 | pci_t *pci_psycho_init(ofw_tree_node_t *node) |
125 | { |
125 | { |
126 | pci_t *pci; |
126 | pci_t *pci; |
127 | ofw_tree_property_t *prop; |
127 | ofw_tree_property_t *prop; |
128 | 128 | ||
129 | /* |
129 | /* |
130 | * Get registers. |
130 | * Get registers. |
131 | */ |
131 | */ |
132 | prop = ofw_tree_getprop(node, "reg"); |
132 | prop = ofw_tree_getprop(node, "reg"); |
133 | if (!prop || !prop->value) |
133 | if (!prop || !prop->value) |
134 | return NULL; |
134 | return NULL; |
135 | 135 | ||
136 | ofw_upa_reg_t *reg = prop->value; |
136 | ofw_upa_reg_t *reg = prop->value; |
137 | count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
137 | count_t regs = prop->size / sizeof(ofw_upa_reg_t); |
138 | 138 | ||
139 | if (regs < PCI_PSYCHO_REGS_REG + 1) |
139 | if (regs < PCI_PSYCHO_REGS_REG + 1) |
140 | return NULL; |
140 | return NULL; |
141 | 141 | ||
142 | uintptr_t paddr; |
142 | uintptr_t paddr; |
143 | if (!ofw_upa_apply_ranges(node->parent, ®[PCI_PSYCHO_REGS_REG], &paddr)) |
143 | if (!ofw_upa_apply_ranges(node->parent, ®[PCI_PSYCHO_REGS_REG], &paddr)) |
144 | return NULL; |
144 | return NULL; |
145 | 145 | ||
146 | pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC); |
146 | pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC); |
147 | if (!pci) |
147 | if (!pci) |
148 | return NULL; |
148 | return NULL; |
149 | 149 | ||
150 | pci->model = PCI_PSYCHO; |
150 | pci->model = PCI_PSYCHO; |
151 | pci->op = &pci_psycho_ops; |
151 | pci->op = &pci_psycho_ops; |
152 | pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size); |
152 | pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size); |
153 | 153 | ||
154 | return pci; |
154 | return pci; |
155 | } |
155 | } |
156 | 156 | ||
157 | void pci_sabre_enable_interrupt(pci_t *pci, int inr) |
157 | void pci_sabre_enable_interrupt(pci_t *pci, int inr) |
158 | { |
158 | { |
159 | pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK; |
159 | pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK; |
160 | } |
160 | } |
161 | 161 | ||
162 | void pci_sabre_clear_interrupt(pci_t *pci, int inr) |
162 | void pci_sabre_clear_interrupt(pci_t *pci, int inr) |
163 | { |
163 | { |
164 | pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0; |
164 | pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0; |
165 | } |
165 | } |
166 | 166 | ||
167 | void pci_psycho_enable_interrupt(pci_t *pci, int inr) |
167 | void pci_psycho_enable_interrupt(pci_t *pci, int inr) |
168 | { |
168 | { |
169 | pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK; |
169 | pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK; |
170 | } |
170 | } |
171 | 171 | ||
172 | void pci_psycho_clear_interrupt(pci_t *pci, int inr) |
172 | void pci_psycho_clear_interrupt(pci_t *pci, int inr) |
173 | { |
173 | { |
174 | pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0; |
174 | pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0; |
175 | } |
175 | } |
176 | 176 | ||
177 | /** Initialize PCI controller. */ |
177 | /** Initialize PCI controller. */ |
178 | pci_t *pci_init(ofw_tree_node_t *node) |
178 | pci_t *pci_init(ofw_tree_node_t *node) |
179 | { |
179 | { |
180 | ofw_tree_property_t *prop; |
180 | ofw_tree_property_t *prop; |
181 | 181 | ||
182 | /* |
182 | /* |
183 | * First, verify this is a PCI node. |
183 | * First, verify this is a PCI node. |
184 | */ |
184 | */ |
185 | ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0); |
185 | ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0); |
186 | 186 | ||
187 | /* |
187 | /* |
188 | * Determine PCI controller model. |
188 | * Determine PCI controller model. |
189 | */ |
189 | */ |
190 | prop = ofw_tree_getprop(node, "model"); |
190 | prop = ofw_tree_getprop(node, "model"); |
191 | if (!prop || !prop->value) |
191 | if (!prop || !prop->value) |
192 | return NULL; |
192 | return NULL; |
193 | 193 | ||
194 | if (strcmp(prop->value, "SUNW,sabre") == 0) { |
194 | if (strcmp(prop->value, "SUNW,sabre") == 0) { |
195 | /* |
195 | /* |
196 | * PCI controller Sabre. |
196 | * PCI controller Sabre. |
197 | * This model is found on UltraSPARC IIi based machines. |
197 | * This model is found on UltraSPARC IIi based machines. |
198 | */ |
198 | */ |
199 | return pci_sabre_init(node); |
199 | return pci_sabre_init(node); |
200 | } else if (strcmp(prop->value, "SUNW,psycho") == 0) { |
200 | } else if (strcmp(prop->value, "SUNW,psycho") == 0) { |
201 | /* |
201 | /* |
202 | * PCI controller Psycho. |
202 | * PCI controller Psycho. |
203 | * Used on UltraSPARC II based processors, for instance, |
203 | * Used on UltraSPARC II based processors, for instance, |
204 | * on Ultra 60. |
204 | * on Ultra 60. |
205 | */ |
205 | */ |
206 | return pci_psycho_init(node); |
206 | return pci_psycho_init(node); |
207 | } else { |
207 | } else { |
208 | /* |
208 | /* |
209 | * Unsupported model. |
209 | * Unsupported model. |
210 | */ |
210 | */ |
211 | printf("Unsupported PCI controller model (%s).\n", prop->value); |
211 | printf("Unsupported PCI controller model (%s).\n", prop->value); |
212 | } |
212 | } |
213 | 213 | ||
214 | return NULL; |
214 | return NULL; |
215 | } |
215 | } |
216 | 216 | ||
217 | void pci_enable_interrupt(pci_t *pci, int inr) |
217 | void pci_enable_interrupt(pci_t *pci, int inr) |
218 | { |
218 | { |
219 | ASSERT(pci->model); |
219 | ASSERT(pci->model); |
220 | ASSERT(pci->op && pci->op->enable_interrupt); |
220 | ASSERT(pci->op && pci->op->enable_interrupt); |
221 | pci->op->enable_interrupt(pci, inr); |
221 | pci->op->enable_interrupt(pci, inr); |
222 | } |
222 | } |
223 | 223 | ||
224 | void pci_clear_interrupt(pci_t *pci, int inr) |
224 | void pci_clear_interrupt(pci_t *pci, int inr) |
225 | { |
225 | { |
226 | ASSERT(pci->model); |
226 | ASSERT(pci->model); |
227 | ASSERT(pci->op && pci->op->clear_interrupt); |
227 | ASSERT(pci->op && pci->op->clear_interrupt); |
228 | pci->op->clear_interrupt(pci, inr); |
228 | pci->op->clear_interrupt(pci, inr); |
229 | } |
229 | } |
230 | 230 | ||
231 | /** @} |
231 | /** @} |
232 | */ |
232 | */ |
233 | 233 |