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/*
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/*
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 * Copyright (C) 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64
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/** @addtogroup sparc64
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 * @{
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 * @{
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 */
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 */
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/**
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/**
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 * @file
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 * @file
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 * @brief   FireHose Controller (FHC) driver.
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 * @brief   FireHose Controller (FHC) driver.
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 *
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 *
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 * Note that this driver is a result of reverse engineering
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 * Note that this driver is a result of reverse engineering
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 * rather than implementation of a specification. This
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 * rather than implementation of a specification. This
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 * is due to the fact that the FHC documentation is not
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 * is due to the fact that the FHC documentation is not
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 * publicly available.
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 * publicly available.
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 */
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 */
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#include <arch/drivers/fhc.h>
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#include <arch/drivers/fhc.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <mm/slab.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <typedefs.h>
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 - 
 
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#include <genarch/ofw/ofw_tree.h>
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#include <genarch/kbd/z8530.h>
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#include <genarch/kbd/z8530.h>
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volatile uint32_t *fhc = NULL;
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fhc_t *central_fhc = NULL;
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- 
 
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/**
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#define FHC_UART_ADDR   0x1fff8808000ULL        /* hardcoded for Simics simulation */
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 * I suspect this must be hardcoded in the FHC.
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 * If it is not, than we can read all IMAP registers
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 * and get the complete mapping.
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 */
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#define FHC_UART_INO    0x39   
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#define FHC_UART_IMAP   0x0
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#define FHC_UART_IMAP   0x0
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#define FHC_UART_ICLR   0x4
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#define FHC_UART_ICLR   0x4
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- 
 
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#define UART_IMAP_REG   4
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void fhc_init(void)
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fhc_t *fhc_init(ofw_tree_node_t *node)
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{
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{
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    fhc_t *fhc;
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    ofw_tree_property_t *prop;
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    prop = ofw_tree_getprop(node, "reg");
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    if (!prop || !prop->value)
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        return NULL;
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    count_t regs = prop->size / sizeof(ofw_central_reg_t);
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    if (regs + 1 < UART_IMAP_REG)
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        return NULL;
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    ofw_central_reg_t *reg = &((ofw_central_reg_t *) prop->value)[UART_IMAP_REG];
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    uintptr_t paddr;
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    if (!ofw_central_apply_ranges(node->parent, reg, &paddr))
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        return NULL;
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    fhc = (void *) hw_map(FHC_UART_ADDR, PAGE_SIZE);
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    fhc = (fhc_t *) malloc(sizeof(fhc_t), FRAME_ATOMIC);
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    if (!fhc)
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        return NULL;
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    fhc->uart_imap = (uint32_t *) hw_map(paddr, reg->size);
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    return fhc;
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}
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void fhc_enable_interrupt(fhc_t *fhc, int ino)
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{
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    switch (ino) {
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    case FHC_UART_INO:
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    fhc[FHC_UART_ICLR] = 0;
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        fhc->uart_imap[FHC_UART_ICLR] = 0x0;
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    fhc[FHC_UART_IMAP] = 0x80000000;
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        fhc->uart_imap[FHC_UART_IMAP] = 0x80000000;
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        break;
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    default:
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        panic("Unexpected INO (%d)\n", ino);
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        break;
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    }
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}
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}
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void fhc_uart_reset(void)
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void fhc_clear_interrupt(fhc_t *fhc, int ino)
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{
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{
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    ASSERT(fhc->uart_imap);
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    switch (ino) {
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    case FHC_UART_INO:
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    fhc[FHC_UART_ICLR] = 0;
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        fhc->uart_imap[FHC_UART_ICLR] = 0;
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        break;
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    default:
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        panic("Unexpected INO (%d)\n", ino);
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        break;
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    }
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}
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}
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/** @}
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/** @}
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 */
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 */
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