WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/trap/mmu.h


/*
 * Copyright (C) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64interrupt
 * @{
 */
/**
 * @file
 * @brief This file contains fast MMU trap handlers.
 */
 
#ifndef KERN_sparc64_MMU_TRAP_H_
#define KERN_sparc64_MMU_TRAP_H_
 
#include <arch/stack.h>
#include <arch/regdef.h>
#include <arch/mm/tlb.h>
#include <arch/mm/mmu.h>
#include <arch/mm/tte.h>
 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
 
#define FAST_MMU_HANDLER_SIZE           128
 
#ifdef __ASM__
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
 
    /*
     * First, try to refill TLB from TSB.
     */
    ! TODO
 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
    /*
     * First, try to refill TLB from TSB.
     */
    ! TODO
 
    /*
     * Second, test if it is the portion of the kernel address space
     * which is faulting. If that is the case, immediately create
     * identity mapping for that page in DTLB. VPN 0 is excluded from
     * this treatment.
     *
     * Note that branch-delay slots are used in order to save space.
     */
0:
    mov VA_DMMU_TAG_ACCESS, %g1
    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
    andcc %g1, %g2, %g3             ! get Context
    bnz 0f                      ! Context is non-zero
    andncc %g1, %g2, %g3                ! get page address into %g3
    bz 0f                       ! page address is zero
 
    or %g3, (TTE_CP|TTE_P|TTE_W), %g2       ! 8K pages are the default (encoded as 0)
        set 1, %g3
        sllx %g3, TTE_V_SHIFT, %g3
        or %g2, %g3, %g2
    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
    retry
 
    /*
     * Third, catch and handle special cases when the trap is caused by
     * some register window trap handler.
     */
0:
    ! TODO
 
0:
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_data_access_protection
 
 
 
.endm
#endif /* __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 1852	Rev 1859
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64interrupt	29	/** @addtogroup sparc64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief This file contains fast MMU trap handlers.	34	* @brief This file contains fast MMU trap handlers.
35	*/	35	*/
36		36
37	#ifndef __sparc64_MMU_TRAP_H__	37	#ifndef KERN_sparc64_MMU_TRAP_H_
38	#define __sparc64_MMU_TRAP_H__	38	#define KERN_sparc64_MMU_TRAP_H_
39		39
40	#include <arch/stack.h>	40	#include <arch/stack.h>
41	#include <arch/regdef.h>	41	#include <arch/regdef.h>
42	#include <arch/mm/tlb.h>	42	#include <arch/mm/tlb.h>
43	#include <arch/mm/mmu.h>	43	#include <arch/mm/mmu.h>
44	#include <arch/mm/tte.h>	44	#include <arch/mm/tte.h>
45		45
46	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64	46	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
47	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68	47	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
48	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c	48	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
49		49
50	#define FAST_MMU_HANDLER_SIZE 128	50	#define FAST_MMU_HANDLER_SIZE 128
51		51
52	#ifdef __ASM__	52	#ifdef __ASM__
53	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER	53	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
54	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp	-
-		54	/*
55	call fast_instruction_access_mmu_miss	55	* First, try to refill TLB from TSB.
56	nop	56	*/
57	restore	57	! TODO
58	retry	58
-		59	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
-		60	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
59	.endm	61	.endm
60		62
61	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER	63	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
62	/*	64	/*
63	* First, try to refill TLB from TSB.	65	* First, try to refill TLB from TSB.
64	*/	66	*/
65	! TODO	67	! TODO
66		68
67	/*	69	/*
68	* Second, test if it is the portion of the kernel address space	70	* Second, test if it is the portion of the kernel address space
69	* which is faulting. If that is the case, immediately create	71	* which is faulting. If that is the case, immediately create
70	* identity mapping for that page in DTLB. VPN 0 is excluded from	72	* identity mapping for that page in DTLB. VPN 0 is excluded from
71	* this treatment.	73	* this treatment.
72	*	74	*
73	* Note that branch-delay slots are used in order to save space.	75	* Note that branch-delay slots are used in order to save space.
74	*/	76	*/
75	0:	77	0:
76	mov VA_DMMU_TAG_ACCESS, %g1	78	mov VA_DMMU_TAG_ACCESS, %g1
77	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN	79	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN
78	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2	80	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
79	andcc %g1, %g2, %g3 ! get Context	81	andcc %g1, %g2, %g3 ! get Context
80	bnz 0f ! Context is non-zero	82	bnz 0f ! Context is non-zero
81	andncc %g1, %g2, %g3 ! get page address into %g3	83	andncc %g1, %g2, %g3 ! get page address into %g3
82	bz 0f ! page address is zero	84	bz 0f ! page address is zero
83		85
84	or %g3, (TTE_CP\|TTE_P\|TTE_W), %g2 ! 8K pages are the default (encoded as 0)	86	or %g3, (TTE_CP\|TTE_P\|TTE_W), %g2 ! 8K pages are the default (encoded as 0)
85	set 1, %g3	87	set 1, %g3
86	sllx %g3, TTE_V_SHIFT, %g3	88	sllx %g3, TTE_V_SHIFT, %g3
87	or %g2, %g3, %g2	89	or %g2, %g3, %g2
88	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page	90	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page
89	retry	91	retry
90		92
91	/*	93	/*
92	* Third, catch and handle special cases when the trap is caused by	94	* Third, catch and handle special cases when the trap is caused by
93	* some register window trap handler.	95	* some register window trap handler.
94	*/	96	*/
95	0:	97	0:
96	! TODO	98	! TODO
97		99
98	0:	100	0:
99	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	101	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
100	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss	102	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
101	.endm	103	.endm
102		104
103	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER	105	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
104	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp	106	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
105	call fast_data_access_protection	107	PREEMPTIBLE_HANDLER fast_data_access_protection
106	nop	-
107	restore	-
108	retry	-
109	.endm	108	.endm
110	#endif /* __ASM__ */	109	#endif /* __ASM__ */
111		110
112	#endif	111	#endif
113		112
114	/** @}	113	/** @}
115	*/	114	*/
116		115

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(root)/trunk/kernel/arch/sparc64/include/trap/mmu.h @ 2472 – Rev 1852 → 1859