WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/trap/mmu.h


/*
 * Copyright (C) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64interrupt
 * @{
 */
/**
 * @file
 * @brief This file contains fast MMU trap handlers.
 */
 
#ifndef KERN_sparc64_MMU_TRAP_H_
#define KERN_sparc64_MMU_TRAP_H_
 
#include <arch/stack.h>
#include <arch/regdef.h>
#include <arch/mm/tlb.h>
#include <arch/mm/mmu.h>
#include <arch/mm/tte.h>
#include <arch/trap/regwin.h>
 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS        0x68
#define TT_FAST_DATA_ACCESS_PROTECTION      0x6c
 
#define FAST_MMU_HANDLER_SIZE           128
 
#ifdef __ASM__
 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    /*
     * First, try to refill TLB from TSB.
     */
    ! TODO
 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
    /*
     * First, try to refill TLB from TSB.
     */
    ! TODO
 
    /*
     * Second, test if it is the portion of the kernel address space
     * which is faulting. If that is the case, immediately create
     * identity mapping for that page in DTLB. VPN 0 is excluded from
     * this treatment.
     *
     * Note that branch-delay slots are used in order to save space.
     */
 
    mov VA_DMMU_TAG_ACCESS, %g1
    ldxa [%g1] ASI_DMMU, %g1            ! read the faulting Context and VPN
    set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
    andcc %g1, %g2, %g3             ! get Context
    bnz 0f                      ! Context is non-zero
    andncc %g1, %g2, %g3                ! get page address into %g3
    bz 0f                       ! page address is zero
 
    or %g3, (TTE_CP|TTE_P|TTE_W), %g2       ! 8K pages are the default (encoded as 0)
    mov 1, %g3
    sllx %g3, TTE_V_SHIFT, %g3
    or %g2, %g3, %g2
    stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG        ! identity map the kernel page
    retry
 
    /*
     * Third, catch and handle special cases when the trap is caused by
     * the userspace register window spill or fill handler. In case
     * one of these two traps caused this trap, we just lower the trap
     * level and service the DTLB miss. In the end, we restart
     * the offending SAVE or RESTORE.
     */
0:
    HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
    /*
     * First, try to refill TLB from TSB.
     */
    ! TODO
 
    /*
     * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
     */
    HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
 
    wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    PREEMPTIBLE_HANDLER fast_data_access_protection
.endm
 
/*
 * Macro used to lower TL when a MMU trap is caused by
 * the userspace register window spill or fill handler.
 */
.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
    rdpr %tl, %g1
    dec %g1
    brz %g1, 0f         ! if TL was 1, skip
    nop
    wrpr %g1, 0, %tl        ! TL--
    rdpr %tt, %g2
    cmp %g2, TT_SPILL_1_NORMAL
    be 0f               ! trap from spill_1_normal
    cmp %g2, TT_FILL_1_NORMAL
    be 0f               ! trap from fill_1_normal
    inc %g1
    wrpr %g1, 0, %tl        ! another trap, TL++
0:
.endm
 
#endif /* __ASM__ */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/trap/mmu.h – Rev 1860 → 1861

Rev 1860		Rev 1861
1	/*	1	/*
2	* Copyright (C) 2006 Jakub Jermar	2	* Copyright (C) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64interrupt	29	/** @addtogroup sparc64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief This file contains fast MMU trap handlers.	34	* @brief This file contains fast MMU trap handlers.
35	*/	35	*/
36		36
37	#ifndef KERN_sparc64_MMU_TRAP_H_	37	#ifndef KERN_sparc64_MMU_TRAP_H_
38	#define KERN_sparc64_MMU_TRAP_H_	38	#define KERN_sparc64_MMU_TRAP_H_
39		39
40	#include <arch/stack.h>	40	#include <arch/stack.h>
41	#include <arch/regdef.h>	41	#include <arch/regdef.h>
42	#include <arch/mm/tlb.h>	42	#include <arch/mm/tlb.h>
43	#include <arch/mm/mmu.h>	43	#include <arch/mm/mmu.h>
44	#include <arch/mm/tte.h>	44	#include <arch/mm/tte.h>
45	#include <arch/trap/regwin.h>	45	#include <arch/trap/regwin.h>
46		46
47	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64	47	#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
48	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68	48	#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
49	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c	49	#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
50		50
51	#define FAST_MMU_HANDLER_SIZE 128	51	#define FAST_MMU_HANDLER_SIZE 128
52		52
53	#ifdef __ASM__	53	#ifdef __ASM__
54		54
55	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER	55	.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
56	!	56	/*
57	! First, try to refill TLB from TSB.	57	* First, try to refill TLB from TSB.
58	!	58	*/
59	! TODO	59	! TODO
60		60
61	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	61	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
62	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss	62	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
63	.endm	63	.endm
64		64
65	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER	65	.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
66	/*	66	/*
67	* First, try to refill TLB from TSB.	67	* First, try to refill TLB from TSB.
68	*/	68	*/
69	! TODO	69	! TODO
70		70
71	/*	71	/*
72	* Second, test if it is the portion of the kernel address space	72	* Second, test if it is the portion of the kernel address space
73	* which is faulting. If that is the case, immediately create	73	* which is faulting. If that is the case, immediately create
74	* identity mapping for that page in DTLB. VPN 0 is excluded from	74	* identity mapping for that page in DTLB. VPN 0 is excluded from
75	* this treatment.	75	* this treatment.
76	*	76	*
77	* Note that branch-delay slots are used in order to save space.	77	* Note that branch-delay slots are used in order to save space.
78	*/	78	*/
79		79
80	mov VA_DMMU_TAG_ACCESS, %g1	80	mov VA_DMMU_TAG_ACCESS, %g1
81	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN	81	ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN
82	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2	82	set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
83	andcc %g1, %g2, %g3 ! get Context	83	andcc %g1, %g2, %g3 ! get Context
84	bnz 0f ! Context is non-zero	84	bnz 0f ! Context is non-zero
85	andncc %g1, %g2, %g3 ! get page address into %g3	85	andncc %g1, %g2, %g3 ! get page address into %g3
86	bz 0f ! page address is zero	86	bz 0f ! page address is zero
87		87
88	or %g3, (TTE_CP\|TTE_P\|TTE_W), %g2 ! 8K pages are the default (encoded as 0)	88	or %g3, (TTE_CP\|TTE_P\|TTE_W), %g2 ! 8K pages are the default (encoded as 0)
89	mov 1, %g3	89	mov 1, %g3
90	sllx %g3, TTE_V_SHIFT, %g3	90	sllx %g3, TTE_V_SHIFT, %g3
91	or %g2, %g3, %g2	91	or %g2, %g3, %g2
92	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page	92	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page
93	retry	93	retry
94		94
95	/*	95	/*
96	* Third, catch and handle special cases when the trap is caused by	96	* Third, catch and handle special cases when the trap is caused by
97	* the userspace register window spill or fill handler. In case	97	* the userspace register window spill or fill handler. In case
98	* one of these two traps caused this trap, we just lower the trap	98	* one of these two traps caused this trap, we just lower the trap
99	* level and service the DTLB miss. In the end, we restart	99	* level and service the DTLB miss. In the end, we restart
100	* the offending SAVE or RESTORE.	100	* the offending SAVE or RESTORE.
101	*/	101	*/
102	0:	102	0:
103	HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL	103	HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
104		104
105	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	105	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
106	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss	106	PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
107	.endm	107	.endm
108		108
109	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER	109	.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
110	/*	110	/*
111	* First, try to refill TLB from TSB.	111	* First, try to refill TLB from TSB.
112	*/	112	*/
113	! TODO	113	! TODO
114		114
115	/*	115	/*
116	* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.	116	* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
117	*/	117	*/
118	HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL	118	HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
119		119
120	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate	120	wrpr %g0, PSTATE_PRIV_BIT \| PSTATE_AG_BIT, %pstate
121	PREEMPTIBLE_HANDLER fast_data_access_protection	121	PREEMPTIBLE_HANDLER fast_data_access_protection
122	.endm	122	.endm
123		123
124	/*	124	/*
125	* Macro used to lower TL when a MMU trap is caused by	125	* Macro used to lower TL when a MMU trap is caused by
126	* the userspace register window spill or fill handler.	126	* the userspace register window spill or fill handler.
127	*/	127	*/
128	.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL	128	.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL
129	rdpr %tl, %g1	129	rdpr %tl, %g1
130	dec %g1	130	dec %g1
131	brz %g1, 0f ! if TL was 1, skip	131	brz %g1, 0f ! if TL was 1, skip
132	nop	132	nop
133	wrpr %g1, 0, %tl ! TL--	133	wrpr %g1, 0, %tl ! TL--
134	rdpr %tt, %g2	134	rdpr %tt, %g2
135	cmp %g2, TT_SPILL_1_NORMAL	135	cmp %g2, TT_SPILL_1_NORMAL
136	be 0f ! trap from spill_1_normal	136	be 0f ! trap from spill_1_normal
137	cmp %g2, TT_FILL_1_NORMAL	137	cmp %g2, TT_FILL_1_NORMAL
138	be 0f ! trap from fill_1_normal	138	be 0f ! trap from fill_1_normal
139	inc %g1	139	inc %g1
140	wrpr %g1, 0, %tl ! another trap, TL++	140	wrpr %g1, 0, %tl ! another trap, TL++
141	0:	141	0:
142	.endm	142	.endm
143		143
144	#endif /* __ASM__ */	144	#endif /* __ASM__ */
145		145
146	#endif	146	#endif
147		147
148	/** @}	148	/** @}
149	*/	149	*/
150		150