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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64interrupt |
29 | /** @addtogroup sparc64interrupt |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** |
32 | /** |
33 | * @file |
33 | * @file |
34 | * @brief This file contains interrupt vector trap handler. |
34 | * @brief This file contains interrupt vector trap handler. |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #ifndef __sparc64_TRAP_INTERRUPT_H__ |
37 | #ifndef __sparc64_TRAP_INTERRUPT_H__ |
38 | #define __sparc64_TRAP_INTERRUPT_H__ |
38 | #define __sparc64_TRAP_INTERRUPT_H__ |
39 | 39 | ||
40 | #include <arch/trap/trap_table.h> |
40 | #include <arch/trap/trap_table.h> |
41 | #include <arch/stack.h> |
41 | #include <arch/stack.h> |
42 | 42 | ||
43 | /* Interrupt ASI registers. */ |
43 | /* Interrupt ASI registers. */ |
44 | #define ASI_UDB_INTR_W 0x77 |
44 | #define ASI_UDB_INTR_W 0x77 |
45 | #define ASI_INTR_DISPATCH_STATUS 0x48 |
45 | #define ASI_INTR_DISPATCH_STATUS 0x48 |
46 | #define ASI_UDB_INTR_R 0x7f |
46 | #define ASI_UDB_INTR_R 0x7f |
47 | #define ASI_INTR_RECEIVE 0x49 |
47 | #define ASI_INTR_RECEIVE 0x49 |
48 | 48 | ||
49 | /* VA's used with ASI_UDB_INTR_W register. */ |
49 | /* VA's used with ASI_UDB_INTR_W register. */ |
50 | #define ASI_UDB_INTR_W_DATA_0 0x40 |
50 | #define ASI_UDB_INTR_W_DATA_0 0x40 |
51 | #define ASI_UDB_INTR_W_DATA_1 0x50 |
51 | #define ASI_UDB_INTR_W_DATA_1 0x50 |
52 | #define ASI_UDB_INTR_W_DATA_2 0x60 |
52 | #define ASI_UDB_INTR_W_DATA_2 0x60 |
53 | 53 | ||
54 | /* VA's used with ASI_UDB_INTR_R register. */ |
54 | /* VA's used with ASI_UDB_INTR_R register. */ |
55 | #define ASI_UDB_INTR_R_DATA_0 0x40 |
55 | #define ASI_UDB_INTR_R_DATA_0 0x40 |
56 | #define ASI_UDB_INTR_R_DATA_1 0x50 |
56 | #define ASI_UDB_INTR_R_DATA_1 0x50 |
57 | #define ASI_UDB_INTR_R_DATA_2 0x60 |
57 | #define ASI_UDB_INTR_R_DATA_2 0x60 |
58 | 58 | ||
59 | #define TT_INTERRUPT_LEVEL_1 0x41 |
59 | #define TT_INTERRUPT_LEVEL_1 0x41 |
60 | #define TT_INTERRUPT_LEVEL_2 0x42 |
60 | #define TT_INTERRUPT_LEVEL_2 0x42 |
61 | #define TT_INTERRUPT_LEVEL_3 0x43 |
61 | #define TT_INTERRUPT_LEVEL_3 0x43 |
62 | #define TT_INTERRUPT_LEVEL_4 0x44 |
62 | #define TT_INTERRUPT_LEVEL_4 0x44 |
63 | #define TT_INTERRUPT_LEVEL_5 0x45 |
63 | #define TT_INTERRUPT_LEVEL_5 0x45 |
64 | #define TT_INTERRUPT_LEVEL_6 0x46 |
64 | #define TT_INTERRUPT_LEVEL_6 0x46 |
65 | #define TT_INTERRUPT_LEVEL_7 0x47 |
65 | #define TT_INTERRUPT_LEVEL_7 0x47 |
66 | #define TT_INTERRUPT_LEVEL_8 0x48 |
66 | #define TT_INTERRUPT_LEVEL_8 0x48 |
67 | #define TT_INTERRUPT_LEVEL_9 0x49 |
67 | #define TT_INTERRUPT_LEVEL_9 0x49 |
68 | #define TT_INTERRUPT_LEVEL_10 0x4a |
68 | #define TT_INTERRUPT_LEVEL_10 0x4a |
69 | #define TT_INTERRUPT_LEVEL_11 0x4b |
69 | #define TT_INTERRUPT_LEVEL_11 0x4b |
70 | #define TT_INTERRUPT_LEVEL_12 0x4c |
70 | #define TT_INTERRUPT_LEVEL_12 0x4c |
71 | #define TT_INTERRUPT_LEVEL_13 0x4d |
71 | #define TT_INTERRUPT_LEVEL_13 0x4d |
72 | #define TT_INTERRUPT_LEVEL_14 0x4e |
72 | #define TT_INTERRUPT_LEVEL_14 0x4e |
73 | #define TT_INTERRUPT_LEVEL_15 0x4f |
73 | #define TT_INTERRUPT_LEVEL_15 0x4f |
74 | 74 | ||
75 | #define TT_INTERRUPT_VECTOR_TRAP 0x60 |
75 | #define TT_INTERRUPT_VECTOR_TRAP 0x60 |
76 | 76 | ||
77 | #define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
77 | #define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
78 | #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
78 | #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
79 | 79 | ||
80 | #ifdef __ASM__ |
80 | #ifdef __ASM__ |
81 | .macro INTERRUPT_LEVEL_N_HANDLER n |
81 | .macro INTERRUPT_LEVEL_N_HANDLER n |
82 | save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp |
- | |
83 | mov \n - 1, %o0 |
82 | mov \n - 1, %g2 |
84 | PREEMPTIBLE_HANDLER exc_dispatch |
83 | PREEMPTIBLE_HANDLER exc_dispatch |
85 | .endm |
84 | .endm |
86 | 85 | ||
87 | .macro INTERRUPT_VECTOR_TRAP_HANDLER |
86 | .macro INTERRUPT_VECTOR_TRAP_HANDLER |
88 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
87 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
89 | SIMPLE_HANDLER interrupt |
88 | SIMPLE_HANDLER interrupt |
90 | restore |
89 | restore |
91 | retry |
90 | retry |
92 | .endm |
91 | .endm |
93 | #endif /* __ASM__ */ |
92 | #endif /* __ASM__ */ |
94 | 93 | ||
95 | #ifndef __ASM__ |
94 | #ifndef __ASM__ |
96 | extern void interrupt(void); |
95 | extern void interrupt(void); |
97 | #endif /* !def __ASM__ */ |
96 | #endif /* !def __ASM__ */ |
98 | 97 | ||
99 | #endif |
98 | #endif |
100 | 99 | ||
101 | /** @} |
100 | /** @} |
102 | */ |
101 | */ |
103 | 102 |