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/*
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/*
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 * Copyright (C) 2006 Jakub Jermar
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 * Copyright (C) 2006 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64mm  
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/** @addtogroup sparc64mm  
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#ifndef KERN_sparc64_TSB_H_
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#ifndef KERN_sparc64_TSB_H_
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#define KERN_sparc64_TSB_H_
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#define KERN_sparc64_TSB_H_
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#include <arch/mm/tte.h>
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#include <arch/mm/mmu.h>
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#include <arch/types.h>
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#include <typedefs.h>
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/*
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/*
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 * ITSB abd DTSB will claim 64K of memory, which
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 * ITSB abd DTSB will claim 64K of memory, which
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 * is a nice number considered that it is one of
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 * is a nice number considered that it is one of
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 * the page sizes supported by hardware, which,
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 * the page sizes supported by hardware, which,
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 * again, is nice because TSBs need to be locked
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 * again, is nice because TSBs need to be locked
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 * in TLBs - only one TLB entry will do.
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 * in TLBs - only one TLB entry will do.
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 */
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 */
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#define TSB_SIZE            2           /* when changing this, change as.c as well */
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#define TSB_SIZE            2           /* when changing this, change as.c as well */
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#define ITSB_ENTRY_COUNT        (512*(1<<TSB_SIZE))
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#define ITSB_ENTRY_COUNT        (512*(1<<TSB_SIZE))
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#define DTSB_ENTRY_COUNT        (512*(1<<TSB_SIZE))
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#define DTSB_ENTRY_COUNT        (512*(1<<TSB_SIZE))
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- 
 
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#define TSB_TAG_TARGET_CONTEXT_SHIFT    48
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#ifndef __ASM__
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#include <arch/mm/tte.h>
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#include <arch/mm/mmu.h>
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#include <arch/types.h>
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#include <typedefs.h>
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/** TSB Tag Target register. */
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union tsb_tag_target {
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    uint64_t value;
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    struct {
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        unsigned invalid : 1;   /**< Invalidated by software. */
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        unsigned : 2;
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        unsigned context : 13;  /**< Software ASID. */
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        unsigned : 6;
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        uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
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    } __attribute__ ((packed));
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};
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typedef union tsb_tag_target tsb_tag_target_t;
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/** TSB entry. */
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struct tsb_entry {
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struct tsb_entry {
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    tte_tag_t tag;
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    tsb_tag_target_t tag;
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    tte_data_t data;
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    tte_data_t data;
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} __attribute__ ((packed));
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} __attribute__ ((packed));
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typedef struct tsb_entry tsb_entry_t;
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typedef struct tsb_entry tsb_entry_t;
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/** TSB Base register. */
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/** TSB Base register. */
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union tsb_base_reg {
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union tsb_base_reg {
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    uint64_t value;
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    uint64_t value;
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    struct {
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    struct {
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        uint64_t base : 51; /**< TSB base address, bits 63:13. */
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        uint64_t base : 51; /**< TSB base address, bits 63:13. */
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        unsigned split : 1; /**< Split vs. common TSB for 8K and 64K pages.
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        unsigned split : 1; /**< Split vs. common TSB for 8K and 64K pages.
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                      *  HelenOS uses only 8K pages for user mappings,
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                      *  HelenOS uses only 8K pages for user mappings,
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                      *  so we always set this to 0.
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                      *  so we always set this to 0.
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                      */
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                      */
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        unsigned : 9;
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        unsigned : 9;
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        unsigned size : 3;  /**< TSB size. Number of entries is 512*2^size. */
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        unsigned size : 3;  /**< TSB size. Number of entries is 512*2^size. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union tsb_base_reg tsb_base_reg_t;
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typedef union tsb_base_reg tsb_base_reg_t;
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/** Read ITSB Base register.
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/** Read ITSB Base register.
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 *
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 *
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 * @return Content of the ITSB Base register.
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 * @return Content of the ITSB Base register.
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 */
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 */
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static inline uint64_t itsb_base_read(void)
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static inline uint64_t itsb_base_read(void)
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{
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{
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    return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
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    return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
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}
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}
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/** Read DTSB Base register.
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/** Read DTSB Base register.
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 *
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 *
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 * @return Content of the DTSB Base register.
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 * @return Content of the DTSB Base register.
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 */
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 */
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static inline uint64_t dtsb_base_read(void)
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static inline uint64_t dtsb_base_read(void)
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{
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{
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    return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
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    return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
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}
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}
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/** Write ITSB Base register.
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/** Write ITSB Base register.
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 *
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 *
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 * @param v New content of the ITSB Base register.
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 * @param v New content of the ITSB Base register.
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 */
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 */
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static inline void itsb_base_write(uint64_t v)
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static inline void itsb_base_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
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    asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
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}
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}
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/** Write DTSB Base register.
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/** Write DTSB Base register.
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 *
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 *
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 * @param v New content of the DTSB Base register.
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 * @param v New content of the DTSB Base register.
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 */
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 */
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static inline void dtsb_base_write(uint64_t v)
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static inline void dtsb_base_write(uint64_t v)
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{
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{
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    asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
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    asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
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}
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}
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extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages);
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extern void tsb_invalidate(as_t *as, uintptr_t page, count_t pages);
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extern void itsb_pte_copy(pte_t *t);
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extern void dtsb_pte_copy(pte_t *t, bool ro);
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#endif /* !def __ASM__ */
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */
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