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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64mm |
29 | /** @addtogroup sparc64mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef __sparc64_TLB_H__ |
35 | #ifndef __sparc64_TLB_H__ |
36 | #define __sparc64_TLB_H__ |
36 | #define __sparc64_TLB_H__ |
37 | 37 | ||
38 | #include <arch/mm/tte.h> |
- | |
39 | #include <arch/mm/mmu.h> |
- | |
40 | #include <arch/mm/page.h> |
- | |
41 | #include <arch/asm.h> |
- | |
42 | #include <arch/barrier.h> |
- | |
43 | #include <arch/types.h> |
- | |
44 | #include <typedefs.h> |
- | |
45 | 38 | ||
46 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
47 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
48 | 41 | ||
- | 42 | #define MEM_CONTEXT_KERNEL 0 |
|
- | 43 | #define MEM_CONTEXT_TEMP 1 |
|
- | 44 | ||
49 | /** Page sizes. */ |
45 | /** Page sizes. */ |
50 | #define PAGESIZE_8K 0 |
46 | #define PAGESIZE_8K 0 |
51 | #define PAGESIZE_64K 1 |
47 | #define PAGESIZE_64K 1 |
52 | #define PAGESIZE_512K 2 |
48 | #define PAGESIZE_512K 2 |
53 | #define PAGESIZE_4M 3 |
49 | #define PAGESIZE_4M 3 |
54 | 50 | ||
55 | /** Bit width of the TLB-locked portion of kernel address space. */ |
51 | /** Bit width of the TLB-locked portion of kernel address space. */ |
56 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
52 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
57 | 53 | ||
- | 54 | /* TLB Demap Operation types. */ |
|
- | 55 | #define TLB_DEMAP_PAGE 0 |
|
- | 56 | #define TLB_DEMAP_CONTEXT 1 |
|
- | 57 | ||
- | 58 | #define TLB_DEMAP_TYPE_SHIFT 6 |
|
- | 59 | ||
- | 60 | /* TLB Demap Operation Context register encodings. */ |
|
- | 61 | #define TLB_DEMAP_PRIMARY 0 |
|
- | 62 | #define TLB_DEMAP_SECONDARY 1 |
|
- | 63 | #define TLB_DEMAP_NUCLEUS 2 |
|
- | 64 | ||
- | 65 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
|
- | 66 | ||
- | 67 | /* TLB Tag Access shifts */ |
|
- | 68 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
|
- | 69 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
|
- | 70 | ||
- | 71 | #ifndef __ASM__ |
|
- | 72 | ||
- | 73 | #include <arch/mm/tte.h> |
|
- | 74 | #include <arch/mm/mmu.h> |
|
- | 75 | #include <arch/mm/page.h> |
|
- | 76 | #include <arch/asm.h> |
|
- | 77 | #include <arch/barrier.h> |
|
- | 78 | #include <arch/types.h> |
|
- | 79 | #include <typedefs.h> |
|
- | 80 | ||
58 | union tlb_context_reg { |
81 | union tlb_context_reg { |
59 | uint64_t v; |
82 | uint64_t v; |
60 | struct { |
83 | struct { |
61 | unsigned long : 51; |
84 | unsigned long : 51; |
62 | unsigned context : 13; /**< Context/ASID. */ |
85 | unsigned context : 13; /**< Context/ASID. */ |
63 | } __attribute__ ((packed)); |
86 | } __attribute__ ((packed)); |
64 | }; |
87 | }; |
65 | typedef union tlb_context_reg tlb_context_reg_t; |
88 | typedef union tlb_context_reg tlb_context_reg_t; |
66 | 89 | ||
67 | /** I-/D-TLB Data In/Access Register type. */ |
90 | /** I-/D-TLB Data In/Access Register type. */ |
68 | typedef tte_data_t tlb_data_t; |
91 | typedef tte_data_t tlb_data_t; |
69 | 92 | ||
70 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
93 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
71 | union tlb_data_access_addr { |
94 | union tlb_data_access_addr { |
72 | uint64_t value; |
95 | uint64_t value; |
73 | struct { |
96 | struct { |
74 | uint64_t : 55; |
97 | uint64_t : 55; |
75 | unsigned tlb_entry : 6; |
98 | unsigned tlb_entry : 6; |
76 | unsigned : 3; |
99 | unsigned : 3; |
77 | } __attribute__ ((packed)); |
100 | } __attribute__ ((packed)); |
78 | }; |
101 | }; |
79 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
102 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
80 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
103 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
81 | 104 | ||
82 | /** I-/D-TLB Tag Read Register. */ |
105 | /** I-/D-TLB Tag Read Register. */ |
83 | union tlb_tag_read_reg { |
106 | union tlb_tag_read_reg { |
84 | uint64_t value; |
107 | uint64_t value; |
85 | struct { |
108 | struct { |
86 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
109 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
87 | unsigned context : 13; /**< Context identifier. */ |
110 | unsigned context : 13; /**< Context identifier. */ |
88 | } __attribute__ ((packed)); |
111 | } __attribute__ ((packed)); |
89 | }; |
112 | }; |
90 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
113 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
91 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
114 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
92 | 115 | ||
93 | /** TLB Demap Operation types. */ |
- | |
94 | #define TLB_DEMAP_PAGE 0 |
- | |
95 | #define TLB_DEMAP_CONTEXT 1 |
- | |
96 | - | ||
97 | /** TLB Demap Operation Context register encodings. */ |
- | |
98 | #define TLB_DEMAP_PRIMARY 0 |
- | |
99 | #define TLB_DEMAP_SECONDARY 1 |
- | |
100 | #define TLB_DEMAP_NUCLEUS 2 |
- | |
101 | 116 | ||
102 | /** TLB Demap Operation Address. */ |
117 | /** TLB Demap Operation Address. */ |
103 | union tlb_demap_addr { |
118 | union tlb_demap_addr { |
104 | uint64_t value; |
119 | uint64_t value; |
105 | struct { |
120 | struct { |
106 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
121 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
107 | unsigned : 6; /**< Ignored. */ |
122 | unsigned : 6; /**< Ignored. */ |
108 | unsigned type : 1; /**< The type of demap operation. */ |
123 | unsigned type : 1; /**< The type of demap operation. */ |
109 | unsigned context : 2; /**< Context register selection. */ |
124 | unsigned context : 2; /**< Context register selection. */ |
110 | unsigned : 4; /**< Zero. */ |
125 | unsigned : 4; /**< Zero. */ |
111 | } __attribute__ ((packed)); |
126 | } __attribute__ ((packed)); |
112 | }; |
127 | }; |
113 | typedef union tlb_demap_addr tlb_demap_addr_t; |
128 | typedef union tlb_demap_addr tlb_demap_addr_t; |
114 | 129 | ||
115 | /** TLB Synchronous Fault Status Register. */ |
130 | /** TLB Synchronous Fault Status Register. */ |
116 | union tlb_sfsr_reg { |
131 | union tlb_sfsr_reg { |
117 | uint64_t value; |
132 | uint64_t value; |
118 | struct { |
133 | struct { |
119 | unsigned long : 39; /**< Implementation dependent. */ |
134 | unsigned long : 39; /**< Implementation dependent. */ |
120 | unsigned nf : 1; /**< Nonfaulting load. */ |
135 | unsigned nf : 1; /**< Nonfaulting load. */ |
121 | unsigned asi : 8; /**< ASI. */ |
136 | unsigned asi : 8; /**< ASI. */ |
122 | unsigned tm : 1; /**< TLB miss. */ |
137 | unsigned tm : 1; /**< TLB miss. */ |
123 | unsigned : 1; |
138 | unsigned : 1; |
124 | unsigned ft : 7; /**< Fault type. */ |
139 | unsigned ft : 7; /**< Fault type. */ |
125 | unsigned e : 1; /**< Side-effect bit. */ |
140 | unsigned e : 1; /**< Side-effect bit. */ |
126 | unsigned ct : 2; /**< Context Register selection. */ |
141 | unsigned ct : 2; /**< Context Register selection. */ |
127 | unsigned pr : 1; /**< Privilege bit. */ |
142 | unsigned pr : 1; /**< Privilege bit. */ |
128 | unsigned w : 1; /**< Write bit. */ |
143 | unsigned w : 1; /**< Write bit. */ |
129 | unsigned ow : 1; /**< Overwrite bit. */ |
144 | unsigned ow : 1; /**< Overwrite bit. */ |
130 | unsigned fv : 1; /**< Fault Valid bit. */ |
145 | unsigned fv : 1; /**< Fault Valid bit. */ |
131 | } __attribute__ ((packed)); |
146 | } __attribute__ ((packed)); |
132 | }; |
147 | }; |
133 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
148 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
134 | 149 | ||
135 | /** Read MMU Primary Context Register. |
150 | /** Read MMU Primary Context Register. |
136 | * |
151 | * |
137 | * @return Current value of Primary Context Register. |
152 | * @return Current value of Primary Context Register. |
138 | */ |
153 | */ |
139 | static inline uint64_t mmu_primary_context_read(void) |
154 | static inline uint64_t mmu_primary_context_read(void) |
140 | { |
155 | { |
141 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
156 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
142 | } |
157 | } |
143 | 158 | ||
144 | /** Write MMU Primary Context Register. |
159 | /** Write MMU Primary Context Register. |
145 | * |
160 | * |
146 | * @param v New value of Primary Context Register. |
161 | * @param v New value of Primary Context Register. |
147 | */ |
162 | */ |
148 | static inline void mmu_primary_context_write(uint64_t v) |
163 | static inline void mmu_primary_context_write(uint64_t v) |
149 | { |
164 | { |
150 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
165 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
151 | flush(); |
166 | flush(); |
152 | } |
167 | } |
153 | 168 | ||
154 | /** Read MMU Secondary Context Register. |
169 | /** Read MMU Secondary Context Register. |
155 | * |
170 | * |
156 | * @return Current value of Secondary Context Register. |
171 | * @return Current value of Secondary Context Register. |
157 | */ |
172 | */ |
158 | static inline uint64_t mmu_secondary_context_read(void) |
173 | static inline uint64_t mmu_secondary_context_read(void) |
159 | { |
174 | { |
160 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
175 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
161 | } |
176 | } |
162 | 177 | ||
163 | /** Write MMU Primary Context Register. |
178 | /** Write MMU Primary Context Register. |
164 | * |
179 | * |
165 | * @param v New value of Primary Context Register. |
180 | * @param v New value of Primary Context Register. |
166 | */ |
181 | */ |
167 | static inline void mmu_secondary_context_write(uint64_t v) |
182 | static inline void mmu_secondary_context_write(uint64_t v) |
168 | { |
183 | { |
169 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
184 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
170 | flush(); |
185 | flush(); |
171 | } |
186 | } |
172 | 187 | ||
173 | /** Read IMMU TLB Data Access Register. |
188 | /** Read IMMU TLB Data Access Register. |
174 | * |
189 | * |
175 | * @param entry TLB Entry index. |
190 | * @param entry TLB Entry index. |
176 | * |
191 | * |
177 | * @return Current value of specified IMMU TLB Data Access Register. |
192 | * @return Current value of specified IMMU TLB Data Access Register. |
178 | */ |
193 | */ |
179 | static inline uint64_t itlb_data_access_read(index_t entry) |
194 | static inline uint64_t itlb_data_access_read(index_t entry) |
180 | { |
195 | { |
181 | tlb_data_access_addr_t reg; |
196 | tlb_data_access_addr_t reg; |
182 | 197 | ||
183 | reg.value = 0; |
198 | reg.value = 0; |
184 | reg.tlb_entry = entry; |
199 | reg.tlb_entry = entry; |
185 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
200 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
186 | } |
201 | } |
187 | 202 | ||
188 | /** Write IMMU TLB Data Access Register. |
203 | /** Write IMMU TLB Data Access Register. |
189 | * |
204 | * |
190 | * @param entry TLB Entry index. |
205 | * @param entry TLB Entry index. |
191 | * @param value Value to be written. |
206 | * @param value Value to be written. |
192 | */ |
207 | */ |
193 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
208 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
194 | { |
209 | { |
195 | tlb_data_access_addr_t reg; |
210 | tlb_data_access_addr_t reg; |
196 | 211 | ||
197 | reg.value = 0; |
212 | reg.value = 0; |
198 | reg.tlb_entry = entry; |
213 | reg.tlb_entry = entry; |
199 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
214 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
200 | flush(); |
215 | flush(); |
201 | } |
216 | } |
202 | 217 | ||
203 | /** Read DMMU TLB Data Access Register. |
218 | /** Read DMMU TLB Data Access Register. |
204 | * |
219 | * |
205 | * @param entry TLB Entry index. |
220 | * @param entry TLB Entry index. |
206 | * |
221 | * |
207 | * @return Current value of specified DMMU TLB Data Access Register. |
222 | * @return Current value of specified DMMU TLB Data Access Register. |
208 | */ |
223 | */ |
209 | static inline uint64_t dtlb_data_access_read(index_t entry) |
224 | static inline uint64_t dtlb_data_access_read(index_t entry) |
210 | { |
225 | { |
211 | tlb_data_access_addr_t reg; |
226 | tlb_data_access_addr_t reg; |
212 | 227 | ||
213 | reg.value = 0; |
228 | reg.value = 0; |
214 | reg.tlb_entry = entry; |
229 | reg.tlb_entry = entry; |
215 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
230 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
216 | } |
231 | } |
217 | 232 | ||
218 | /** Write DMMU TLB Data Access Register. |
233 | /** Write DMMU TLB Data Access Register. |
219 | * |
234 | * |
220 | * @param entry TLB Entry index. |
235 | * @param entry TLB Entry index. |
221 | * @param value Value to be written. |
236 | * @param value Value to be written. |
222 | */ |
237 | */ |
223 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
238 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
224 | { |
239 | { |
225 | tlb_data_access_addr_t reg; |
240 | tlb_data_access_addr_t reg; |
226 | 241 | ||
227 | reg.value = 0; |
242 | reg.value = 0; |
228 | reg.tlb_entry = entry; |
243 | reg.tlb_entry = entry; |
229 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
244 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
230 | membar(); |
245 | membar(); |
231 | } |
246 | } |
232 | 247 | ||
233 | /** Read IMMU TLB Tag Read Register. |
248 | /** Read IMMU TLB Tag Read Register. |
234 | * |
249 | * |
235 | * @param entry TLB Entry index. |
250 | * @param entry TLB Entry index. |
236 | * |
251 | * |
237 | * @return Current value of specified IMMU TLB Tag Read Register. |
252 | * @return Current value of specified IMMU TLB Tag Read Register. |
238 | */ |
253 | */ |
239 | static inline uint64_t itlb_tag_read_read(index_t entry) |
254 | static inline uint64_t itlb_tag_read_read(index_t entry) |
240 | { |
255 | { |
241 | tlb_tag_read_addr_t tag; |
256 | tlb_tag_read_addr_t tag; |
242 | 257 | ||
243 | tag.value = 0; |
258 | tag.value = 0; |
244 | tag.tlb_entry = entry; |
259 | tag.tlb_entry = entry; |
245 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
260 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
246 | } |
261 | } |
247 | 262 | ||
248 | /** Read DMMU TLB Tag Read Register. |
263 | /** Read DMMU TLB Tag Read Register. |
249 | * |
264 | * |
250 | * @param entry TLB Entry index. |
265 | * @param entry TLB Entry index. |
251 | * |
266 | * |
252 | * @return Current value of specified DMMU TLB Tag Read Register. |
267 | * @return Current value of specified DMMU TLB Tag Read Register. |
253 | */ |
268 | */ |
254 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
269 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
255 | { |
270 | { |
256 | tlb_tag_read_addr_t tag; |
271 | tlb_tag_read_addr_t tag; |
257 | 272 | ||
258 | tag.value = 0; |
273 | tag.value = 0; |
259 | tag.tlb_entry = entry; |
274 | tag.tlb_entry = entry; |
260 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
275 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
261 | } |
276 | } |
262 | 277 | ||
263 | /** Write IMMU TLB Tag Access Register. |
278 | /** Write IMMU TLB Tag Access Register. |
264 | * |
279 | * |
265 | * @param v Value to be written. |
280 | * @param v Value to be written. |
266 | */ |
281 | */ |
267 | static inline void itlb_tag_access_write(uint64_t v) |
282 | static inline void itlb_tag_access_write(uint64_t v) |
268 | { |
283 | { |
269 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
284 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
270 | flush(); |
285 | flush(); |
271 | } |
286 | } |
272 | 287 | ||
273 | /** Read IMMU TLB Tag Access Register. |
288 | /** Read IMMU TLB Tag Access Register. |
274 | * |
289 | * |
275 | * @return Current value of IMMU TLB Tag Access Register. |
290 | * @return Current value of IMMU TLB Tag Access Register. |
276 | */ |
291 | */ |
277 | static inline uint64_t itlb_tag_access_read(void) |
292 | static inline uint64_t itlb_tag_access_read(void) |
278 | { |
293 | { |
279 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
294 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
280 | } |
295 | } |
281 | 296 | ||
282 | /** Write DMMU TLB Tag Access Register. |
297 | /** Write DMMU TLB Tag Access Register. |
283 | * |
298 | * |
284 | * @param v Value to be written. |
299 | * @param v Value to be written. |
285 | */ |
300 | */ |
286 | static inline void dtlb_tag_access_write(uint64_t v) |
301 | static inline void dtlb_tag_access_write(uint64_t v) |
287 | { |
302 | { |
288 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
303 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
289 | membar(); |
304 | membar(); |
290 | } |
305 | } |
291 | 306 | ||
292 | /** Read DMMU TLB Tag Access Register. |
307 | /** Read DMMU TLB Tag Access Register. |
293 | * |
308 | * |
294 | * @return Current value of DMMU TLB Tag Access Register. |
309 | * @return Current value of DMMU TLB Tag Access Register. |
295 | */ |
310 | */ |
296 | static inline uint64_t dtlb_tag_access_read(void) |
311 | static inline uint64_t dtlb_tag_access_read(void) |
297 | { |
312 | { |
298 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
313 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
299 | } |
314 | } |
300 | 315 | ||
301 | 316 | ||
302 | /** Write IMMU TLB Data in Register. |
317 | /** Write IMMU TLB Data in Register. |
303 | * |
318 | * |
304 | * @param v Value to be written. |
319 | * @param v Value to be written. |
305 | */ |
320 | */ |
306 | static inline void itlb_data_in_write(uint64_t v) |
321 | static inline void itlb_data_in_write(uint64_t v) |
307 | { |
322 | { |
308 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
323 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
309 | flush(); |
324 | flush(); |
310 | } |
325 | } |
311 | 326 | ||
312 | /** Write DMMU TLB Data in Register. |
327 | /** Write DMMU TLB Data in Register. |
313 | * |
328 | * |
314 | * @param v Value to be written. |
329 | * @param v Value to be written. |
315 | */ |
330 | */ |
316 | static inline void dtlb_data_in_write(uint64_t v) |
331 | static inline void dtlb_data_in_write(uint64_t v) |
317 | { |
332 | { |
318 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
333 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
319 | membar(); |
334 | membar(); |
320 | } |
335 | } |
321 | 336 | ||
322 | /** Read ITLB Synchronous Fault Status Register. |
337 | /** Read ITLB Synchronous Fault Status Register. |
323 | * |
338 | * |
324 | * @return Current content of I-SFSR register. |
339 | * @return Current content of I-SFSR register. |
325 | */ |
340 | */ |
326 | static inline uint64_t itlb_sfsr_read(void) |
341 | static inline uint64_t itlb_sfsr_read(void) |
327 | { |
342 | { |
328 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
343 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
329 | } |
344 | } |
330 | 345 | ||
331 | /** Write ITLB Synchronous Fault Status Register. |
346 | /** Write ITLB Synchronous Fault Status Register. |
332 | * |
347 | * |
333 | * @param v New value of I-SFSR register. |
348 | * @param v New value of I-SFSR register. |
334 | */ |
349 | */ |
335 | static inline void itlb_sfsr_write(uint64_t v) |
350 | static inline void itlb_sfsr_write(uint64_t v) |
336 | { |
351 | { |
337 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
352 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
338 | flush(); |
353 | flush(); |
339 | } |
354 | } |
340 | 355 | ||
341 | /** Read DTLB Synchronous Fault Status Register. |
356 | /** Read DTLB Synchronous Fault Status Register. |
342 | * |
357 | * |
343 | * @return Current content of D-SFSR register. |
358 | * @return Current content of D-SFSR register. |
344 | */ |
359 | */ |
345 | static inline uint64_t dtlb_sfsr_read(void) |
360 | static inline uint64_t dtlb_sfsr_read(void) |
346 | { |
361 | { |
347 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
362 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
348 | } |
363 | } |
349 | 364 | ||
350 | /** Write DTLB Synchronous Fault Status Register. |
365 | /** Write DTLB Synchronous Fault Status Register. |
351 | * |
366 | * |
352 | * @param v New value of D-SFSR register. |
367 | * @param v New value of D-SFSR register. |
353 | */ |
368 | */ |
354 | static inline void dtlb_sfsr_write(uint64_t v) |
369 | static inline void dtlb_sfsr_write(uint64_t v) |
355 | { |
370 | { |
356 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
371 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
357 | membar(); |
372 | membar(); |
358 | } |
373 | } |
359 | 374 | ||
360 | /** Read DTLB Synchronous Fault Address Register. |
375 | /** Read DTLB Synchronous Fault Address Register. |
361 | * |
376 | * |
362 | * @return Current content of D-SFAR register. |
377 | * @return Current content of D-SFAR register. |
363 | */ |
378 | */ |
364 | static inline uint64_t dtlb_sfar_read(void) |
379 | static inline uint64_t dtlb_sfar_read(void) |
365 | { |
380 | { |
366 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
381 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
367 | } |
382 | } |
368 | 383 | ||
369 | /** Perform IMMU TLB Demap Operation. |
384 | /** Perform IMMU TLB Demap Operation. |
370 | * |
385 | * |
371 | * @param type Selects between context and page demap. |
386 | * @param type Selects between context and page demap. |
372 | * @param context_encoding Specifies which Context register has Context ID for demap. |
387 | * @param context_encoding Specifies which Context register has Context ID for demap. |
373 | * @param page Address which is on the page to be demapped. |
388 | * @param page Address which is on the page to be demapped. |
374 | */ |
389 | */ |
375 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
390 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
376 | { |
391 | { |
377 | tlb_demap_addr_t da; |
392 | tlb_demap_addr_t da; |
378 | page_address_t pg; |
393 | page_address_t pg; |
379 | 394 | ||
380 | da.value = 0; |
395 | da.value = 0; |
381 | pg.address = page; |
396 | pg.address = page; |
382 | 397 | ||
383 | da.type = type; |
398 | da.type = type; |
384 | da.context = context_encoding; |
399 | da.context = context_encoding; |
385 | da.vpn = pg.vpn; |
400 | da.vpn = pg.vpn; |
386 | 401 | ||
387 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
402 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
388 | flush(); |
403 | flush(); |
389 | } |
404 | } |
390 | 405 | ||
391 | /** Perform DMMU TLB Demap Operation. |
406 | /** Perform DMMU TLB Demap Operation. |
392 | * |
407 | * |
393 | * @param type Selects between context and page demap. |
408 | * @param type Selects between context and page demap. |
394 | * @param context_encoding Specifies which Context register has Context ID for demap. |
409 | * @param context_encoding Specifies which Context register has Context ID for demap. |
395 | * @param page Address which is on the page to be demapped. |
410 | * @param page Address which is on the page to be demapped. |
396 | */ |
411 | */ |
397 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
412 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
398 | { |
413 | { |
399 | tlb_demap_addr_t da; |
414 | tlb_demap_addr_t da; |
400 | page_address_t pg; |
415 | page_address_t pg; |
401 | 416 | ||
402 | da.value = 0; |
417 | da.value = 0; |
403 | pg.address = page; |
418 | pg.address = page; |
404 | 419 | ||
405 | da.type = type; |
420 | da.type = type; |
406 | da.context = context_encoding; |
421 | da.context = context_encoding; |
407 | da.vpn = pg.vpn; |
422 | da.vpn = pg.vpn; |
408 | 423 | ||
409 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
424 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */ |
410 | membar(); |
425 | membar(); |
411 | } |
426 | } |
412 | 427 | ||
413 | extern void fast_instruction_access_mmu_miss(void); |
428 | extern void fast_instruction_access_mmu_miss(void); |
414 | extern void fast_data_access_mmu_miss(void); |
429 | extern void fast_data_access_mmu_miss(void); |
415 | extern void fast_data_access_protection(void); |
430 | extern void fast_data_access_protection(void); |
416 | 431 | ||
417 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
432 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
418 | 433 | ||
- | 434 | #endif /* !def __ASM__ */ |
|
- | 435 | ||
419 | #endif |
436 | #endif |
420 | 437 | ||
421 | /** @} |
438 | /** @} |
422 | */ |
439 | */ |
423 | 440 |