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/*
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/*
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 * Copyright (C) 2005 Jakub Jermar
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64
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/** @addtogroup sparc64
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#ifndef KERN_sparc64_BARRIER_H_
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#ifndef KERN_sparc64_BARRIER_H_
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#define KERN_sparc64_BARRIER_H_
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#define KERN_sparc64_BARRIER_H_
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/*
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/*
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 * We assume TSO memory model in which only reads can pass earlier stores
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 * Our critical section barriers are prepared for the weakest RMO memory model.
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 * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER()
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 * can be empty.
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 */
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 */
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#define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define CS_ENTER_BARRIER()              \
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    __asm__ volatile (              \
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        "membar #LoadLoad | #LoadStore\n"   \
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        ::: "memory"                \
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    )
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#define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()              \
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    __asm__ volatile (              \
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        "membar #StoreStore\n"          \
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        "membar #LoadStore\n"           \
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        ::: "memory"                \
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    )
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#define memory_barrier()    \
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#define memory_barrier()    __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
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    __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
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#define read_barrier()      \
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#define read_barrier()      __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
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    __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
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#define write_barrier()     \
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#define write_barrier()     __asm__ volatile ("membar #StoreStore\n" ::: "memory")
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    __asm__ volatile ("membar #StoreStore\n" ::: "memory")
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/** Flush Instruction Memory instruction. */
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/** Flush Instruction Memory instruction. */
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static inline void flush(void)
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static inline void flush(void)
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{
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{
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    /*
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    /*
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     * The FLUSH instruction takes address parameter.
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     * The FLUSH instruction takes address parameter.
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     * As such, it may trap if the address is not found in DTLB.
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     * As such, it may trap if the address is not found in DTLB.
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     *
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     *
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     * The entire kernel text is mapped by a locked ITLB and
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     * The entire kernel text is mapped by a locked ITLB and
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     * DTLB entries. Therefore, when this function is called,
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     * DTLB entries. Therefore, when this function is called,
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     * the %o7 register will always be in the range mapped by
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     * the %o7 register will always be in the range mapped by
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     * DTLB.
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     * DTLB.
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     */
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     */
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        __asm__ volatile ("flush %o7\n");
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        __asm__ volatile ("flush %o7\n");
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}
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}
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/** Memory Barrier instruction. */
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/** Memory Barrier instruction. */
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static inline void membar(void)
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static inline void membar(void)
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{
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{
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    __asm__ volatile ("membar #Sync\n");
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    __asm__ volatile ("membar #Sync\n");
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}
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}
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */
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