WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
 
 
 
static inline void outb(ioport_t port, uint8_t v)
{
    *((volatile uint8_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outw(ioport_t port, uint16_t v)
{
    *((volatile uint16_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outl(ioport_t port, uint32_t v)
{
    *((volatile uint32_t *)(port)) = v;
    memory_barrier();
}
 
 
 
static inline uint8_t inb(ioport_t port)
{
    uint8_t rv;
 
    rv = *((volatile uint8_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint16_t inw(ioport_t port)
{
    uint16_t rv;
 
    rv = *((volatile uint16_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint32_t inl(ioport_t port)
{
    uint32_t rv;
 
 
 
 
    rv = *((volatile uint32_t *)(port));
    memory_barrier();
 
    return rv;
}
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
/** Read UPA_CONFIG register.
 *
 * @return Value of the UPA_CONFIG register.
 */
static inline uint64_t upa_config_read(void)
{
    return asi_u64_read(ASI_UPA_CONFIG, 0);
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Rev 3577	Rev 3580
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <typedefs.h>	40	#include <typedefs.h>
41	#include <align.h>	41	#include <align.h>
42	#include <arch/register.h>	42	#include <arch/register.h>
43	#include <config.h>	43	#include <config.h>
44	#include <arch/stack.h>	44	#include <arch/stack.h>
-		45	#include <arch/barrier.h>
45		46
46	typedef uint64_t ioport_t;	-
47		-
48		-
49	static inline void outb(ioport_t port,uint8_t v)	47	static inline void outb(ioport_t port, uint8_t v)
50	{	48	{
51	((uint8_t )(port)) = v;	49	((volatile uint8_t )(port)) = v;
-		50	memory_barrier();
52	}	51	}
53		52
54	static inline void outw(ioport_t port,uint16_t v)	53	static inline void outw(ioport_t port, uint16_t v)
55	{	54	{
56	((uint16_t )(port)) = v;	55	((volatile uint16_t )(port)) = v;
-		56	memory_barrier();
57	}	57	}
58		58
59	static inline void outl(ioport_t port,uint32_t v)	59	static inline void outl(ioport_t port, uint32_t v)
60	{	60	{
61	((uint32_t )(port)) = v;	61	((volatile uint32_t )(port)) = v;
-		62	memory_barrier();
62	}	63	}
63		64
64		-
65		-
66	static inline uint8_t inb(ioport_t port)	65	static inline uint8_t inb(ioport_t port)
67	{	66	{
-		67	uint8_t rv;
-		68
68	return ((uint8_t )(port));	69	rv = ((volatile uint8_t )(port));
-		70	memory_barrier();
-		71
-		72	return rv;
69	}	73	}
70		74
71	static inline uint16_t inw(ioport_t port)	75	static inline uint16_t inw(ioport_t port)
72	{	76	{
-		77	uint16_t rv;
-		78
73	return ((uint16_t )(port));	79	rv = ((volatile uint16_t )(port));
-		80	memory_barrier();
-		81
-		82	return rv;
74	}	83	}
75		84
76	static inline uint32_t inl(ioport_t port)	85	static inline uint32_t inl(ioport_t port)
77	{	86	{
78	return ((uint32_t )(port));	87	uint32_t rv;
79	}	-
80		-
81		-
82		88
-		89	rv = ((volatile uint32_t )(port));
-		90	memory_barrier();
83		91
-		92	return rv;
-		93	}
84		94
85	/** Read Processor State register.	95	/** Read Processor State register.
86	*	96	*
87	* @return Value of PSTATE register.	97	* @return Value of PSTATE register.
88	*/	98	*/
89	static inline uint64_t pstate_read(void)	99	static inline uint64_t pstate_read(void)
90	{	100	{
91	uint64_t v;	101	uint64_t v;
92		102
93	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
94		104
95	return v;	105	return v;
96	}	106	}
97		107
98	/** Write Processor State register.	108	/** Write Processor State register.
99	*	109	*
100	* @param v New value of PSTATE register.	110	* @param v New value of PSTATE register.
101	*/	111	*/
102	static inline void pstate_write(uint64_t v)	112	static inline void pstate_write(uint64_t v)
103	{	113	{
104	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
105	}	115	}
106		116
107	/** Read TICK_compare Register.	117	/** Read TICK_compare Register.
108	*	118	*
109	* @return Value of TICK_comapre register.	119	* @return Value of TICK_comapre register.
110	*/	120	*/
111	static inline uint64_t tick_compare_read(void)	121	static inline uint64_t tick_compare_read(void)
112	{	122	{
113	uint64_t v;	123	uint64_t v;
114		124
115	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
116		126
117	return v;	127	return v;
118	}	128	}
119		129
120	/** Write TICK_compare Register.	130	/** Write TICK_compare Register.
121	*	131	*
122	* @param v New value of TICK_comapre register.	132	* @param v New value of TICK_comapre register.
123	*/	133	*/
124	static inline void tick_compare_write(uint64_t v)	134	static inline void tick_compare_write(uint64_t v)
125	{	135	{
126	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
127	}	137	}
128		138
129	/** Read TICK Register.	139	/** Read TICK Register.
130	*	140	*
131	* @return Value of TICK register.	141	* @return Value of TICK register.
132	*/	142	*/
133	static inline uint64_t tick_read(void)	143	static inline uint64_t tick_read(void)
134	{	144	{
135	uint64_t v;	145	uint64_t v;
136		146
137	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	147	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
138		148
139	return v;	149	return v;
140	}	150	}
141		151
142	/** Write TICK Register.	152	/** Write TICK Register.
143	*	153	*
144	* @param v New value of TICK register.	154	* @param v New value of TICK register.
145	*/	155	*/
146	static inline void tick_write(uint64_t v)	156	static inline void tick_write(uint64_t v)
147	{	157	{
148	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	158	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
149	}	159	}
150		160
151	/** Read FPRS Register.	161	/** Read FPRS Register.
152	*	162	*
153	* @return Value of FPRS register.	163	* @return Value of FPRS register.
154	*/	164	*/
155	static inline uint64_t fprs_read(void)	165	static inline uint64_t fprs_read(void)
156	{	166	{
157	uint64_t v;	167	uint64_t v;
158		168
159	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	169	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
160		170
161	return v;	171	return v;
162	}	172	}
163		173
164	/** Write FPRS Register.	174	/** Write FPRS Register.
165	*	175	*
166	* @param v New value of FPRS register.	176	* @param v New value of FPRS register.
167	*/	177	*/
168	static inline void fprs_write(uint64_t v)	178	static inline void fprs_write(uint64_t v)
169	{	179	{
170	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	180	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
171	}	181	}
172		182
173	/** Read SOFTINT Register.	183	/** Read SOFTINT Register.
174	*	184	*
175	* @return Value of SOFTINT register.	185	* @return Value of SOFTINT register.
176	*/	186	*/
177	static inline uint64_t softint_read(void)	187	static inline uint64_t softint_read(void)
178	{	188	{
179	uint64_t v;	189	uint64_t v;
180		190
181	asm volatile ("rd %%softint, %0\n" : "=r" (v));	191	asm volatile ("rd %%softint, %0\n" : "=r" (v));
182		192
183	return v;	193	return v;
184	}	194	}
185		195
186	/** Write SOFTINT Register.	196	/** Write SOFTINT Register.
187	*	197	*
188	* @param v New value of SOFTINT register.	198	* @param v New value of SOFTINT register.
189	*/	199	*/
190	static inline void softint_write(uint64_t v)	200	static inline void softint_write(uint64_t v)
191	{	201	{
192	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	202	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
193	}	203	}
194		204
195	/** Write CLEAR_SOFTINT Register.	205	/** Write CLEAR_SOFTINT Register.
196	*	206	*
197	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	207	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
198	*	208	*
199	* @param v New value of CLEAR_SOFTINT register.	209	* @param v New value of CLEAR_SOFTINT register.
200	*/	210	*/
201	static inline void clear_softint_write(uint64_t v)	211	static inline void clear_softint_write(uint64_t v)
202	{	212	{
203	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	213	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
204	}	214	}
205		215
206	/** Write SET_SOFTINT Register.	216	/** Write SET_SOFTINT Register.
207	*	217	*
208	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	218	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
209	*	219	*
210	* @param v New value of SET_SOFTINT register.	220	* @param v New value of SET_SOFTINT register.
211	*/	221	*/
212	static inline void set_softint_write(uint64_t v)	222	static inline void set_softint_write(uint64_t v)
213	{	223	{
214	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	224	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
215	}	225	}
216		226
217	/** Enable interrupts.	227	/** Enable interrupts.
218	*	228	*
219	* Enable interrupts and return previous	229	* Enable interrupts and return previous
220	* value of IPL.	230	* value of IPL.
221	*	231	*
222	* @return Old interrupt priority level.	232	* @return Old interrupt priority level.
223	*/	233	*/
224	static inline ipl_t interrupts_enable(void) {	234	static inline ipl_t interrupts_enable(void) {
225	pstate_reg_t pstate;	235	pstate_reg_t pstate;
226	uint64_t value;	236	uint64_t value;
227		237
228	value = pstate_read();	238	value = pstate_read();
229	pstate.value = value;	239	pstate.value = value;
230	pstate.ie = true;	240	pstate.ie = true;
231	pstate_write(pstate.value);	241	pstate_write(pstate.value);
232		242
233	return (ipl_t) value;	243	return (ipl_t) value;
234	}	244	}
235		245
236	/** Disable interrupts.	246	/** Disable interrupts.
237	*	247	*
238	* Disable interrupts and return previous	248	* Disable interrupts and return previous
239	* value of IPL.	249	* value of IPL.
240	*	250	*
241	* @return Old interrupt priority level.	251	* @return Old interrupt priority level.
242	*/	252	*/
243	static inline ipl_t interrupts_disable(void) {	253	static inline ipl_t interrupts_disable(void) {
244	pstate_reg_t pstate;	254	pstate_reg_t pstate;
245	uint64_t value;	255	uint64_t value;
246		256
247	value = pstate_read();	257	value = pstate_read();
248	pstate.value = value;	258	pstate.value = value;
249	pstate.ie = false;	259	pstate.ie = false;
250	pstate_write(pstate.value);	260	pstate_write(pstate.value);
251		261
252	return (ipl_t) value;	262	return (ipl_t) value;
253	}	263	}
254		264
255	/** Restore interrupt priority level.	265	/** Restore interrupt priority level.
256	*	266	*
257	* Restore IPL.	267	* Restore IPL.
258	*	268	*
259	* @param ipl Saved interrupt priority level.	269	* @param ipl Saved interrupt priority level.
260	*/	270	*/
261	static inline void interrupts_restore(ipl_t ipl) {	271	static inline void interrupts_restore(ipl_t ipl) {
262	pstate_reg_t pstate;	272	pstate_reg_t pstate;
263		273
264	pstate.value = pstate_read();	274	pstate.value = pstate_read();
265	pstate.ie = ((pstate_reg_t) ipl).ie;	275	pstate.ie = ((pstate_reg_t) ipl).ie;
266	pstate_write(pstate.value);	276	pstate_write(pstate.value);
267	}	277	}
268		278
269	/** Return interrupt priority level.	279	/** Return interrupt priority level.
270	*	280	*
271	* Return IPL.	281	* Return IPL.
272	*	282	*
273	* @return Current interrupt priority level.	283	* @return Current interrupt priority level.
274	*/	284	*/
275	static inline ipl_t interrupts_read(void) {	285	static inline ipl_t interrupts_read(void) {
276	return (ipl_t) pstate_read();	286	return (ipl_t) pstate_read();
277	}	287	}
278		288
279	/** Return base address of current stack.	289	/** Return base address of current stack.
280	*	290	*
281	* Return the base address of the current stack.	291	* Return the base address of the current stack.
282	* The stack is assumed to be STACK_SIZE bytes long.	292	* The stack is assumed to be STACK_SIZE bytes long.
283	* The stack must start on page boundary.	293	* The stack must start on page boundary.
284	*/	294	*/
285	static inline uintptr_t get_stack_base(void)	295	static inline uintptr_t get_stack_base(void)
286	{	296	{
287	uintptr_t unbiased_sp;	297	uintptr_t unbiased_sp;
288		298
289	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	299	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
290		300
291	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	301	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
292	}	302	}
293		303
294	/** Read Version Register.	304	/** Read Version Register.
295	*	305	*
296	* @return Value of VER register.	306	* @return Value of VER register.
297	*/	307	*/
298	static inline uint64_t ver_read(void)	308	static inline uint64_t ver_read(void)
299	{	309	{
300	uint64_t v;	310	uint64_t v;
301		311
302	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	312	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
303		313
304	return v;	314	return v;
305	}	315	}
306		316
307	/** Read Trap Program Counter register.	317	/** Read Trap Program Counter register.
308	*	318	*
309	* @return Current value in TPC.	319	* @return Current value in TPC.
310	*/	320	*/
311	static inline uint64_t tpc_read(void)	321	static inline uint64_t tpc_read(void)
312	{	322	{
313	uint64_t v;	323	uint64_t v;
314		324
315	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	325	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
316		326
317	return v;	327	return v;
318	}	328	}
319		329
320	/** Read Trap Level register.	330	/** Read Trap Level register.
321	*	331	*
322	* @return Current value in TL.	332	* @return Current value in TL.
323	*/	333	*/
324	static inline uint64_t tl_read(void)	334	static inline uint64_t tl_read(void)
325	{	335	{
326	uint64_t v;	336	uint64_t v;
327		337
328	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	338	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
329		339
330	return v;	340	return v;
331	}	341	}
332		342
333	/** Read Trap Base Address register.	343	/** Read Trap Base Address register.
334	*	344	*
335	* @return Current value in TBA.	345	* @return Current value in TBA.
336	*/	346	*/
337	static inline uint64_t tba_read(void)	347	static inline uint64_t tba_read(void)
338	{	348	{
339	uint64_t v;	349	uint64_t v;
340		350
341	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	351	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
342		352
343	return v;	353	return v;
344	}	354	}
345		355
346	/** Write Trap Base Address register.	356	/** Write Trap Base Address register.
347	*	357	*
348	* @param v New value of TBA.	358	* @param v New value of TBA.
349	*/	359	*/
350	static inline void tba_write(uint64_t v)	360	static inline void tba_write(uint64_t v)
351	{	361	{
352	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	362	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
353	}	363	}
354		364
355	/** Load uint64_t from alternate space.	365	/** Load uint64_t from alternate space.
356	*	366	*
357	* @param asi ASI determining the alternate space.	367	* @param asi ASI determining the alternate space.
358	* @param va Virtual address within the ASI.	368	* @param va Virtual address within the ASI.
359	*	369	*
360	* @return Value read from the virtual address in the specified address space.	370	* @return Value read from the virtual address in the specified address space.
361	*/	371	*/
362	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	372	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
363	{	373	{
364	uint64_t v;	374	uint64_t v;
365		375
366	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	376	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
367		377
368	return v;	378	return v;
369	}	379	}
370		380
371	/** Store uint64_t to alternate space.	381	/** Store uint64_t to alternate space.
372	*	382	*
373	* @param asi ASI determining the alternate space.	383	* @param asi ASI determining the alternate space.
374	* @param va Virtual address within the ASI.	384	* @param va Virtual address within the ASI.
375	* @param v Value to be written.	385	* @param v Value to be written.
376	*/	386	*/
377	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	387	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
378	{	388	{
379	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	389	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
380	}	390	}
381		391
382	/** Flush all valid register windows to memory. */	392	/** Flush all valid register windows to memory. */
383	static inline void flushw(void)	393	static inline void flushw(void)
384	{	394	{
385	asm volatile ("flushw\n");	395	asm volatile ("flushw\n");
386	}	396	}
387		397
388	/** Switch to nucleus by setting TL to 1. */	398	/** Switch to nucleus by setting TL to 1. */
389	static inline void nucleus_enter(void)	399	static inline void nucleus_enter(void)
390	{	400	{
391	asm volatile ("wrpr %g0, 1, %tl\n");	401	asm volatile ("wrpr %g0, 1, %tl\n");
392	}	402	}
393		403
394	/** Switch from nucleus by setting TL to 0. */	404	/** Switch from nucleus by setting TL to 0. */
395	static inline void nucleus_leave(void)	405	static inline void nucleus_leave(void)
396	{	406	{
397	asm volatile ("wrpr %g0, %g0, %tl\n");	407	asm volatile ("wrpr %g0, %g0, %tl\n");
398	}	408	}
399		409
400	/** Read UPA_CONFIG register.	410	/** Read UPA_CONFIG register.
401	*	411	*
402	* @return Value of the UPA_CONFIG register.	412	* @return Value of the UPA_CONFIG register.
403	*/	413	*/
404	static inline uint64_t upa_config_read(void)	414	static inline uint64_t upa_config_read(void)
405	{	415	{
406	return asi_u64_read(ASI_UPA_CONFIG, 0);	416	return asi_u64_read(ASI_UPA_CONFIG, 0);
407	}	417	}
408		418
409	extern void cpu_halt(void);	419	extern void cpu_halt(void);
410	extern void cpu_sleep(void);	420	extern void cpu_sleep(void);
411	extern void asm_delay_loop(const uint32_t usec);	421	extern void asm_delay_loop(const uint32_t usec);
412		422
413	extern uint64_t read_from_ag_g7(void);	423	extern uint64_t read_from_ag_g7(void);
414	extern void write_to_ag_g6(uint64_t val);	424	extern void write_to_ag_g6(uint64_t val);
415	extern void write_to_ag_g7(uint64_t val);	425	extern void write_to_ag_g7(uint64_t val);
416	extern void write_to_ig_g6(uint64_t val);	426	extern void write_to_ig_g6(uint64_t val);
417		427
418	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	428	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
419		429
420	#endif	430	#endif
421		431
422	/** @}	432	/** @}
423	*/	433	*/
424		434

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(root)/trunk/kernel/arch/sparc64/include/asm.h @ 3672 – Rev 3577 → 3580