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1 | /* |
1 | /* |
2 | * Copyright (c) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_ASM_H_ |
35 | #ifndef KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
37 | 37 | ||
38 | #include <arch/arch.h> |
38 | #include <arch/arch.h> |
39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
40 | #include <typedefs.h> |
40 | #include <typedefs.h> |
41 | #include <align.h> |
41 | #include <align.h> |
42 | #include <arch/register.h> |
42 | #include <arch/register.h> |
43 | #include <config.h> |
43 | #include <config.h> |
44 | #include <arch/stack.h> |
44 | #include <arch/stack.h> |
45 | 45 | ||
- | 46 | typedef uint64_t ioport_t; |
|
- | 47 | ||
- | 48 | ||
- | 49 | static inline void outb(ioport_t port,uint8_t v) |
|
- | 50 | { |
|
- | 51 | *((uint8_t *)(port)) = v; |
|
- | 52 | } |
|
- | 53 | ||
- | 54 | static inline void outw(ioport_t port,uint16_t v) |
|
- | 55 | { |
|
- | 56 | *((uint16_t *)(port)) = v; |
|
- | 57 | } |
|
- | 58 | ||
- | 59 | static inline void outl(ioport_t port,uint32_t v) |
|
- | 60 | { |
|
- | 61 | *((uint32_t *)(port)) = v; |
|
- | 62 | } |
|
- | 63 | ||
- | 64 | ||
- | 65 | ||
- | 66 | static inline uint8_t inb(ioport_t port) |
|
- | 67 | { |
|
- | 68 | return *((uint8_t *)(port)); |
|
- | 69 | } |
|
- | 70 | ||
- | 71 | static inline uint16_t inw(ioport_t port) |
|
- | 72 | { |
|
- | 73 | return *((uint16_t *)(port)); |
|
- | 74 | } |
|
- | 75 | ||
- | 76 | static inline uint32_t inl(ioport_t port) |
|
- | 77 | { |
|
- | 78 | return *((uint32_t *)(port)); |
|
- | 79 | } |
|
- | 80 | ||
- | 81 | ||
- | 82 | ||
- | 83 | ||
- | 84 | ||
46 | /** Read Processor State register. |
85 | /** Read Processor State register. |
47 | * |
86 | * |
48 | * @return Value of PSTATE register. |
87 | * @return Value of PSTATE register. |
49 | */ |
88 | */ |
50 | static inline uint64_t pstate_read(void) |
89 | static inline uint64_t pstate_read(void) |
51 | { |
90 | { |
52 | uint64_t v; |
91 | uint64_t v; |
53 | 92 | ||
54 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
93 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
55 | 94 | ||
56 | return v; |
95 | return v; |
57 | } |
96 | } |
58 | 97 | ||
59 | /** Write Processor State register. |
98 | /** Write Processor State register. |
60 | * |
99 | * |
61 | * @param v New value of PSTATE register. |
100 | * @param v New value of PSTATE register. |
62 | */ |
101 | */ |
63 | static inline void pstate_write(uint64_t v) |
102 | static inline void pstate_write(uint64_t v) |
64 | { |
103 | { |
65 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
104 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
66 | } |
105 | } |
67 | 106 | ||
68 | /** Read TICK_compare Register. |
107 | /** Read TICK_compare Register. |
69 | * |
108 | * |
70 | * @return Value of TICK_comapre register. |
109 | * @return Value of TICK_comapre register. |
71 | */ |
110 | */ |
72 | static inline uint64_t tick_compare_read(void) |
111 | static inline uint64_t tick_compare_read(void) |
73 | { |
112 | { |
74 | uint64_t v; |
113 | uint64_t v; |
75 | 114 | ||
76 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
115 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
77 | 116 | ||
78 | return v; |
117 | return v; |
79 | } |
118 | } |
80 | 119 | ||
81 | /** Write TICK_compare Register. |
120 | /** Write TICK_compare Register. |
82 | * |
121 | * |
83 | * @param v New value of TICK_comapre register. |
122 | * @param v New value of TICK_comapre register. |
84 | */ |
123 | */ |
85 | static inline void tick_compare_write(uint64_t v) |
124 | static inline void tick_compare_write(uint64_t v) |
86 | { |
125 | { |
87 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
126 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
88 | } |
127 | } |
89 | 128 | ||
90 | /** Read TICK Register. |
129 | /** Read TICK Register. |
91 | * |
130 | * |
92 | * @return Value of TICK register. |
131 | * @return Value of TICK register. |
93 | */ |
132 | */ |
94 | static inline uint64_t tick_read(void) |
133 | static inline uint64_t tick_read(void) |
95 | { |
134 | { |
96 | uint64_t v; |
135 | uint64_t v; |
97 | 136 | ||
98 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
137 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
99 | 138 | ||
100 | return v; |
139 | return v; |
101 | } |
140 | } |
102 | 141 | ||
103 | /** Write TICK Register. |
142 | /** Write TICK Register. |
104 | * |
143 | * |
105 | * @param v New value of TICK register. |
144 | * @param v New value of TICK register. |
106 | */ |
145 | */ |
107 | static inline void tick_write(uint64_t v) |
146 | static inline void tick_write(uint64_t v) |
108 | { |
147 | { |
109 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
148 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
110 | } |
149 | } |
111 | 150 | ||
112 | /** Read FPRS Register. |
151 | /** Read FPRS Register. |
113 | * |
152 | * |
114 | * @return Value of FPRS register. |
153 | * @return Value of FPRS register. |
115 | */ |
154 | */ |
116 | static inline uint64_t fprs_read(void) |
155 | static inline uint64_t fprs_read(void) |
117 | { |
156 | { |
118 | uint64_t v; |
157 | uint64_t v; |
119 | 158 | ||
120 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
159 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
121 | 160 | ||
122 | return v; |
161 | return v; |
123 | } |
162 | } |
124 | 163 | ||
125 | /** Write FPRS Register. |
164 | /** Write FPRS Register. |
126 | * |
165 | * |
127 | * @param v New value of FPRS register. |
166 | * @param v New value of FPRS register. |
128 | */ |
167 | */ |
129 | static inline void fprs_write(uint64_t v) |
168 | static inline void fprs_write(uint64_t v) |
130 | { |
169 | { |
131 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
170 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
132 | } |
171 | } |
133 | 172 | ||
134 | /** Read SOFTINT Register. |
173 | /** Read SOFTINT Register. |
135 | * |
174 | * |
136 | * @return Value of SOFTINT register. |
175 | * @return Value of SOFTINT register. |
137 | */ |
176 | */ |
138 | static inline uint64_t softint_read(void) |
177 | static inline uint64_t softint_read(void) |
139 | { |
178 | { |
140 | uint64_t v; |
179 | uint64_t v; |
141 | 180 | ||
142 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
181 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
143 | 182 | ||
144 | return v; |
183 | return v; |
145 | } |
184 | } |
146 | 185 | ||
147 | /** Write SOFTINT Register. |
186 | /** Write SOFTINT Register. |
148 | * |
187 | * |
149 | * @param v New value of SOFTINT register. |
188 | * @param v New value of SOFTINT register. |
150 | */ |
189 | */ |
151 | static inline void softint_write(uint64_t v) |
190 | static inline void softint_write(uint64_t v) |
152 | { |
191 | { |
153 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
192 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
154 | } |
193 | } |
155 | 194 | ||
156 | /** Write CLEAR_SOFTINT Register. |
195 | /** Write CLEAR_SOFTINT Register. |
157 | * |
196 | * |
158 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
197 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
159 | * |
198 | * |
160 | * @param v New value of CLEAR_SOFTINT register. |
199 | * @param v New value of CLEAR_SOFTINT register. |
161 | */ |
200 | */ |
162 | static inline void clear_softint_write(uint64_t v) |
201 | static inline void clear_softint_write(uint64_t v) |
163 | { |
202 | { |
164 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
203 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
165 | } |
204 | } |
166 | 205 | ||
167 | /** Write SET_SOFTINT Register. |
206 | /** Write SET_SOFTINT Register. |
168 | * |
207 | * |
169 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
208 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
170 | * |
209 | * |
171 | * @param v New value of SET_SOFTINT register. |
210 | * @param v New value of SET_SOFTINT register. |
172 | */ |
211 | */ |
173 | static inline void set_softint_write(uint64_t v) |
212 | static inline void set_softint_write(uint64_t v) |
174 | { |
213 | { |
175 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
214 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
176 | } |
215 | } |
177 | 216 | ||
178 | /** Enable interrupts. |
217 | /** Enable interrupts. |
179 | * |
218 | * |
180 | * Enable interrupts and return previous |
219 | * Enable interrupts and return previous |
181 | * value of IPL. |
220 | * value of IPL. |
182 | * |
221 | * |
183 | * @return Old interrupt priority level. |
222 | * @return Old interrupt priority level. |
184 | */ |
223 | */ |
185 | static inline ipl_t interrupts_enable(void) { |
224 | static inline ipl_t interrupts_enable(void) { |
186 | pstate_reg_t pstate; |
225 | pstate_reg_t pstate; |
187 | uint64_t value; |
226 | uint64_t value; |
188 | 227 | ||
189 | value = pstate_read(); |
228 | value = pstate_read(); |
190 | pstate.value = value; |
229 | pstate.value = value; |
191 | pstate.ie = true; |
230 | pstate.ie = true; |
192 | pstate_write(pstate.value); |
231 | pstate_write(pstate.value); |
193 | 232 | ||
194 | return (ipl_t) value; |
233 | return (ipl_t) value; |
195 | } |
234 | } |
196 | 235 | ||
197 | /** Disable interrupts. |
236 | /** Disable interrupts. |
198 | * |
237 | * |
199 | * Disable interrupts and return previous |
238 | * Disable interrupts and return previous |
200 | * value of IPL. |
239 | * value of IPL. |
201 | * |
240 | * |
202 | * @return Old interrupt priority level. |
241 | * @return Old interrupt priority level. |
203 | */ |
242 | */ |
204 | static inline ipl_t interrupts_disable(void) { |
243 | static inline ipl_t interrupts_disable(void) { |
205 | pstate_reg_t pstate; |
244 | pstate_reg_t pstate; |
206 | uint64_t value; |
245 | uint64_t value; |
207 | 246 | ||
208 | value = pstate_read(); |
247 | value = pstate_read(); |
209 | pstate.value = value; |
248 | pstate.value = value; |
210 | pstate.ie = false; |
249 | pstate.ie = false; |
211 | pstate_write(pstate.value); |
250 | pstate_write(pstate.value); |
212 | 251 | ||
213 | return (ipl_t) value; |
252 | return (ipl_t) value; |
214 | } |
253 | } |
215 | 254 | ||
216 | /** Restore interrupt priority level. |
255 | /** Restore interrupt priority level. |
217 | * |
256 | * |
218 | * Restore IPL. |
257 | * Restore IPL. |
219 | * |
258 | * |
220 | * @param ipl Saved interrupt priority level. |
259 | * @param ipl Saved interrupt priority level. |
221 | */ |
260 | */ |
222 | static inline void interrupts_restore(ipl_t ipl) { |
261 | static inline void interrupts_restore(ipl_t ipl) { |
223 | pstate_reg_t pstate; |
262 | pstate_reg_t pstate; |
224 | 263 | ||
225 | pstate.value = pstate_read(); |
264 | pstate.value = pstate_read(); |
226 | pstate.ie = ((pstate_reg_t) ipl).ie; |
265 | pstate.ie = ((pstate_reg_t) ipl).ie; |
227 | pstate_write(pstate.value); |
266 | pstate_write(pstate.value); |
228 | } |
267 | } |
229 | 268 | ||
230 | /** Return interrupt priority level. |
269 | /** Return interrupt priority level. |
231 | * |
270 | * |
232 | * Return IPL. |
271 | * Return IPL. |
233 | * |
272 | * |
234 | * @return Current interrupt priority level. |
273 | * @return Current interrupt priority level. |
235 | */ |
274 | */ |
236 | static inline ipl_t interrupts_read(void) { |
275 | static inline ipl_t interrupts_read(void) { |
237 | return (ipl_t) pstate_read(); |
276 | return (ipl_t) pstate_read(); |
238 | } |
277 | } |
239 | 278 | ||
240 | /** Return base address of current stack. |
279 | /** Return base address of current stack. |
241 | * |
280 | * |
242 | * Return the base address of the current stack. |
281 | * Return the base address of the current stack. |
243 | * The stack is assumed to be STACK_SIZE bytes long. |
282 | * The stack is assumed to be STACK_SIZE bytes long. |
244 | * The stack must start on page boundary. |
283 | * The stack must start on page boundary. |
245 | */ |
284 | */ |
246 | static inline uintptr_t get_stack_base(void) |
285 | static inline uintptr_t get_stack_base(void) |
247 | { |
286 | { |
248 | uintptr_t unbiased_sp; |
287 | uintptr_t unbiased_sp; |
249 | 288 | ||
250 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
289 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
251 | 290 | ||
252 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
291 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
253 | } |
292 | } |
254 | 293 | ||
255 | /** Read Version Register. |
294 | /** Read Version Register. |
256 | * |
295 | * |
257 | * @return Value of VER register. |
296 | * @return Value of VER register. |
258 | */ |
297 | */ |
259 | static inline uint64_t ver_read(void) |
298 | static inline uint64_t ver_read(void) |
260 | { |
299 | { |
261 | uint64_t v; |
300 | uint64_t v; |
262 | 301 | ||
263 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
302 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
264 | 303 | ||
265 | return v; |
304 | return v; |
266 | } |
305 | } |
267 | 306 | ||
268 | /** Read Trap Program Counter register. |
307 | /** Read Trap Program Counter register. |
269 | * |
308 | * |
270 | * @return Current value in TPC. |
309 | * @return Current value in TPC. |
271 | */ |
310 | */ |
272 | static inline uint64_t tpc_read(void) |
311 | static inline uint64_t tpc_read(void) |
273 | { |
312 | { |
274 | uint64_t v; |
313 | uint64_t v; |
275 | 314 | ||
276 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
315 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
277 | 316 | ||
278 | return v; |
317 | return v; |
279 | } |
318 | } |
280 | 319 | ||
281 | /** Read Trap Level register. |
320 | /** Read Trap Level register. |
282 | * |
321 | * |
283 | * @return Current value in TL. |
322 | * @return Current value in TL. |
284 | */ |
323 | */ |
285 | static inline uint64_t tl_read(void) |
324 | static inline uint64_t tl_read(void) |
286 | { |
325 | { |
287 | uint64_t v; |
326 | uint64_t v; |
288 | 327 | ||
289 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
328 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
290 | 329 | ||
291 | return v; |
330 | return v; |
292 | } |
331 | } |
293 | 332 | ||
294 | /** Read Trap Base Address register. |
333 | /** Read Trap Base Address register. |
295 | * |
334 | * |
296 | * @return Current value in TBA. |
335 | * @return Current value in TBA. |
297 | */ |
336 | */ |
298 | static inline uint64_t tba_read(void) |
337 | static inline uint64_t tba_read(void) |
299 | { |
338 | { |
300 | uint64_t v; |
339 | uint64_t v; |
301 | 340 | ||
302 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
341 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
303 | 342 | ||
304 | return v; |
343 | return v; |
305 | } |
344 | } |
306 | 345 | ||
307 | /** Write Trap Base Address register. |
346 | /** Write Trap Base Address register. |
308 | * |
347 | * |
309 | * @param v New value of TBA. |
348 | * @param v New value of TBA. |
310 | */ |
349 | */ |
311 | static inline void tba_write(uint64_t v) |
350 | static inline void tba_write(uint64_t v) |
312 | { |
351 | { |
313 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
352 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
314 | } |
353 | } |
315 | 354 | ||
316 | /** Load uint64_t from alternate space. |
355 | /** Load uint64_t from alternate space. |
317 | * |
356 | * |
318 | * @param asi ASI determining the alternate space. |
357 | * @param asi ASI determining the alternate space. |
319 | * @param va Virtual address within the ASI. |
358 | * @param va Virtual address within the ASI. |
320 | * |
359 | * |
321 | * @return Value read from the virtual address in the specified address space. |
360 | * @return Value read from the virtual address in the specified address space. |
322 | */ |
361 | */ |
323 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
362 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
324 | { |
363 | { |
325 | uint64_t v; |
364 | uint64_t v; |
326 | 365 | ||
327 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
366 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
328 | 367 | ||
329 | return v; |
368 | return v; |
330 | } |
369 | } |
331 | 370 | ||
332 | /** Store uint64_t to alternate space. |
371 | /** Store uint64_t to alternate space. |
333 | * |
372 | * |
334 | * @param asi ASI determining the alternate space. |
373 | * @param asi ASI determining the alternate space. |
335 | * @param va Virtual address within the ASI. |
374 | * @param va Virtual address within the ASI. |
336 | * @param v Value to be written. |
375 | * @param v Value to be written. |
337 | */ |
376 | */ |
338 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
377 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
339 | { |
378 | { |
340 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
379 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
341 | } |
380 | } |
342 | 381 | ||
343 | /** Flush all valid register windows to memory. */ |
382 | /** Flush all valid register windows to memory. */ |
344 | static inline void flushw(void) |
383 | static inline void flushw(void) |
345 | { |
384 | { |
346 | asm volatile ("flushw\n"); |
385 | asm volatile ("flushw\n"); |
347 | } |
386 | } |
348 | 387 | ||
349 | /** Switch to nucleus by setting TL to 1. */ |
388 | /** Switch to nucleus by setting TL to 1. */ |
350 | static inline void nucleus_enter(void) |
389 | static inline void nucleus_enter(void) |
351 | { |
390 | { |
352 | asm volatile ("wrpr %g0, 1, %tl\n"); |
391 | asm volatile ("wrpr %g0, 1, %tl\n"); |
353 | } |
392 | } |
354 | 393 | ||
355 | /** Switch from nucleus by setting TL to 0. */ |
394 | /** Switch from nucleus by setting TL to 0. */ |
356 | static inline void nucleus_leave(void) |
395 | static inline void nucleus_leave(void) |
357 | { |
396 | { |
358 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
397 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
359 | } |
398 | } |
360 | 399 | ||
361 | /** Read UPA_CONFIG register. |
400 | /** Read UPA_CONFIG register. |
362 | * |
401 | * |
363 | * @return Value of the UPA_CONFIG register. |
402 | * @return Value of the UPA_CONFIG register. |
364 | */ |
403 | */ |
365 | static inline uint64_t upa_config_read(void) |
404 | static inline uint64_t upa_config_read(void) |
366 | { |
405 | { |
367 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
406 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
368 | } |
407 | } |
369 | 408 | ||
370 | extern void cpu_halt(void); |
409 | extern void cpu_halt(void); |
371 | extern void cpu_sleep(void); |
410 | extern void cpu_sleep(void); |
372 | extern void asm_delay_loop(const uint32_t usec); |
411 | extern void asm_delay_loop(const uint32_t usec); |
373 | 412 | ||
374 | extern uint64_t read_from_ag_g7(void); |
413 | extern uint64_t read_from_ag_g7(void); |
375 | extern void write_to_ag_g6(uint64_t val); |
414 | extern void write_to_ag_g6(uint64_t val); |
376 | extern void write_to_ag_g7(uint64_t val); |
415 | extern void write_to_ag_g7(uint64_t val); |
377 | extern void write_to_ig_g6(uint64_t val); |
416 | extern void write_to_ig_g6(uint64_t val); |
378 | 417 | ||
379 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
418 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
380 | 419 | ||
381 | #endif |
420 | #endif |
382 | 421 | ||
383 | /** @} |
422 | /** @} |
384 | */ |
423 | */ |
385 | 424 |