WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (C) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch.h>
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
#include <config.h>
#include <time/clock.h>
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    __asm__ volatile ("andn %%sp, %1, %0\n" : "=r" (v) : "r" (STACK_SIZE-1));
   
    return v;
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    __asm__ volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    __asm__ volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    __asm__ volatile ("wrpr %g0, %g0, %tl\n");
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/include/asm.h – Rev 1880 → 1881

Rev 1880		Rev 1881
1	/*	1	/*
2	* Copyright (C) 2005 Jakub Jermar	2	* Copyright (C) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
-		38	#include <arch.h>
38	#include <typedefs.h>	39	#include <typedefs.h>
39	#include <arch/types.h>	40	#include <arch/types.h>
40	#include <arch/register.h>	41	#include <arch/register.h>
41	#include <config.h>	42	#include <config.h>
-		43	#include <time/clock.h>
42		44
43	/** Read Processor State register.	45	/** Read Processor State register.
44	*	46	*
45	* @return Value of PSTATE register.	47	* @return Value of PSTATE register.
46	*/	48	*/
47	static inline uint64_t pstate_read(void)	49	static inline uint64_t pstate_read(void)
48	{	50	{
49	uint64_t v;	51	uint64_t v;
50		52
51	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));	53	__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
52		54
53	return v;	55	return v;
54	}	56	}
55		57
56	/** Write Processor State register.	58	/** Write Processor State register.
57	*	59	*
58	* @param v New value of PSTATE register.	60	* @param v New value of PSTATE register.
59	*/	61	*/
60	static inline void pstate_write(uint64_t v)	62	static inline void pstate_write(uint64_t v)
61	{	63	{
62	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	64	__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
63	}	65	}
64		66
65	/** Read TICK_compare Register.	67	/** Read TICK_compare Register.
66	*	68	*
67	* @return Value of TICK_comapre register.	69	* @return Value of TICK_comapre register.
68	*/	70	*/
69	static inline uint64_t tick_compare_read(void)	71	static inline uint64_t tick_compare_read(void)
70	{	72	{
71	uint64_t v;	73	uint64_t v;
72		74
73	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	75	__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
74		76
75	return v;	77	return v;
76	}	78	}
77		79
78	/** Write TICK_compare Register.	80	/** Write TICK_compare Register.
79	*	81	*
80	* @param v New value of TICK_comapre register.	82	* @param v New value of TICK_comapre register.
81	*/	83	*/
82	static inline void tick_compare_write(uint64_t v)	84	static inline void tick_compare_write(uint64_t v)
83	{	85	{
84	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	86	__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
85	}	87	}
86		88
87	/** Read TICK Register.	89	/** Read TICK Register.
88	*	90	*
89	* @return Value of TICK register.	91	* @return Value of TICK register.
90	*/	92	*/
91	static inline uint64_t tick_read(void)	93	static inline uint64_t tick_read(void)
92	{	94	{
93	uint64_t v;	95	uint64_t v;
94		96
95	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));	97	__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
96		98
97	return v;	99	return v;
98	}	100	}
99		101
100	/** Write TICK Register.	102	/** Write TICK Register.
101	*	103	*
102	* @param v New value of TICK register.	104	* @param v New value of TICK register.
103	*/	105	*/
104	static inline void tick_write(uint64_t v)	106	static inline void tick_write(uint64_t v)
105	{	107	{
106	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	108	__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
107	}	109	}
108		110
109	/** Read SOFTINT Register.	111	/** Read SOFTINT Register.
110	*	112	*
111	* @return Value of SOFTINT register.	113	* @return Value of SOFTINT register.
112	*/	114	*/
113	static inline uint64_t softint_read(void)	115	static inline uint64_t softint_read(void)
114	{	116	{
115	uint64_t v;	117	uint64_t v;
116		118
117	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));	119	__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
118		120
119	return v;	121	return v;
120	}	122	}
121		123
122	/** Write SOFTINT Register.	124	/** Write SOFTINT Register.
123	*	125	*
124	* @param v New value of SOFTINT register.	126	* @param v New value of SOFTINT register.
125	*/	127	*/
126	static inline void softint_write(uint64_t v)	128	static inline void softint_write(uint64_t v)
127	{	129	{
128	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	130	__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
129	}	131	}
130		132
131	/** Write CLEAR_SOFTINT Register.	133	/** Write CLEAR_SOFTINT Register.
132	*	134	*
133	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	135	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
134	*	136	*
135	* @param v New value of CLEAR_SOFTINT register.	137	* @param v New value of CLEAR_SOFTINT register.
136	*/	138	*/
137	static inline void clear_softint_write(uint64_t v)	139	static inline void clear_softint_write(uint64_t v)
138	{	140	{
139	__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	141	__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
140	}	142	}
141		143
142	/** Write SET_SOFTINT Register.	144	/** Write SET_SOFTINT Register.
143	*	145	*
144	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	146	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
145	*	147	*
146	* @param v New value of SET_SOFTINT register.	148	* @param v New value of SET_SOFTINT register.
147	*/	149	*/
148	static inline void set_softint_write(uint64_t v)	150	static inline void set_softint_write(uint64_t v)
149	{	151	{
150	__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	152	__asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
151	}	153	}
152		154
153	/** Enable interrupts.	155	/** Enable interrupts.
154	*	156	*
155	* Enable interrupts and return previous	157	* Enable interrupts and return previous
156	* value of IPL.	158	* value of IPL.
157	*	159	*
158	* @return Old interrupt priority level.	160	* @return Old interrupt priority level.
159	*/	161	*/
160	static inline ipl_t interrupts_enable(void) {	162	static inline ipl_t interrupts_enable(void) {
161	pstate_reg_t pstate;	163	pstate_reg_t pstate;
162	uint64_t value;	164	uint64_t value;
163		165
164	value = pstate_read();	166	value = pstate_read();
165	pstate.value = value;	167	pstate.value = value;
166	pstate.ie = true;	168	pstate.ie = true;
167	pstate_write(pstate.value);	169	pstate_write(pstate.value);
168		170
169	return (ipl_t) value;	171	return (ipl_t) value;
170	}	172	}
171		173
172	/** Disable interrupts.	174	/** Disable interrupts.
173	*	175	*
174	* Disable interrupts and return previous	176	* Disable interrupts and return previous
175	* value of IPL.	177	* value of IPL.
176	*	178	*
177	* @return Old interrupt priority level.	179	* @return Old interrupt priority level.
178	*/	180	*/
179	static inline ipl_t interrupts_disable(void) {	181	static inline ipl_t interrupts_disable(void) {
180	pstate_reg_t pstate;	182	pstate_reg_t pstate;
181	uint64_t value;	183	uint64_t value;
182		184
183	value = pstate_read();	185	value = pstate_read();
184	pstate.value = value;	186	pstate.value = value;
185	pstate.ie = false;	187	pstate.ie = false;
186	pstate_write(pstate.value);	188	pstate_write(pstate.value);
187		189
188	return (ipl_t) value;	190	return (ipl_t) value;
189	}	191	}
190		192
191	/** Restore interrupt priority level.	193	/** Restore interrupt priority level.
192	*	194	*
193	* Restore IPL.	195	* Restore IPL.
194	*	196	*
195	* @param ipl Saved interrupt priority level.	197	* @param ipl Saved interrupt priority level.
196	*/	198	*/
197	static inline void interrupts_restore(ipl_t ipl) {	199	static inline void interrupts_restore(ipl_t ipl) {
198	pstate_reg_t pstate;	200	pstate_reg_t pstate;
199		201
200	pstate.value = pstate_read();	202	pstate.value = pstate_read();
201	pstate.ie = ((pstate_reg_t) ipl).ie;	203	pstate.ie = ((pstate_reg_t) ipl).ie;
202	pstate_write(pstate.value);	204	pstate_write(pstate.value);
203	}	205	}
204		206
205	/** Return interrupt priority level.	207	/** Return interrupt priority level.
206	*	208	*
207	* Return IPL.	209	* Return IPL.
208	*	210	*
209	* @return Current interrupt priority level.	211	* @return Current interrupt priority level.
210	*/	212	*/
211	static inline ipl_t interrupts_read(void) {	213	static inline ipl_t interrupts_read(void) {
212	return (ipl_t) pstate_read();	214	return (ipl_t) pstate_read();
213	}	215	}
214		216
215	/** Return base address of current stack.	217	/** Return base address of current stack.
216	*	218	*
217	* Return the base address of the current stack.	219	* Return the base address of the current stack.
218	* The stack is assumed to be STACK_SIZE bytes long.	220	* The stack is assumed to be STACK_SIZE bytes long.
219	* The stack must start on page boundary.	221	* The stack must start on page boundary.
220	*/	222	*/
221	static inline uintptr_t get_stack_base(void)	223	static inline uintptr_t get_stack_base(void)
222	{	224	{
223	uintptr_t v;	225	uintptr_t v;
224		226
225	__asm__ volatile ("andn %%sp, %1, %0\n" : "=r" (v) : "r" (STACK_SIZE-1));	227	__asm__ volatile ("andn %%sp, %1, %0\n" : "=r" (v) : "r" (STACK_SIZE-1));
226		228
227	return v;	229	return v;
228	}	230	}
229		231
230	/** Read Version Register.	232	/** Read Version Register.
231	*	233	*
232	* @return Value of VER register.	234	* @return Value of VER register.
233	*/	235	*/
234	static inline uint64_t ver_read(void)	236	static inline uint64_t ver_read(void)
235	{	237	{
236	uint64_t v;	238	uint64_t v;
237		239
238	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));	240	__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
239		241
240	return v;	242	return v;
241	}	243	}
242		244
243	/** Read Trap Base Address register.	245	/** Read Trap Base Address register.
244	*	246	*
245	* @return Current value in TBA.	247	* @return Current value in TBA.
246	*/	248	*/
247	static inline uint64_t tba_read(void)	249	static inline uint64_t tba_read(void)
248	{	250	{
249	uint64_t v;	251	uint64_t v;
250		252
251	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));	253	__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
252		254
253	return v;	255	return v;
254	}	256	}
255		257
256	/** Read Trap Program Counter register.	258	/** Read Trap Program Counter register.
257	*	259	*
258	* @return Current value in TPC.	260	* @return Current value in TPC.
259	*/	261	*/
260	static inline uint64_t tpc_read(void)	262	static inline uint64_t tpc_read(void)
261	{	263	{
262	uint64_t v;	264	uint64_t v;
263		265
264	__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));	266	__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
265		267
266	return v;	268	return v;
267	}	269	}
268		270
269	/** Read Trap Level register.	271	/** Read Trap Level register.
270	*	272	*
271	* @return Current value in TL.	273	* @return Current value in TL.
272	*/	274	*/
273	static inline uint64_t tl_read(void)	275	static inline uint64_t tl_read(void)
274	{	276	{
275	uint64_t v;	277	uint64_t v;
276		278
277	__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));	279	__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
278		280
279	return v;	281	return v;
280	}	282	}
281		283
282	/** Write Trap Base Address register.	284	/** Write Trap Base Address register.
283	*	285	*
284	* @param v New value of TBA.	286	* @param v New value of TBA.
285	*/	287	*/
286	static inline void tba_write(uint64_t v)	288	static inline void tba_write(uint64_t v)
287	{	289	{
288	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	290	__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
289	}	291	}
290		292
291	/** Load uint64_t from alternate space.	293	/** Load uint64_t from alternate space.
292	*	294	*
293	* @param asi ASI determining the alternate space.	295	* @param asi ASI determining the alternate space.
294	* @param va Virtual address within the ASI.	296	* @param va Virtual address within the ASI.
295	*	297	*
296	* @return Value read from the virtual address in the specified address space.	298	* @return Value read from the virtual address in the specified address space.
297	*/	299	*/
298	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	300	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
299	{	301	{
300	uint64_t v;	302	uint64_t v;
301		303
302	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));	304	__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
303		305
304	return v;	306	return v;
305	}	307	}
306		308
307	/** Store uint64_t to alternate space.	309	/** Store uint64_t to alternate space.
308	*	310	*
309	* @param asi ASI determining the alternate space.	311	* @param asi ASI determining the alternate space.
310	* @param va Virtual address within the ASI.	312	* @param va Virtual address within the ASI.
311	* @param v Value to be written.	313	* @param v Value to be written.
312	*/	314	*/
313	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	315	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
314	{	316	{
315	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");	317	__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
316	}	318	}
317		319
318	/** Flush all valid register windows to memory. */	320	/** Flush all valid register windows to memory. */
319	static inline void flushw(void)	321	static inline void flushw(void)
320	{	322	{
321	__asm__ volatile ("flushw\n");	323	__asm__ volatile ("flushw\n");
322	}	324	}
323		325
324	/** Switch to nucleus by setting TL to 1. */	326	/** Switch to nucleus by setting TL to 1. */
325	static inline void nucleus_enter(void)	327	static inline void nucleus_enter(void)
326	{	328	{
327	__asm__ volatile ("wrpr %g0, 1, %tl\n");	329	__asm__ volatile ("wrpr %g0, 1, %tl\n");
328	}	330	}
329		331
330	/** Switch from nucleus by setting TL to 0. */	332	/** Switch from nucleus by setting TL to 0. */
331	static inline void nucleus_leave(void)	333	static inline void nucleus_leave(void)
332	{	334	{
333	__asm__ volatile ("wrpr %g0, %g0, %tl\n");	335	__asm__ volatile ("wrpr %g0, %g0, %tl\n");
334	}	336	}
335		337
336	extern void cpu_halt(void);	338	extern void cpu_halt(void);
337	extern void cpu_sleep(void);	339	extern void cpu_sleep(void);
338	extern void asm_delay_loop(uint32_t t);	340	extern void asm_delay_loop(const uint32_t usec);
339		341
340	extern uint64_t read_from_ag_g7(void);	342	extern uint64_t read_from_ag_g7(void);
341	extern void write_to_ag_g6(uint64_t val);	343	extern void write_to_ag_g6(uint64_t val);
342	extern void write_to_ag_g7(uint64_t val);	344	extern void write_to_ag_g7(uint64_t val);
343	extern void write_to_ig_g6(uint64_t val);	345	extern void write_to_ig_g6(uint64_t val);
344		346
345	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	347	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
346		348
347	#endif	349	#endif
348		350
349	/** @}	351	/** @}
350	*/	352	*/
351		353