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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <macros.h> |
42 | #include <macros.h> |
43 | - | ||
44 | #ifdef CONFIG_SYMTAB |
- | |
45 | #include <symtab.h> |
43 | #include <symtab.h> |
46 | #endif |
- | |
47 | 44 | ||
48 | static unsigned int seed = 10; |
45 | static unsigned int seed = 10; |
49 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
46 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
50 | 47 | ||
51 | 48 | ||
52 | #define TLB_FLUSH \ |
49 | #define TLB_FLUSH \ |
53 | "tlbie %0\n" \ |
50 | "tlbie %0\n" \ |
54 | "addi %0, %0, 0x1000\n" |
51 | "addi %0, %0, 0x1000\n" |
55 | 52 | ||
56 | 53 | ||
57 | /** Try to find PTE for faulting address |
54 | /** Try to find PTE for faulting address |
58 | * |
55 | * |
59 | * Try to find PTE for faulting address. |
56 | * Try to find PTE for faulting address. |
60 | * The as->lock must be held on entry to this function |
57 | * The as->lock must be held on entry to this function |
61 | * if lock is true. |
58 | * if lock is true. |
62 | * |
59 | * |
63 | * @param as Address space. |
60 | * @param as Address space. |
64 | * @param lock Lock/unlock the address space. |
61 | * @param lock Lock/unlock the address space. |
65 | * @param badvaddr Faulting virtual address. |
62 | * @param badvaddr Faulting virtual address. |
66 | * @param access Access mode that caused the fault. |
63 | * @param access Access mode that caused the fault. |
67 | * @param istate Pointer to interrupted state. |
64 | * @param istate Pointer to interrupted state. |
68 | * @param pfrc Pointer to variable where as_page_fault() return code |
65 | * @param pfrc Pointer to variable where as_page_fault() return code |
69 | * will be stored. |
66 | * will be stored. |
70 | * @return PTE on success, NULL otherwise. |
67 | * @return PTE on success, NULL otherwise. |
71 | * |
68 | * |
72 | */ |
69 | */ |
73 | static pte_t * |
70 | static pte_t * |
74 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
71 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
75 | istate_t *istate, int *pfrc) |
72 | istate_t *istate, int *pfrc) |
76 | { |
73 | { |
77 | /* |
74 | /* |
78 | * Check if the mapping exists in page tables. |
75 | * Check if the mapping exists in page tables. |
79 | */ |
76 | */ |
80 | pte_t *pte = page_mapping_find(as, badvaddr); |
77 | pte_t *pte = page_mapping_find(as, badvaddr); |
81 | if ((pte) && (pte->present)) { |
78 | if ((pte) && (pte->present)) { |
82 | /* |
79 | /* |
83 | * Mapping found in page tables. |
80 | * Mapping found in page tables. |
84 | * Immediately succeed. |
81 | * Immediately succeed. |
85 | */ |
82 | */ |
86 | return pte; |
83 | return pte; |
87 | } else { |
84 | } else { |
88 | int rc; |
85 | int rc; |
89 | 86 | ||
90 | /* |
87 | /* |
91 | * Mapping not found in page tables. |
88 | * Mapping not found in page tables. |
92 | * Resort to higher-level page fault handler. |
89 | * Resort to higher-level page fault handler. |
93 | */ |
90 | */ |
94 | page_table_unlock(as, lock); |
91 | page_table_unlock(as, lock); |
95 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
92 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
96 | case AS_PF_OK: |
93 | case AS_PF_OK: |
97 | /* |
94 | /* |
98 | * The higher-level page fault handler succeeded, |
95 | * The higher-level page fault handler succeeded, |
99 | * The mapping ought to be in place. |
96 | * The mapping ought to be in place. |
100 | */ |
97 | */ |
101 | page_table_lock(as, lock); |
98 | page_table_lock(as, lock); |
102 | pte = page_mapping_find(as, badvaddr); |
99 | pte = page_mapping_find(as, badvaddr); |
103 | ASSERT((pte) && (pte->present)); |
100 | ASSERT((pte) && (pte->present)); |
104 | *pfrc = 0; |
101 | *pfrc = 0; |
105 | return pte; |
102 | return pte; |
106 | case AS_PF_DEFER: |
103 | case AS_PF_DEFER: |
107 | page_table_lock(as, lock); |
104 | page_table_lock(as, lock); |
108 | *pfrc = rc; |
105 | *pfrc = rc; |
109 | return NULL; |
106 | return NULL; |
110 | case AS_PF_FAULT: |
107 | case AS_PF_FAULT: |
111 | page_table_lock(as, lock); |
108 | page_table_lock(as, lock); |
112 | *pfrc = rc; |
109 | *pfrc = rc; |
113 | return NULL; |
110 | return NULL; |
114 | default: |
111 | default: |
115 | panic("Unexpected rc (%d).", rc); |
112 | panic("Unexpected rc (%d).", rc); |
116 | } |
113 | } |
117 | } |
114 | } |
118 | } |
115 | } |
119 | 116 | ||
120 | 117 | ||
121 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
118 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
122 | { |
119 | { |
123 | char *symbol = ""; |
120 | char *symbol; |
124 | char *sym2 = ""; |
121 | char *sym2; |
125 | 122 | ||
126 | #ifdef CONFIG_SYMTAB |
- | |
127 | char *str = get_symtab_entry(istate->pc); |
123 | symbol = symtab_fmt_name_lookup(istate->pc); |
128 | if (str) |
- | |
129 | symbol = str; |
- | |
130 | str = get_symtab_entry(istate->lr); |
124 | sym2 = symtab_fmt_name_lookup(istate->lr); |
131 | if (str) |
- | |
132 | sym2 = str; |
- | |
133 | #endif |
- | |
134 | 125 | ||
135 | fault_if_from_uspace(istate, |
126 | fault_if_from_uspace(istate, |
136 | "PHT Refill Exception on %p.", badvaddr); |
127 | "PHT Refill Exception on %p.", badvaddr); |
137 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
128 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
138 | istate->pc, symbol, sym2); |
129 | istate->pc, symbol, sym2); |
139 | } |
130 | } |
140 | 131 | ||
141 | 132 | ||
142 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
133 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
143 | { |
134 | { |
144 | uint32_t page = (vaddr >> 12) & 0xffff; |
135 | uint32_t page = (vaddr >> 12) & 0xffff; |
145 | uint32_t api = (vaddr >> 22) & 0x3f; |
136 | uint32_t api = (vaddr >> 22) & 0x3f; |
146 | 137 | ||
147 | uint32_t vsid; |
138 | uint32_t vsid; |
148 | asm volatile ( |
139 | asm volatile ( |
149 | "mfsrin %0, %1\n" |
140 | "mfsrin %0, %1\n" |
150 | : "=r" (vsid) |
141 | : "=r" (vsid) |
151 | : "r" (vaddr) |
142 | : "r" (vaddr) |
152 | ); |
143 | ); |
153 | 144 | ||
154 | uint32_t sdr1; |
145 | uint32_t sdr1; |
155 | asm volatile ( |
146 | asm volatile ( |
156 | "mfsdr1 %0\n" |
147 | "mfsdr1 %0\n" |
157 | : "=r" (sdr1) |
148 | : "=r" (sdr1) |
158 | ); |
149 | ); |
159 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
150 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
160 | 151 | ||
161 | /* Primary hash (xor) */ |
152 | /* Primary hash (xor) */ |
162 | uint32_t h = 0; |
153 | uint32_t h = 0; |
163 | uint32_t hash = vsid ^ page; |
154 | uint32_t hash = vsid ^ page; |
164 | uint32_t base = (hash & 0x3ff) << 3; |
155 | uint32_t base = (hash & 0x3ff) << 3; |
165 | uint32_t i; |
156 | uint32_t i; |
166 | bool found = false; |
157 | bool found = false; |
167 | 158 | ||
168 | /* Find colliding PTE in PTEG */ |
159 | /* Find colliding PTE in PTEG */ |
169 | for (i = 0; i < 8; i++) { |
160 | for (i = 0; i < 8; i++) { |
170 | if ((phte[base + i].v) |
161 | if ((phte[base + i].v) |
171 | && (phte[base + i].vsid == vsid) |
162 | && (phte[base + i].vsid == vsid) |
172 | && (phte[base + i].api == api) |
163 | && (phte[base + i].api == api) |
173 | && (phte[base + i].h == 0)) { |
164 | && (phte[base + i].h == 0)) { |
174 | found = true; |
165 | found = true; |
175 | break; |
166 | break; |
176 | } |
167 | } |
177 | } |
168 | } |
178 | 169 | ||
179 | if (!found) { |
170 | if (!found) { |
180 | /* Find unused PTE in PTEG */ |
171 | /* Find unused PTE in PTEG */ |
181 | for (i = 0; i < 8; i++) { |
172 | for (i = 0; i < 8; i++) { |
182 | if (!phte[base + i].v) { |
173 | if (!phte[base + i].v) { |
183 | found = true; |
174 | found = true; |
184 | break; |
175 | break; |
185 | } |
176 | } |
186 | } |
177 | } |
187 | } |
178 | } |
188 | 179 | ||
189 | if (!found) { |
180 | if (!found) { |
190 | /* Secondary hash (not) */ |
181 | /* Secondary hash (not) */ |
191 | uint32_t base2 = (~hash & 0x3ff) << 3; |
182 | uint32_t base2 = (~hash & 0x3ff) << 3; |
192 | 183 | ||
193 | /* Find colliding PTE in PTEG */ |
184 | /* Find colliding PTE in PTEG */ |
194 | for (i = 0; i < 8; i++) { |
185 | for (i = 0; i < 8; i++) { |
195 | if ((phte[base2 + i].v) |
186 | if ((phte[base2 + i].v) |
196 | && (phte[base2 + i].vsid == vsid) |
187 | && (phte[base2 + i].vsid == vsid) |
197 | && (phte[base2 + i].api == api) |
188 | && (phte[base2 + i].api == api) |
198 | && (phte[base2 + i].h == 1)) { |
189 | && (phte[base2 + i].h == 1)) { |
199 | found = true; |
190 | found = true; |
200 | base = base2; |
191 | base = base2; |
201 | h = 1; |
192 | h = 1; |
202 | break; |
193 | break; |
203 | } |
194 | } |
204 | } |
195 | } |
205 | 196 | ||
206 | if (!found) { |
197 | if (!found) { |
207 | /* Find unused PTE in PTEG */ |
198 | /* Find unused PTE in PTEG */ |
208 | for (i = 0; i < 8; i++) { |
199 | for (i = 0; i < 8; i++) { |
209 | if (!phte[base2 + i].v) { |
200 | if (!phte[base2 + i].v) { |
210 | found = true; |
201 | found = true; |
211 | base = base2; |
202 | base = base2; |
212 | h = 1; |
203 | h = 1; |
213 | break; |
204 | break; |
214 | } |
205 | } |
215 | } |
206 | } |
216 | } |
207 | } |
217 | 208 | ||
218 | if (!found) |
209 | if (!found) |
219 | i = RANDI(seed) % 8; |
210 | i = RANDI(seed) % 8; |
220 | } |
211 | } |
221 | 212 | ||
222 | phte[base + i].v = 1; |
213 | phte[base + i].v = 1; |
223 | phte[base + i].vsid = vsid; |
214 | phte[base + i].vsid = vsid; |
224 | phte[base + i].h = h; |
215 | phte[base + i].h = h; |
225 | phte[base + i].api = api; |
216 | phte[base + i].api = api; |
226 | phte[base + i].rpn = pte->pfn; |
217 | phte[base + i].rpn = pte->pfn; |
227 | phte[base + i].r = 0; |
218 | phte[base + i].r = 0; |
228 | phte[base + i].c = 0; |
219 | phte[base + i].c = 0; |
229 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
220 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
230 | phte[base + i].pp = 2; // FIXME |
221 | phte[base + i].pp = 2; // FIXME |
231 | } |
222 | } |
232 | 223 | ||
233 | 224 | ||
234 | /** Process Instruction/Data Storage Exception |
225 | /** Process Instruction/Data Storage Exception |
235 | * |
226 | * |
236 | * @param n Exception vector number. |
227 | * @param n Exception vector number. |
237 | * @param istate Interrupted register context. |
228 | * @param istate Interrupted register context. |
238 | * |
229 | * |
239 | */ |
230 | */ |
240 | void pht_refill(int n, istate_t *istate) |
231 | void pht_refill(int n, istate_t *istate) |
241 | { |
232 | { |
242 | uintptr_t badvaddr; |
233 | uintptr_t badvaddr; |
243 | pte_t *pte; |
234 | pte_t *pte; |
244 | int pfrc; |
235 | int pfrc; |
245 | as_t *as; |
236 | as_t *as; |
246 | bool lock; |
237 | bool lock; |
247 | 238 | ||
248 | if (AS == NULL) { |
239 | if (AS == NULL) { |
249 | as = AS_KERNEL; |
240 | as = AS_KERNEL; |
250 | lock = false; |
241 | lock = false; |
251 | } else { |
242 | } else { |
252 | as = AS; |
243 | as = AS; |
253 | lock = true; |
244 | lock = true; |
254 | } |
245 | } |
255 | 246 | ||
256 | if (n == VECTOR_DATA_STORAGE) |
247 | if (n == VECTOR_DATA_STORAGE) |
257 | badvaddr = istate->dar; |
248 | badvaddr = istate->dar; |
258 | else |
249 | else |
259 | badvaddr = istate->pc; |
250 | badvaddr = istate->pc; |
260 | 251 | ||
261 | page_table_lock(as, lock); |
252 | page_table_lock(as, lock); |
262 | 253 | ||
263 | pte = find_mapping_and_check(as, lock, badvaddr, |
254 | pte = find_mapping_and_check(as, lock, badvaddr, |
264 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
255 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
265 | if (!pte) { |
256 | if (!pte) { |
266 | switch (pfrc) { |
257 | switch (pfrc) { |
267 | case AS_PF_FAULT: |
258 | case AS_PF_FAULT: |
268 | goto fail; |
259 | goto fail; |
269 | break; |
260 | break; |
270 | case AS_PF_DEFER: |
261 | case AS_PF_DEFER: |
271 | /* |
262 | /* |
272 | * The page fault came during copy_from_uspace() |
263 | * The page fault came during copy_from_uspace() |
273 | * or copy_to_uspace(). |
264 | * or copy_to_uspace(). |
274 | */ |
265 | */ |
275 | page_table_unlock(as, lock); |
266 | page_table_unlock(as, lock); |
276 | return; |
267 | return; |
277 | default: |
268 | default: |
278 | panic("Unexpected pfrc (%d).", pfrc); |
269 | panic("Unexpected pfrc (%d).", pfrc); |
279 | } |
270 | } |
280 | } |
271 | } |
281 | 272 | ||
282 | pte->accessed = 1; /* Record access to PTE */ |
273 | pte->accessed = 1; /* Record access to PTE */ |
283 | pht_insert(badvaddr, pte); |
274 | pht_insert(badvaddr, pte); |
284 | 275 | ||
285 | page_table_unlock(as, lock); |
276 | page_table_unlock(as, lock); |
286 | return; |
277 | return; |
287 | 278 | ||
288 | fail: |
279 | fail: |
289 | page_table_unlock(as, lock); |
280 | page_table_unlock(as, lock); |
290 | pht_refill_fail(badvaddr, istate); |
281 | pht_refill_fail(badvaddr, istate); |
291 | } |
282 | } |
292 | 283 | ||
293 | 284 | ||
294 | /** Process Instruction/Data Storage Exception in Real Mode |
285 | /** Process Instruction/Data Storage Exception in Real Mode |
295 | * |
286 | * |
296 | * @param n Exception vector number. |
287 | * @param n Exception vector number. |
297 | * @param istate Interrupted register context. |
288 | * @param istate Interrupted register context. |
298 | * |
289 | * |
299 | */ |
290 | */ |
300 | bool pht_refill_real(int n, istate_t *istate) |
291 | bool pht_refill_real(int n, istate_t *istate) |
301 | { |
292 | { |
302 | uintptr_t badvaddr; |
293 | uintptr_t badvaddr; |
303 | 294 | ||
304 | if (n == VECTOR_DATA_STORAGE) |
295 | if (n == VECTOR_DATA_STORAGE) |
305 | badvaddr = istate->dar; |
296 | badvaddr = istate->dar; |
306 | else |
297 | else |
307 | badvaddr = istate->pc; |
298 | badvaddr = istate->pc; |
308 | 299 | ||
309 | uint32_t physmem; |
300 | uint32_t physmem; |
310 | asm volatile ( |
301 | asm volatile ( |
311 | "mfsprg3 %0\n" |
302 | "mfsprg3 %0\n" |
312 | : "=r" (physmem) |
303 | : "=r" (physmem) |
313 | ); |
304 | ); |
314 | 305 | ||
315 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
306 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
316 | return false; |
307 | return false; |
317 | 308 | ||
318 | uint32_t page = (badvaddr >> 12) & 0xffff; |
309 | uint32_t page = (badvaddr >> 12) & 0xffff; |
319 | uint32_t api = (badvaddr >> 22) & 0x3f; |
310 | uint32_t api = (badvaddr >> 22) & 0x3f; |
320 | 311 | ||
321 | uint32_t vsid; |
312 | uint32_t vsid; |
322 | asm volatile ( |
313 | asm volatile ( |
323 | "mfsrin %0, %1\n" |
314 | "mfsrin %0, %1\n" |
324 | : "=r" (vsid) |
315 | : "=r" (vsid) |
325 | : "r" (badvaddr) |
316 | : "r" (badvaddr) |
326 | ); |
317 | ); |
327 | 318 | ||
328 | uint32_t sdr1; |
319 | uint32_t sdr1; |
329 | asm volatile ( |
320 | asm volatile ( |
330 | "mfsdr1 %0\n" |
321 | "mfsdr1 %0\n" |
331 | : "=r" (sdr1) |
322 | : "=r" (sdr1) |
332 | ); |
323 | ); |
333 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
324 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
334 | 325 | ||
335 | /* Primary hash (xor) */ |
326 | /* Primary hash (xor) */ |
336 | uint32_t h = 0; |
327 | uint32_t h = 0; |
337 | uint32_t hash = vsid ^ page; |
328 | uint32_t hash = vsid ^ page; |
338 | uint32_t base = (hash & 0x3ff) << 3; |
329 | uint32_t base = (hash & 0x3ff) << 3; |
339 | uint32_t i; |
330 | uint32_t i; |
340 | bool found = false; |
331 | bool found = false; |
341 | 332 | ||
342 | /* Find colliding PTE in PTEG */ |
333 | /* Find colliding PTE in PTEG */ |
343 | for (i = 0; i < 8; i++) { |
334 | for (i = 0; i < 8; i++) { |
344 | if ((phte_real[base + i].v) |
335 | if ((phte_real[base + i].v) |
345 | && (phte_real[base + i].vsid == vsid) |
336 | && (phte_real[base + i].vsid == vsid) |
346 | && (phte_real[base + i].api == api) |
337 | && (phte_real[base + i].api == api) |
347 | && (phte_real[base + i].h == 0)) { |
338 | && (phte_real[base + i].h == 0)) { |
348 | found = true; |
339 | found = true; |
349 | break; |
340 | break; |
350 | } |
341 | } |
351 | } |
342 | } |
352 | 343 | ||
353 | if (!found) { |
344 | if (!found) { |
354 | /* Find unused PTE in PTEG */ |
345 | /* Find unused PTE in PTEG */ |
355 | for (i = 0; i < 8; i++) { |
346 | for (i = 0; i < 8; i++) { |
356 | if (!phte_real[base + i].v) { |
347 | if (!phte_real[base + i].v) { |
357 | found = true; |
348 | found = true; |
358 | break; |
349 | break; |
359 | } |
350 | } |
360 | } |
351 | } |
361 | } |
352 | } |
362 | 353 | ||
363 | if (!found) { |
354 | if (!found) { |
364 | /* Secondary hash (not) */ |
355 | /* Secondary hash (not) */ |
365 | uint32_t base2 = (~hash & 0x3ff) << 3; |
356 | uint32_t base2 = (~hash & 0x3ff) << 3; |
366 | 357 | ||
367 | /* Find colliding PTE in PTEG */ |
358 | /* Find colliding PTE in PTEG */ |
368 | for (i = 0; i < 8; i++) { |
359 | for (i = 0; i < 8; i++) { |
369 | if ((phte_real[base2 + i].v) |
360 | if ((phte_real[base2 + i].v) |
370 | && (phte_real[base2 + i].vsid == vsid) |
361 | && (phte_real[base2 + i].vsid == vsid) |
371 | && (phte_real[base2 + i].api == api) |
362 | && (phte_real[base2 + i].api == api) |
372 | && (phte_real[base2 + i].h == 1)) { |
363 | && (phte_real[base2 + i].h == 1)) { |
373 | found = true; |
364 | found = true; |
374 | base = base2; |
365 | base = base2; |
375 | h = 1; |
366 | h = 1; |
376 | break; |
367 | break; |
377 | } |
368 | } |
378 | } |
369 | } |
379 | 370 | ||
380 | if (!found) { |
371 | if (!found) { |
381 | /* Find unused PTE in PTEG */ |
372 | /* Find unused PTE in PTEG */ |
382 | for (i = 0; i < 8; i++) { |
373 | for (i = 0; i < 8; i++) { |
383 | if (!phte_real[base2 + i].v) { |
374 | if (!phte_real[base2 + i].v) { |
384 | found = true; |
375 | found = true; |
385 | base = base2; |
376 | base = base2; |
386 | h = 1; |
377 | h = 1; |
387 | break; |
378 | break; |
388 | } |
379 | } |
389 | } |
380 | } |
390 | } |
381 | } |
391 | 382 | ||
392 | if (!found) { |
383 | if (!found) { |
393 | /* Use secondary hash to avoid collisions |
384 | /* Use secondary hash to avoid collisions |
394 | with usual PHT refill handler. */ |
385 | with usual PHT refill handler. */ |
395 | i = RANDI(seed_real) % 8; |
386 | i = RANDI(seed_real) % 8; |
396 | base = base2; |
387 | base = base2; |
397 | h = 1; |
388 | h = 1; |
398 | } |
389 | } |
399 | } |
390 | } |
400 | 391 | ||
401 | phte_real[base + i].v = 1; |
392 | phte_real[base + i].v = 1; |
402 | phte_real[base + i].vsid = vsid; |
393 | phte_real[base + i].vsid = vsid; |
403 | phte_real[base + i].h = h; |
394 | phte_real[base + i].h = h; |
404 | phte_real[base + i].api = api; |
395 | phte_real[base + i].api = api; |
405 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
396 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
406 | phte_real[base + i].r = 0; |
397 | phte_real[base + i].r = 0; |
407 | phte_real[base + i].c = 0; |
398 | phte_real[base + i].c = 0; |
408 | phte_real[base + i].wimg = 0; |
399 | phte_real[base + i].wimg = 0; |
409 | phte_real[base + i].pp = 2; // FIXME |
400 | phte_real[base + i].pp = 2; // FIXME |
410 | 401 | ||
411 | return true; |
402 | return true; |
412 | } |
403 | } |
413 | 404 | ||
414 | 405 | ||
415 | /** Process ITLB/DTLB Miss Exception in Real Mode |
406 | /** Process ITLB/DTLB Miss Exception in Real Mode |
416 | * |
407 | * |
417 | * |
408 | * |
418 | */ |
409 | */ |
419 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
410 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
420 | { |
411 | { |
421 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
412 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
422 | 413 | ||
423 | uint32_t physmem; |
414 | uint32_t physmem; |
424 | asm volatile ( |
415 | asm volatile ( |
425 | "mfsprg3 %0\n" |
416 | "mfsprg3 %0\n" |
426 | : "=r" (physmem) |
417 | : "=r" (physmem) |
427 | ); |
418 | ); |
428 | 419 | ||
429 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
420 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
430 | return; // FIXME |
421 | return; // FIXME |
431 | 422 | ||
432 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
423 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
433 | ptelo.wimg = 0; |
424 | ptelo.wimg = 0; |
434 | ptelo.pp = 2; // FIXME |
425 | ptelo.pp = 2; // FIXME |
435 | 426 | ||
436 | uint32_t index = 0; |
427 | uint32_t index = 0; |
437 | asm volatile ( |
428 | asm volatile ( |
438 | "mtspr 981, %0\n" |
429 | "mtspr 981, %0\n" |
439 | "mtspr 982, %1\n" |
430 | "mtspr 982, %1\n" |
440 | "tlbld %2\n" |
431 | "tlbld %2\n" |
441 | "tlbli %2\n" |
432 | "tlbli %2\n" |
442 | : "=r" (index) |
433 | : "=r" (index) |
443 | : "r" (ptehi), |
434 | : "r" (ptehi), |
444 | "r" (ptelo) |
435 | "r" (ptelo) |
445 | ); |
436 | ); |
446 | } |
437 | } |
447 | 438 | ||
448 | 439 | ||
449 | void tlb_arch_init(void) |
440 | void tlb_arch_init(void) |
450 | { |
441 | { |
451 | tlb_invalidate_all(); |
442 | tlb_invalidate_all(); |
452 | } |
443 | } |
453 | 444 | ||
454 | 445 | ||
455 | void tlb_invalidate_all(void) |
446 | void tlb_invalidate_all(void) |
456 | { |
447 | { |
457 | uint32_t index; |
448 | uint32_t index; |
458 | asm volatile ( |
449 | asm volatile ( |
459 | "li %0, 0\n" |
450 | "li %0, 0\n" |
460 | "sync\n" |
451 | "sync\n" |
461 | 452 | ||
462 | TLB_FLUSH |
453 | TLB_FLUSH |
463 | TLB_FLUSH |
454 | TLB_FLUSH |
464 | TLB_FLUSH |
455 | TLB_FLUSH |
465 | TLB_FLUSH |
456 | TLB_FLUSH |
466 | TLB_FLUSH |
457 | TLB_FLUSH |
467 | TLB_FLUSH |
458 | TLB_FLUSH |
468 | TLB_FLUSH |
459 | TLB_FLUSH |
469 | TLB_FLUSH |
460 | TLB_FLUSH |
470 | 461 | ||
471 | TLB_FLUSH |
462 | TLB_FLUSH |
472 | TLB_FLUSH |
463 | TLB_FLUSH |
473 | TLB_FLUSH |
464 | TLB_FLUSH |
474 | TLB_FLUSH |
465 | TLB_FLUSH |
475 | TLB_FLUSH |
466 | TLB_FLUSH |
476 | TLB_FLUSH |
467 | TLB_FLUSH |
477 | TLB_FLUSH |
468 | TLB_FLUSH |
478 | TLB_FLUSH |
469 | TLB_FLUSH |
479 | 470 | ||
480 | TLB_FLUSH |
471 | TLB_FLUSH |
481 | TLB_FLUSH |
472 | TLB_FLUSH |
482 | TLB_FLUSH |
473 | TLB_FLUSH |
483 | TLB_FLUSH |
474 | TLB_FLUSH |
484 | TLB_FLUSH |
475 | TLB_FLUSH |
485 | TLB_FLUSH |
476 | TLB_FLUSH |
486 | TLB_FLUSH |
477 | TLB_FLUSH |
487 | TLB_FLUSH |
478 | TLB_FLUSH |
488 | 479 | ||
489 | TLB_FLUSH |
480 | TLB_FLUSH |
490 | TLB_FLUSH |
481 | TLB_FLUSH |
491 | TLB_FLUSH |
482 | TLB_FLUSH |
492 | TLB_FLUSH |
483 | TLB_FLUSH |
493 | TLB_FLUSH |
484 | TLB_FLUSH |
494 | TLB_FLUSH |
485 | TLB_FLUSH |
495 | TLB_FLUSH |
486 | TLB_FLUSH |
496 | TLB_FLUSH |
487 | TLB_FLUSH |
497 | 488 | ||
498 | TLB_FLUSH |
489 | TLB_FLUSH |
499 | TLB_FLUSH |
490 | TLB_FLUSH |
500 | TLB_FLUSH |
491 | TLB_FLUSH |
501 | TLB_FLUSH |
492 | TLB_FLUSH |
502 | TLB_FLUSH |
493 | TLB_FLUSH |
503 | TLB_FLUSH |
494 | TLB_FLUSH |
504 | TLB_FLUSH |
495 | TLB_FLUSH |
505 | TLB_FLUSH |
496 | TLB_FLUSH |
506 | 497 | ||
507 | TLB_FLUSH |
498 | TLB_FLUSH |
508 | TLB_FLUSH |
499 | TLB_FLUSH |
509 | TLB_FLUSH |
500 | TLB_FLUSH |
510 | TLB_FLUSH |
501 | TLB_FLUSH |
511 | TLB_FLUSH |
502 | TLB_FLUSH |
512 | TLB_FLUSH |
503 | TLB_FLUSH |
513 | TLB_FLUSH |
504 | TLB_FLUSH |
514 | TLB_FLUSH |
505 | TLB_FLUSH |
515 | 506 | ||
516 | TLB_FLUSH |
507 | TLB_FLUSH |
517 | TLB_FLUSH |
508 | TLB_FLUSH |
518 | TLB_FLUSH |
509 | TLB_FLUSH |
519 | TLB_FLUSH |
510 | TLB_FLUSH |
520 | TLB_FLUSH |
511 | TLB_FLUSH |
521 | TLB_FLUSH |
512 | TLB_FLUSH |
522 | TLB_FLUSH |
513 | TLB_FLUSH |
523 | TLB_FLUSH |
514 | TLB_FLUSH |
524 | 515 | ||
525 | TLB_FLUSH |
516 | TLB_FLUSH |
526 | TLB_FLUSH |
517 | TLB_FLUSH |
527 | TLB_FLUSH |
518 | TLB_FLUSH |
528 | TLB_FLUSH |
519 | TLB_FLUSH |
529 | TLB_FLUSH |
520 | TLB_FLUSH |
530 | TLB_FLUSH |
521 | TLB_FLUSH |
531 | TLB_FLUSH |
522 | TLB_FLUSH |
532 | TLB_FLUSH |
523 | TLB_FLUSH |
533 | 524 | ||
534 | "eieio\n" |
525 | "eieio\n" |
535 | "tlbsync\n" |
526 | "tlbsync\n" |
536 | "sync\n" |
527 | "sync\n" |
537 | : "=r" (index) |
528 | : "=r" (index) |
538 | ); |
529 | ); |
539 | } |
530 | } |
540 | 531 | ||
541 | 532 | ||
542 | void tlb_invalidate_asid(asid_t asid) |
533 | void tlb_invalidate_asid(asid_t asid) |
543 | { |
534 | { |
544 | uint32_t sdr1; |
535 | uint32_t sdr1; |
545 | asm volatile ( |
536 | asm volatile ( |
546 | "mfsdr1 %0\n" |
537 | "mfsdr1 %0\n" |
547 | : "=r" (sdr1) |
538 | : "=r" (sdr1) |
548 | ); |
539 | ); |
549 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
540 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
550 | 541 | ||
551 | uint32_t i; |
542 | uint32_t i; |
552 | for (i = 0; i < 8192; i++) { |
543 | for (i = 0; i < 8192; i++) { |
553 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
544 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
554 | (phte[i].vsid < ((asid << 4) + 16))) |
545 | (phte[i].vsid < ((asid << 4) + 16))) |
555 | phte[i].v = 0; |
546 | phte[i].v = 0; |
556 | } |
547 | } |
557 | tlb_invalidate_all(); |
548 | tlb_invalidate_all(); |
558 | } |
549 | } |
559 | 550 | ||
560 | 551 | ||
561 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
552 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
562 | { |
553 | { |
563 | // TODO |
554 | // TODO |
564 | tlb_invalidate_all(); |
555 | tlb_invalidate_all(); |
565 | } |
556 | } |
566 | 557 | ||
567 | 558 | ||
568 | #define PRINT_BAT(name, ureg, lreg) \ |
559 | #define PRINT_BAT(name, ureg, lreg) \ |
569 | asm volatile ( \ |
560 | asm volatile ( \ |
570 | "mfspr %0," #ureg "\n" \ |
561 | "mfspr %0," #ureg "\n" \ |
571 | "mfspr %1," #lreg "\n" \ |
562 | "mfspr %1," #lreg "\n" \ |
572 | : "=r" (upper), "=r" (lower) \ |
563 | : "=r" (upper), "=r" (lower) \ |
573 | ); \ |
564 | ); \ |
574 | mask = (upper & 0x1ffc) >> 2; \ |
565 | mask = (upper & 0x1ffc) >> 2; \ |
575 | if (upper & 3) { \ |
566 | if (upper & 3) { \ |
576 | uint32_t tmp = mask; \ |
567 | uint32_t tmp = mask; \ |
577 | length = 128; \ |
568 | length = 128; \ |
578 | while (tmp) { \ |
569 | while (tmp) { \ |
579 | if ((tmp & 1) == 0) { \ |
570 | if ((tmp & 1) == 0) { \ |
580 | printf("ibat[0]: error in mask\n"); \ |
571 | printf("ibat[0]: error in mask\n"); \ |
581 | break; \ |
572 | break; \ |
582 | } \ |
573 | } \ |
583 | length <<= 1; \ |
574 | length <<= 1; \ |
584 | tmp >>= 1; \ |
575 | tmp >>= 1; \ |
585 | } \ |
576 | } \ |
586 | } else \ |
577 | } else \ |
587 | length = 0; \ |
578 | length = 0; \ |
588 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
579 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
589 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
580 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
590 | lower & 0xffff0000, length, mask, \ |
581 | lower & 0xffff0000, length, mask, \ |
591 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
582 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
592 | (upper & 1) ? " user" : ""); |
583 | (upper & 1) ? " user" : ""); |
593 | 584 | ||
594 | 585 | ||
595 | void tlb_print(void) |
586 | void tlb_print(void) |
596 | { |
587 | { |
597 | uint32_t sr; |
588 | uint32_t sr; |
598 | 589 | ||
599 | for (sr = 0; sr < 16; sr++) { |
590 | for (sr = 0; sr < 16; sr++) { |
600 | uint32_t vsid; |
591 | uint32_t vsid; |
601 | asm volatile ( |
592 | asm volatile ( |
602 | "mfsrin %0, %1\n" |
593 | "mfsrin %0, %1\n" |
603 | : "=r" (vsid) |
594 | : "=r" (vsid) |
604 | : "r" (sr << 28) |
595 | : "r" (sr << 28) |
605 | ); |
596 | ); |
606 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
597 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
607 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
598 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
608 | ((vsid >> 30) & 1) ? " supervisor" : "", |
599 | ((vsid >> 30) & 1) ? " supervisor" : "", |
609 | ((vsid >> 29) & 1) ? " user" : ""); |
600 | ((vsid >> 29) & 1) ? " user" : ""); |
610 | } |
601 | } |
611 | 602 | ||
612 | uint32_t upper; |
603 | uint32_t upper; |
613 | uint32_t lower; |
604 | uint32_t lower; |
614 | uint32_t mask; |
605 | uint32_t mask; |
615 | uint32_t length; |
606 | uint32_t length; |
616 | 607 | ||
617 | PRINT_BAT("ibat[0]", 528, 529); |
608 | PRINT_BAT("ibat[0]", 528, 529); |
618 | PRINT_BAT("ibat[1]", 530, 531); |
609 | PRINT_BAT("ibat[1]", 530, 531); |
619 | PRINT_BAT("ibat[2]", 532, 533); |
610 | PRINT_BAT("ibat[2]", 532, 533); |
620 | PRINT_BAT("ibat[3]", 534, 535); |
611 | PRINT_BAT("ibat[3]", 534, 535); |
621 | 612 | ||
622 | PRINT_BAT("dbat[0]", 536, 537); |
613 | PRINT_BAT("dbat[0]", 536, 537); |
623 | PRINT_BAT("dbat[1]", 538, 539); |
614 | PRINT_BAT("dbat[1]", 538, 539); |
624 | PRINT_BAT("dbat[2]", 540, 541); |
615 | PRINT_BAT("dbat[2]", 540, 541); |
625 | PRINT_BAT("dbat[3]", 542, 543); |
616 | PRINT_BAT("dbat[3]", 542, 543); |
626 | } |
617 | } |
627 | 618 | ||
628 | /** @} |
619 | /** @} |
629 | */ |
620 | */ |
630 | 621 |