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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <symtab.h> |
42 | #include <symtab.h> |
43 | 43 | ||
44 | 44 | ||
45 | /** Try to find PTE for faulting address |
45 | /** Try to find PTE for faulting address |
46 | * |
46 | * |
47 | * Try to find PTE for faulting address. |
47 | * Try to find PTE for faulting address. |
48 | * The as->lock must be held on entry to this function |
48 | * The as->lock must be held on entry to this function |
49 | * if lock is true. |
49 | * if lock is true. |
50 | * |
50 | * |
51 | * @param as Address space. |
51 | * @param as Address space. |
52 | * @param lock Lock/unlock the address space. |
52 | * @param lock Lock/unlock the address space. |
53 | * @param badvaddr Faulting virtual address. |
53 | * @param badvaddr Faulting virtual address. |
54 | * @param access Access mode that caused the fault. |
54 | * @param access Access mode that caused the fault. |
55 | * @param istate Pointer to interrupted state. |
55 | * @param istate Pointer to interrupted state. |
56 | * @param pfrc Pointer to variable where as_page_fault() return code |
56 | * @param pfrc Pointer to variable where as_page_fault() return code |
57 | * will be stored. |
57 | * will be stored. |
58 | * @return PTE on success, NULL otherwise. |
58 | * @return PTE on success, NULL otherwise. |
59 | * |
59 | * |
60 | */ |
60 | */ |
61 | static pte_t * |
61 | static pte_t * |
62 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
62 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
63 | istate_t *istate, int *pfrc) |
63 | istate_t *istate, int *pfrc) |
64 | { |
64 | { |
65 | /* |
65 | /* |
66 | * Check if the mapping exists in page tables. |
66 | * Check if the mapping exists in page tables. |
67 | */ |
67 | */ |
68 | pte_t *pte = page_mapping_find(as, badvaddr); |
68 | pte_t *pte = page_mapping_find(as, badvaddr); |
69 | if ((pte) && (pte->present)) { |
69 | if ((pte) && (pte->present)) { |
70 | /* |
70 | /* |
71 | * Mapping found in page tables. |
71 | * Mapping found in page tables. |
72 | * Immediately succeed. |
72 | * Immediately succeed. |
73 | */ |
73 | */ |
74 | return pte; |
74 | return pte; |
75 | } else { |
75 | } else { |
76 | int rc; |
76 | int rc; |
77 | 77 | ||
78 | /* |
78 | /* |
79 | * Mapping not found in page tables. |
79 | * Mapping not found in page tables. |
80 | * Resort to higher-level page fault handler. |
80 | * Resort to higher-level page fault handler. |
81 | */ |
81 | */ |
82 | page_table_unlock(as, lock); |
82 | page_table_unlock(as, lock); |
83 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
83 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
84 | case AS_PF_OK: |
84 | case AS_PF_OK: |
85 | /* |
85 | /* |
86 | * The higher-level page fault handler succeeded, |
86 | * The higher-level page fault handler succeeded, |
87 | * The mapping ought to be in place. |
87 | * The mapping ought to be in place. |
88 | */ |
88 | */ |
89 | page_table_lock(as, lock); |
89 | page_table_lock(as, lock); |
90 | pte = page_mapping_find(as, badvaddr); |
90 | pte = page_mapping_find(as, badvaddr); |
91 | ASSERT((pte) && (pte->present)); |
91 | ASSERT((pte) && (pte->present)); |
92 | *pfrc = 0; |
92 | *pfrc = 0; |
93 | return pte; |
93 | return pte; |
94 | case AS_PF_DEFER: |
94 | case AS_PF_DEFER: |
95 | page_table_lock(as, lock); |
95 | page_table_lock(as, lock); |
96 | *pfrc = rc; |
96 | *pfrc = rc; |
97 | return NULL; |
97 | return NULL; |
98 | case AS_PF_FAULT: |
98 | case AS_PF_FAULT: |
99 | page_table_lock(as, lock); |
99 | page_table_lock(as, lock); |
100 | *pfrc = rc; |
100 | *pfrc = rc; |
101 | return NULL; |
101 | return NULL; |
102 | default: |
102 | default: |
103 | panic("Unexpected rc (%d).", rc); |
103 | panic("Unexpected rc (%d).", rc); |
104 | } |
104 | } |
105 | } |
105 | } |
106 | } |
106 | } |
107 | 107 | ||
108 | 108 | ||
109 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
109 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
110 | { |
110 | { |
111 | char *symbol = ""; |
111 | char *symbol = ""; |
112 | char *sym2 = ""; |
112 | char *sym2 = ""; |
113 | 113 | ||
114 | char *s = get_symtab_entry(istate->pc); |
114 | char *str = get_symtab_entry(istate->pc); |
115 | if (s) |
115 | if (str) |
116 | symbol = s; |
116 | symbol = str; |
117 | s = get_symtab_entry(istate->lr); |
117 | str = get_symtab_entry(istate->lr); |
118 | if (s) |
118 | if (str) |
119 | sym2 = s; |
119 | sym2 = str; |
120 | 120 | ||
121 | fault_if_from_uspace(istate, |
121 | fault_if_from_uspace(istate, |
122 | "%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
122 | "PHT Refill Exception on %p.", badvaddr); |
123 | istate->pc, symbol, sym2); |
- | |
124 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
123 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
125 | istate->pc, symbol, sym2); |
124 | istate->pc, symbol, sym2); |
126 | } |
125 | } |
127 | 126 | ||
128 | 127 | ||
129 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
128 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
130 | { |
129 | { |
131 | uint32_t page = (vaddr >> 12) & 0xffff; |
130 | uint32_t page = (vaddr >> 12) & 0xffff; |
132 | uint32_t api = (vaddr >> 22) & 0x3f; |
131 | uint32_t api = (vaddr >> 22) & 0x3f; |
133 | 132 | ||
134 | uint32_t vsid; |
133 | uint32_t vsid; |
135 | asm volatile ( |
134 | asm volatile ( |
136 | "mfsrin %0, %1\n" |
135 | "mfsrin %0, %1\n" |
137 | : "=r" (vsid) |
136 | : "=r" (vsid) |
138 | : "r" (vaddr) |
137 | : "r" (vaddr) |
139 | ); |
138 | ); |
140 | 139 | ||
141 | uint32_t sdr1; |
140 | uint32_t sdr1; |
142 | asm volatile ( |
141 | asm volatile ( |
143 | "mfsdr1 %0\n" |
142 | "mfsdr1 %0\n" |
144 | : "=r" (sdr1) |
143 | : "=r" (sdr1) |
145 | ); |
144 | ); |
146 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
145 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
147 | 146 | ||
148 | /* Primary hash (xor) */ |
147 | /* Primary hash (xor) */ |
149 | uint32_t h = 0; |
148 | uint32_t h = 0; |
150 | uint32_t hash = vsid ^ page; |
149 | uint32_t hash = vsid ^ page; |
151 | uint32_t base = (hash & 0x3ff) << 3; |
150 | uint32_t base = (hash & 0x3ff) << 3; |
152 | uint32_t i; |
151 | uint32_t i; |
153 | bool found = false; |
152 | bool found = false; |
154 | 153 | ||
155 | /* Find unused or colliding |
154 | /* Find unused or colliding |
156 | PTE in PTEG */ |
155 | PTE in PTEG */ |
157 | for (i = 0; i < 8; i++) { |
156 | for (i = 0; i < 8; i++) { |
158 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
157 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && |
159 | (phte[base + i].api == api))) { |
158 | (phte[base + i].api == api))) { |
160 | found = true; |
159 | found = true; |
161 | break; |
160 | break; |
162 | } |
161 | } |
163 | } |
162 | } |
164 | 163 | ||
165 | if (!found) { |
164 | if (!found) { |
166 | /* Secondary hash (not) */ |
165 | /* Secondary hash (not) */ |
167 | uint32_t base2 = (~hash & 0x3ff) << 3; |
166 | uint32_t base2 = (~hash & 0x3ff) << 3; |
168 | 167 | ||
169 | /* Find unused or colliding |
168 | /* Find unused or colliding |
170 | PTE in PTEG */ |
169 | PTE in PTEG */ |
171 | for (i = 0; i < 8; i++) { |
170 | for (i = 0; i < 8; i++) { |
172 | if ((!phte[base2 + i].v) || |
171 | if ((!phte[base2 + i].v) || |
173 | ((phte[base2 + i].vsid == vsid) && |
172 | ((phte[base2 + i].vsid == vsid) && |
174 | (phte[base2 + i].api == api))) { |
173 | (phte[base2 + i].api == api))) { |
175 | found = true; |
174 | found = true; |
176 | base = base2; |
175 | base = base2; |
177 | h = 1; |
176 | h = 1; |
178 | break; |
177 | break; |
179 | } |
178 | } |
180 | } |
179 | } |
181 | 180 | ||
182 | if (!found) { |
181 | if (!found) { |
183 | // TODO: A/C precedence groups |
182 | // TODO: A/C precedence groups |
184 | i = page % 8; |
183 | i = page % 8; |
185 | } |
184 | } |
186 | } |
185 | } |
187 | 186 | ||
188 | phte[base + i].v = 1; |
187 | phte[base + i].v = 1; |
189 | phte[base + i].vsid = vsid; |
188 | phte[base + i].vsid = vsid; |
190 | phte[base + i].h = h; |
189 | phte[base + i].h = h; |
191 | phte[base + i].api = api; |
190 | phte[base + i].api = api; |
192 | phte[base + i].rpn = pte->pfn; |
191 | phte[base + i].rpn = pte->pfn; |
193 | phte[base + i].r = 0; |
192 | phte[base + i].r = 0; |
194 | phte[base + i].c = 0; |
193 | phte[base + i].c = 0; |
195 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
194 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
196 | phte[base + i].pp = 2; // FIXME |
195 | phte[base + i].pp = 2; // FIXME |
197 | } |
196 | } |
198 | 197 | ||
199 | 198 | ||
200 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
199 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
201 | { |
200 | { |
202 | uint32_t page = (vaddr >> 12) & 0xffff; |
201 | uint32_t page = (vaddr >> 12) & 0xffff; |
203 | uint32_t api = (vaddr >> 22) & 0x3f; |
202 | uint32_t api = (vaddr >> 22) & 0x3f; |
204 | 203 | ||
205 | uint32_t vsid; |
204 | uint32_t vsid; |
206 | asm volatile ( |
205 | asm volatile ( |
207 | "mfsrin %0, %1\n" |
206 | "mfsrin %0, %1\n" |
208 | : "=r" (vsid) |
207 | : "=r" (vsid) |
209 | : "r" (vaddr) |
208 | : "r" (vaddr) |
210 | ); |
209 | ); |
211 | 210 | ||
212 | uint32_t sdr1; |
211 | uint32_t sdr1; |
213 | asm volatile ( |
212 | asm volatile ( |
214 | "mfsdr1 %0\n" |
213 | "mfsdr1 %0\n" |
215 | : "=r" (sdr1) |
214 | : "=r" (sdr1) |
216 | ); |
215 | ); |
217 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
216 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
218 | 217 | ||
219 | /* Primary hash (xor) */ |
218 | /* Primary hash (xor) */ |
220 | uint32_t h = 0; |
219 | uint32_t h = 0; |
221 | uint32_t hash = vsid ^ page; |
220 | uint32_t hash = vsid ^ page; |
222 | uint32_t base = (hash & 0x3ff) << 3; |
221 | uint32_t base = (hash & 0x3ff) << 3; |
223 | uint32_t i; |
222 | uint32_t i; |
224 | bool found = false; |
223 | bool found = false; |
225 | 224 | ||
226 | /* Find unused or colliding |
225 | /* Find unused or colliding |
227 | PTE in PTEG */ |
226 | PTE in PTEG */ |
228 | for (i = 0; i < 8; i++) { |
227 | for (i = 0; i < 8; i++) { |
229 | if ((!phte_physical[base + i].v) || |
228 | if ((!phte_physical[base + i].v) || |
230 | ((phte_physical[base + i].vsid == vsid) && |
229 | ((phte_physical[base + i].vsid == vsid) && |
231 | (phte_physical[base + i].api == api))) { |
230 | (phte_physical[base + i].api == api))) { |
232 | found = true; |
231 | found = true; |
233 | break; |
232 | break; |
234 | } |
233 | } |
235 | } |
234 | } |
236 | 235 | ||
237 | if (!found) { |
236 | if (!found) { |
238 | /* Secondary hash (not) */ |
237 | /* Secondary hash (not) */ |
239 | uint32_t base2 = (~hash & 0x3ff) << 3; |
238 | uint32_t base2 = (~hash & 0x3ff) << 3; |
240 | 239 | ||
241 | /* Find unused or colliding |
240 | /* Find unused or colliding |
242 | PTE in PTEG */ |
241 | PTE in PTEG */ |
243 | for (i = 0; i < 8; i++) { |
242 | for (i = 0; i < 8; i++) { |
244 | if ((!phte_physical[base2 + i].v) || |
243 | if ((!phte_physical[base2 + i].v) || |
245 | ((phte_physical[base2 + i].vsid == vsid) && |
244 | ((phte_physical[base2 + i].vsid == vsid) && |
246 | (phte_physical[base2 + i].api == api))) { |
245 | (phte_physical[base2 + i].api == api))) { |
247 | found = true; |
246 | found = true; |
248 | base = base2; |
247 | base = base2; |
249 | h = 1; |
248 | h = 1; |
250 | break; |
249 | break; |
251 | } |
250 | } |
252 | } |
251 | } |
253 | 252 | ||
254 | if (!found) { |
253 | if (!found) { |
255 | // TODO: A/C precedence groups |
254 | // TODO: A/C precedence groups |
256 | i = page % 8; |
255 | i = page % 8; |
257 | } |
256 | } |
258 | } |
257 | } |
259 | 258 | ||
260 | phte_physical[base + i].v = 1; |
259 | phte_physical[base + i].v = 1; |
261 | phte_physical[base + i].vsid = vsid; |
260 | phte_physical[base + i].vsid = vsid; |
262 | phte_physical[base + i].h = h; |
261 | phte_physical[base + i].h = h; |
263 | phte_physical[base + i].api = api; |
262 | phte_physical[base + i].api = api; |
264 | phte_physical[base + i].rpn = pfn; |
263 | phte_physical[base + i].rpn = pfn; |
265 | phte_physical[base + i].r = 0; |
264 | phte_physical[base + i].r = 0; |
266 | phte_physical[base + i].c = 0; |
265 | phte_physical[base + i].c = 0; |
267 | phte_physical[base + i].wimg = 0; |
266 | phte_physical[base + i].wimg = 0; |
268 | phte_physical[base + i].pp = 2; // FIXME |
267 | phte_physical[base + i].pp = 2; // FIXME |
269 | } |
268 | } |
270 | 269 | ||
271 | 270 | ||
272 | /** Process Instruction/Data Storage Interrupt |
271 | /** Process Instruction/Data Storage Interrupt |
273 | * |
272 | * |
274 | * @param n Interrupt vector number. |
273 | * @param n Interrupt vector number. |
275 | * @param istate Interrupted register context. |
274 | * @param istate Interrupted register context. |
276 | * |
275 | * |
277 | */ |
276 | */ |
278 | void pht_refill(int n, istate_t *istate) |
277 | void pht_refill(int n, istate_t *istate) |
279 | { |
278 | { |
280 | uintptr_t badvaddr; |
279 | uintptr_t badvaddr; |
281 | pte_t *pte; |
280 | pte_t *pte; |
282 | int pfrc; |
281 | int pfrc; |
283 | as_t *as; |
282 | as_t *as; |
284 | bool lock; |
283 | bool lock; |
285 | 284 | ||
286 | if (AS == NULL) { |
285 | if (AS == NULL) { |
287 | as = AS_KERNEL; |
286 | as = AS_KERNEL; |
288 | lock = false; |
287 | lock = false; |
289 | } else { |
288 | } else { |
290 | as = AS; |
289 | as = AS; |
291 | lock = true; |
290 | lock = true; |
292 | } |
291 | } |
293 | 292 | ||
294 | if (n == VECTOR_DATA_STORAGE) { |
293 | if (n == VECTOR_DATA_STORAGE) |
295 | asm volatile ( |
- | |
296 | "mfdar %0\n" |
- | |
297 | : "=r" (badvaddr) |
294 | badvaddr = istate->dar; |
298 | ); |
- | |
299 | } else |
295 | else |
300 | badvaddr = istate->pc; |
296 | badvaddr = istate->pc; |
301 | 297 | ||
302 | page_table_lock(as, lock); |
298 | page_table_lock(as, lock); |
303 | 299 | ||
304 | pte = find_mapping_and_check(as, lock, badvaddr, |
300 | pte = find_mapping_and_check(as, lock, badvaddr, |
305 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
301 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
306 | if (!pte) { |
302 | if (!pte) { |
307 | switch (pfrc) { |
303 | switch (pfrc) { |
308 | case AS_PF_FAULT: |
304 | case AS_PF_FAULT: |
309 | goto fail; |
305 | goto fail; |
310 | break; |
306 | break; |
311 | case AS_PF_DEFER: |
307 | case AS_PF_DEFER: |
312 | /* |
308 | /* |
313 | * The page fault came during copy_from_uspace() |
309 | * The page fault came during copy_from_uspace() |
314 | * or copy_to_uspace(). |
310 | * or copy_to_uspace(). |
315 | */ |
311 | */ |
316 | page_table_unlock(as, lock); |
312 | page_table_unlock(as, lock); |
317 | return; |
313 | return; |
318 | default: |
314 | default: |
319 | panic("Unexpected pfrc (%d).", pfrc); |
315 | panic("Unexpected pfrc (%d).", pfrc); |
320 | } |
316 | } |
321 | } |
317 | } |
322 | 318 | ||
323 | pte->accessed = 1; /* Record access to PTE */ |
319 | pte->accessed = 1; /* Record access to PTE */ |
324 | pht_insert(badvaddr, pte); |
320 | pht_insert(badvaddr, pte); |
325 | 321 | ||
326 | page_table_unlock(as, lock); |
322 | page_table_unlock(as, lock); |
327 | return; |
323 | return; |
328 | 324 | ||
329 | fail: |
325 | fail: |
330 | page_table_unlock(as, lock); |
326 | page_table_unlock(as, lock); |
331 | pht_refill_fail(badvaddr, istate); |
327 | pht_refill_fail(badvaddr, istate); |
332 | } |
328 | } |
333 | 329 | ||
334 | 330 | ||
335 | /** Process Instruction/Data Storage Interrupt in Real Mode |
331 | /** Process Instruction/Data Storage Interrupt in Real Mode |
336 | * |
332 | * |
337 | * @param n Interrupt vector number. |
333 | * @param n Interrupt vector number. |
338 | * @param istate Interrupted register context. |
334 | * @param istate Interrupted register context. |
339 | * |
335 | * |
340 | */ |
336 | */ |
341 | bool pht_real_refill(int n, istate_t *istate) |
337 | bool pht_real_refill(int n, istate_t *istate) |
342 | { |
338 | { |
343 | uintptr_t badvaddr; |
339 | uintptr_t badvaddr; |
344 | 340 | ||
345 | if (n == VECTOR_DATA_STORAGE) { |
341 | if (n == VECTOR_DATA_STORAGE) |
346 | asm volatile ( |
- | |
347 | "mfdar %0\n" |
- | |
348 | : "=r" (badvaddr) |
342 | badvaddr = istate->dar; |
349 | ); |
- | |
350 | } else |
343 | else |
351 | badvaddr = istate->pc; |
344 | badvaddr = istate->pc; |
352 | 345 | ||
353 | uint32_t physmem; |
346 | uint32_t physmem; |
354 | asm volatile ( |
347 | asm volatile ( |
355 | "mfsprg3 %0\n" |
348 | "mfsprg3 %0\n" |
356 | : "=r" (physmem) |
349 | : "=r" (physmem) |
357 | ); |
350 | ); |
358 | 351 | ||
359 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
352 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
360 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
353 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
361 | return true; |
354 | return true; |
362 | } |
355 | } |
363 | 356 | ||
364 | return false; |
357 | return false; |
365 | } |
358 | } |
366 | 359 | ||
367 | 360 | ||
368 | void tlb_arch_init(void) |
361 | void tlb_arch_init(void) |
369 | { |
362 | { |
370 | tlb_invalidate_all(); |
363 | tlb_invalidate_all(); |
371 | } |
364 | } |
372 | 365 | ||
373 | 366 | ||
374 | void tlb_invalidate_all(void) |
367 | void tlb_invalidate_all(void) |
375 | { |
368 | { |
376 | asm volatile ( |
369 | asm volatile ( |
377 | "tlbsync\n" |
370 | "tlbsync\n" |
378 | ); |
371 | ); |
379 | } |
372 | } |
380 | 373 | ||
381 | 374 | ||
382 | void tlb_invalidate_asid(asid_t asid) |
375 | void tlb_invalidate_asid(asid_t asid) |
383 | { |
376 | { |
384 | uint32_t sdr1; |
377 | uint32_t sdr1; |
385 | asm volatile ( |
378 | asm volatile ( |
386 | "mfsdr1 %0\n" |
379 | "mfsdr1 %0\n" |
387 | : "=r" (sdr1) |
380 | : "=r" (sdr1) |
388 | ); |
381 | ); |
389 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
382 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
390 | 383 | ||
391 | uint32_t i; |
384 | uint32_t i; |
392 | for (i = 0; i < 8192; i++) { |
385 | for (i = 0; i < 8192; i++) { |
393 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
386 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
394 | (phte[i].vsid < ((asid << 4) + 16))) |
387 | (phte[i].vsid < ((asid << 4) + 16))) |
395 | phte[i].v = 0; |
388 | phte[i].v = 0; |
396 | } |
389 | } |
397 | tlb_invalidate_all(); |
390 | tlb_invalidate_all(); |
398 | } |
391 | } |
399 | 392 | ||
400 | 393 | ||
401 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
394 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
402 | { |
395 | { |
403 | // TODO |
396 | // TODO |
404 | tlb_invalidate_all(); |
397 | tlb_invalidate_all(); |
405 | } |
398 | } |
406 | 399 | ||
407 | 400 | ||
408 | #define PRINT_BAT(name, ureg, lreg) \ |
401 | #define PRINT_BAT(name, ureg, lreg) \ |
409 | asm volatile ( \ |
402 | asm volatile ( \ |
410 | "mfspr %0," #ureg "\n" \ |
403 | "mfspr %0," #ureg "\n" \ |
411 | "mfspr %1," #lreg "\n" \ |
404 | "mfspr %1," #lreg "\n" \ |
412 | : "=r" (upper), "=r" (lower) \ |
405 | : "=r" (upper), "=r" (lower) \ |
413 | ); \ |
406 | ); \ |
414 | mask = (upper & 0x1ffc) >> 2; \ |
407 | mask = (upper & 0x1ffc) >> 2; \ |
415 | if (upper & 3) { \ |
408 | if (upper & 3) { \ |
416 | uint32_t tmp = mask; \ |
409 | uint32_t tmp = mask; \ |
417 | length = 128; \ |
410 | length = 128; \ |
418 | while (tmp) { \ |
411 | while (tmp) { \ |
419 | if ((tmp & 1) == 0) { \ |
412 | if ((tmp & 1) == 0) { \ |
420 | printf("ibat[0]: error in mask\n"); \ |
413 | printf("ibat[0]: error in mask\n"); \ |
421 | break; \ |
414 | break; \ |
422 | } \ |
415 | } \ |
423 | length <<= 1; \ |
416 | length <<= 1; \ |
424 | tmp >>= 1; \ |
417 | tmp >>= 1; \ |
425 | } \ |
418 | } \ |
426 | } else \ |
419 | } else \ |
427 | length = 0; \ |
420 | length = 0; \ |
428 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
421 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
429 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
422 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
430 | lower & 0xffff0000, length, mask, \ |
423 | lower & 0xffff0000, length, mask, \ |
431 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
424 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
432 | (upper & 1) ? " user" : ""); |
425 | (upper & 1) ? " user" : ""); |
433 | 426 | ||
434 | 427 | ||
435 | void tlb_print(void) |
428 | void tlb_print(void) |
436 | { |
429 | { |
437 | uint32_t sr; |
430 | uint32_t sr; |
438 | 431 | ||
439 | for (sr = 0; sr < 16; sr++) { |
432 | for (sr = 0; sr < 16; sr++) { |
440 | uint32_t vsid; |
433 | uint32_t vsid; |
441 | asm volatile ( |
434 | asm volatile ( |
442 | "mfsrin %0, %1\n" |
435 | "mfsrin %0, %1\n" |
443 | : "=r" (vsid) |
436 | : "=r" (vsid) |
444 | : "r" (sr << 28) |
437 | : "r" (sr << 28) |
445 | ); |
438 | ); |
446 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
439 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, |
447 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
440 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
448 | ((vsid >> 30) & 1) ? " supervisor" : "", |
441 | ((vsid >> 30) & 1) ? " supervisor" : "", |
449 | ((vsid >> 29) & 1) ? " user" : ""); |
442 | ((vsid >> 29) & 1) ? " user" : ""); |
450 | } |
443 | } |
451 | 444 | ||
452 | uint32_t upper; |
445 | uint32_t upper; |
453 | uint32_t lower; |
446 | uint32_t lower; |
454 | uint32_t mask; |
447 | uint32_t mask; |
455 | uint32_t length; |
448 | uint32_t length; |
456 | 449 | ||
457 | PRINT_BAT("ibat[0]", 528, 529); |
450 | PRINT_BAT("ibat[0]", 528, 529); |
458 | PRINT_BAT("ibat[1]", 530, 531); |
451 | PRINT_BAT("ibat[1]", 530, 531); |
459 | PRINT_BAT("ibat[2]", 532, 533); |
452 | PRINT_BAT("ibat[2]", 532, 533); |
460 | PRINT_BAT("ibat[3]", 534, 535); |
453 | PRINT_BAT("ibat[3]", 534, 535); |
461 | 454 | ||
462 | PRINT_BAT("dbat[0]", 536, 537); |
455 | PRINT_BAT("dbat[0]", 536, 537); |
463 | PRINT_BAT("dbat[1]", 538, 539); |
456 | PRINT_BAT("dbat[1]", 538, 539); |
464 | PRINT_BAT("dbat[2]", 540, 541); |
457 | PRINT_BAT("dbat[2]", 540, 541); |
465 | PRINT_BAT("dbat[3]", 542, 543); |
458 | PRINT_BAT("dbat[3]", 542, 543); |
466 | } |
459 | } |
467 | 460 | ||
468 | /** @} |
461 | /** @} |
469 | */ |
462 | */ |
470 | 463 |