WebSVN – HelenOS – Diff – /trunk/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
#include <macros.h>
 
 
static unsigned int seed = 10;
static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
 
 
#define TLB_FLUSH \
    "tlbie %0\n" \
    "addi %0, %0, 0x1000\n"
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->present)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->present));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        default:
            panic("Unexpected rc (%d).", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *str = get_symtab_entry(istate->pc);
    if (str)
        symbol = str;
    str = get_symtab_entry(istate->lr);
    if (str)
        sym2 = str;
 
    fault_if_from_uspace(istate,
        "PHT Refill Exception on %p.", badvaddr);
    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find colliding PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((phte[base + i].v)
            && (phte[base + i].vsid == vsid)
            && (phte[base + i].api == api)
            && (phte[base + i].h == 0)) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Find unused PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if (!phte[base + i].v) {
                found = true;
                break;
            }
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find colliding PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((phte[base2 + i].v)
                && (phte[base2 + i].vsid == vsid)
                && (phte[base2 + i].api == api)
                && (phte[base2 + i].h == 1)) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            /* Find unused PTE in PTEG */
            for (i = 0; i < 8; i++) {
                if (!phte[base2 + i].v) {
                    found = true;
                    base = base2;
                    h = 1;
                    break;
                }
            }
        }
       
        if (!found)
            i = RANDI(seed) % 8;
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pte->pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
    phte[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
   
    pte->accessed = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
bool pht_refill_real(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem)))
        return false;
   
    uint32_t page = (badvaddr >> 12) & 0xffff;
    uint32_t api = (badvaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (badvaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find colliding PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((phte_real[base + i].v)
            && (phte_real[base + i].vsid == vsid)
            && (phte_real[base + i].api == api)
            && (phte_real[base + i].h == 0)) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Find unused PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if (!phte_real[base + i].v) {
                found = true;
                break;
            }
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find colliding PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((phte_real[base2 + i].v)
                && (phte_real[base2 + i].vsid == vsid)
                && (phte_real[base2 + i].api == api)
                && (phte_real[base2 + i].h == 1)) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            /* Find unused PTE in PTEG */
            for (i = 0; i < 8; i++) {
                if (!phte_real[base2 + i].v) {
                    found = true;
                    base = base2;
                    h = 1;
                    break;
                }
            }
        }
       
        if (!found) {
            /* Use secondary hash to avoid collisions
               with usual PHT refill handler. */
            i = RANDI(seed_real) % 8;
            base = base2;
            h = 1;
        }
    }
   
    phte_real[base + i].v = 1;
    phte_real[base + i].vsid = vsid;
    phte_real[base + i].h = h;
    phte_real[base + i].api = api;
    phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
    phte_real[base + i].r = 0;
    phte_real[base + i].c = 0;
    phte_real[base + i].wimg = 0;
    phte_real[base + i].pp = 2; // FIXME
   
    return true;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    uint32_t index;
    asm volatile (
        "li %0, 0\n"
        "sync\n"
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
        TLB_FLUSH
       
        "eieio\n"
        "tlbsync\n"
        "sync\n"
        : "=r" (index)
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 3839	Rev 3856
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <interrupt.h>	38	#include <interrupt.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch.h>	40	#include <arch.h>
41	#include <print.h>	41	#include <print.h>
42	#include <symtab.h>	42	#include <symtab.h>
43	#include <macros.h>	43	#include <macros.h>
44		44
45		45
46	static unsigned int seed = 10;	46	static unsigned int seed = 10;
47	static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;	47	static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
48		48
49		49
-		50	#define TLB_FLUSH \
-		51	"tlbie %0\n" \
-		52	"addi %0, %0, 0x1000\n"
-		53
-		54
50	/** Try to find PTE for faulting address	55	/** Try to find PTE for faulting address
51	*	56	*
52	* Try to find PTE for faulting address.	57	* Try to find PTE for faulting address.
53	* The as->lock must be held on entry to this function	58	* The as->lock must be held on entry to this function
54	* if lock is true.	59	* if lock is true.
55	*	60	*
56	* @param as Address space.	61	* @param as Address space.
57	* @param lock Lock/unlock the address space.	62	* @param lock Lock/unlock the address space.
58	* @param badvaddr Faulting virtual address.	63	* @param badvaddr Faulting virtual address.
59	* @param access Access mode that caused the fault.	64	* @param access Access mode that caused the fault.
60	* @param istate Pointer to interrupted state.	65	* @param istate Pointer to interrupted state.
61	* @param pfrc Pointer to variable where as_page_fault() return code	66	* @param pfrc Pointer to variable where as_page_fault() return code
62	* will be stored.	67	* will be stored.
63	* @return PTE on success, NULL otherwise.	68	* @return PTE on success, NULL otherwise.
64	*	69	*
65	*/	70	*/
66	static pte_t *	71	static pte_t *
67	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,	72	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
68	istate_t istate, int pfrc)	73	istate_t istate, int pfrc)
69	{	74	{
70	/*	75	/*
71	* Check if the mapping exists in page tables.	76	* Check if the mapping exists in page tables.
72	*/	77	*/
73	pte_t *pte = page_mapping_find(as, badvaddr);	78	pte_t *pte = page_mapping_find(as, badvaddr);
74	if ((pte) && (pte->present)) {	79	if ((pte) && (pte->present)) {
75	/*	80	/*
76	* Mapping found in page tables.	81	* Mapping found in page tables.
77	* Immediately succeed.	82	* Immediately succeed.
78	*/	83	*/
79	return pte;	84	return pte;
80	} else {	85	} else {
81	int rc;	86	int rc;
82		87
83	/*	88	/*
84	* Mapping not found in page tables.	89	* Mapping not found in page tables.
85	* Resort to higher-level page fault handler.	90	* Resort to higher-level page fault handler.
86	*/	91	*/
87	page_table_unlock(as, lock);	92	page_table_unlock(as, lock);
88	switch (rc = as_page_fault(badvaddr, access, istate)) {	93	switch (rc = as_page_fault(badvaddr, access, istate)) {
89	case AS_PF_OK:	94	case AS_PF_OK:
90	/*	95	/*
91	* The higher-level page fault handler succeeded,	96	* The higher-level page fault handler succeeded,
92	* The mapping ought to be in place.	97	* The mapping ought to be in place.
93	*/	98	*/
94	page_table_lock(as, lock);	99	page_table_lock(as, lock);
95	pte = page_mapping_find(as, badvaddr);	100	pte = page_mapping_find(as, badvaddr);
96	ASSERT((pte) && (pte->present));	101	ASSERT((pte) && (pte->present));
97	*pfrc = 0;	102	*pfrc = 0;
98	return pte;	103	return pte;
99	case AS_PF_DEFER:	104	case AS_PF_DEFER:
100	page_table_lock(as, lock);	105	page_table_lock(as, lock);
101	*pfrc = rc;	106	*pfrc = rc;
102	return NULL;	107	return NULL;
103	case AS_PF_FAULT:	108	case AS_PF_FAULT:
104	page_table_lock(as, lock);	109	page_table_lock(as, lock);
105	*pfrc = rc;	110	*pfrc = rc;
106	return NULL;	111	return NULL;
107	default:	112	default:
108	panic("Unexpected rc (%d).", rc);	113	panic("Unexpected rc (%d).", rc);
109	}	114	}
110	}	115	}
111	}	116	}
112		117
113		118
114	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	119	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
115	{	120	{
116	char *symbol = "";	121	char *symbol = "";
117	char *sym2 = "";	122	char *sym2 = "";
118		123
119	char *str = get_symtab_entry(istate->pc);	124	char *str = get_symtab_entry(istate->pc);
120	if (str)	125	if (str)
121	symbol = str;	126	symbol = str;
122	str = get_symtab_entry(istate->lr);	127	str = get_symtab_entry(istate->lr);
123	if (str)	128	if (str)
124	sym2 = str;	129	sym2 = str;
125		130
126	fault_if_from_uspace(istate,	131	fault_if_from_uspace(istate,
127	"PHT Refill Exception on %p.", badvaddr);	132	"PHT Refill Exception on %p.", badvaddr);
128	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,	133	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
129	istate->pc, symbol, sym2);	134	istate->pc, symbol, sym2);
130	}	135	}
131		136
132		137
133	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)	138	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
134	{	139	{
135	uint32_t page = (vaddr >> 12) & 0xffff;	140	uint32_t page = (vaddr >> 12) & 0xffff;
136	uint32_t api = (vaddr >> 22) & 0x3f;	141	uint32_t api = (vaddr >> 22) & 0x3f;
137		142
138	uint32_t vsid;	143	uint32_t vsid;
139	asm volatile (	144	asm volatile (
140	"mfsrin %0, %1\n"	145	"mfsrin %0, %1\n"
141	: "=r" (vsid)	146	: "=r" (vsid)
142	: "r" (vaddr)	147	: "r" (vaddr)
143	);	148	);
144		149
145	uint32_t sdr1;	150	uint32_t sdr1;
146	asm volatile (	151	asm volatile (
147	"mfsdr1 %0\n"	152	"mfsdr1 %0\n"
148	: "=r" (sdr1)	153	: "=r" (sdr1)
149	);	154	);
150	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	155	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
151		156
152	/* Primary hash (xor) */	157	/* Primary hash (xor) */
153	uint32_t h = 0;	158	uint32_t h = 0;
154	uint32_t hash = vsid ^ page;	159	uint32_t hash = vsid ^ page;
155	uint32_t base = (hash & 0x3ff) << 3;	160	uint32_t base = (hash & 0x3ff) << 3;
156	uint32_t i;	161	uint32_t i;
157	bool found = false;	162	bool found = false;
158		163
159	/* Find colliding PTE in PTEG */	164	/* Find colliding PTE in PTEG */
160	for (i = 0; i < 8; i++) {	165	for (i = 0; i < 8; i++) {
161	if ((phte[base + i].v)	166	if ((phte[base + i].v)
162	&& (phte[base + i].vsid == vsid)	167	&& (phte[base + i].vsid == vsid)
163	&& (phte[base + i].api == api)	168	&& (phte[base + i].api == api)
164	&& (phte[base + i].h == 0)) {	169	&& (phte[base + i].h == 0)) {
165	found = true;	170	found = true;
166	break;	171	break;
167	}	172	}
168	}	173	}
169		174
170	if (!found) {	175	if (!found) {
171	/* Find unused PTE in PTEG */	176	/* Find unused PTE in PTEG */
172	for (i = 0; i < 8; i++) {	177	for (i = 0; i < 8; i++) {
173	if (!phte[base + i].v) {	178	if (!phte[base + i].v) {
174	found = true;	179	found = true;
175	break;	180	break;
176	}	181	}
177	}	182	}
178	}	183	}
179		184
180	if (!found) {	185	if (!found) {
181	/* Secondary hash (not) */	186	/* Secondary hash (not) */
182	uint32_t base2 = (~hash & 0x3ff) << 3;	187	uint32_t base2 = (~hash & 0x3ff) << 3;
183		188
184	/* Find colliding PTE in PTEG */	189	/* Find colliding PTE in PTEG */
185	for (i = 0; i < 8; i++) {	190	for (i = 0; i < 8; i++) {
186	if ((phte[base2 + i].v)	191	if ((phte[base2 + i].v)
187	&& (phte[base2 + i].vsid == vsid)	192	&& (phte[base2 + i].vsid == vsid)
188	&& (phte[base2 + i].api == api)	193	&& (phte[base2 + i].api == api)
189	&& (phte[base2 + i].h == 1)) {	194	&& (phte[base2 + i].h == 1)) {
190	found = true;	195	found = true;
191	base = base2;	196	base = base2;
192	h = 1;	197	h = 1;
193	break;	198	break;
194	}	199	}
195	}	200	}
196		201
197	if (!found) {	202	if (!found) {
198	/* Find unused PTE in PTEG */	203	/* Find unused PTE in PTEG */
199	for (i = 0; i < 8; i++) {	204	for (i = 0; i < 8; i++) {
200	if (!phte[base2 + i].v) {	205	if (!phte[base2 + i].v) {
201	found = true;	206	found = true;
202	base = base2;	207	base = base2;
203	h = 1;	208	h = 1;
204	break;	209	break;
205	}	210	}
206	}	211	}
207	}	212	}
208		213
209	if (!found)	214	if (!found)
210	i = RANDI(seed) % 8;	215	i = RANDI(seed) % 8;
211	}	216	}
212		217
213	phte[base + i].v = 1;	218	phte[base + i].v = 1;
214	phte[base + i].vsid = vsid;	219	phte[base + i].vsid = vsid;
215	phte[base + i].h = h;	220	phte[base + i].h = h;
216	phte[base + i].api = api;	221	phte[base + i].api = api;
217	phte[base + i].rpn = pte->pfn;	222	phte[base + i].rpn = pte->pfn;
218	phte[base + i].r = 0;	223	phte[base + i].r = 0;
219	phte[base + i].c = 0;	224	phte[base + i].c = 0;
220	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);	225	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
221	phte[base + i].pp = 2; // FIXME	226	phte[base + i].pp = 2; // FIXME
222	}	227	}
223		228
224		229
225	/** Process Instruction/Data Storage Interrupt	230	/** Process Instruction/Data Storage Interrupt
226	*	231	*
227	* @param n Interrupt vector number.	232	* @param n Interrupt vector number.
228	* @param istate Interrupted register context.	233	* @param istate Interrupted register context.
229	*	234	*
230	*/	235	*/
231	void pht_refill(int n, istate_t *istate)	236	void pht_refill(int n, istate_t *istate)
232	{	237	{
233	uintptr_t badvaddr;	238	uintptr_t badvaddr;
234	pte_t *pte;	239	pte_t *pte;
235	int pfrc;	240	int pfrc;
236	as_t *as;	241	as_t *as;
237	bool lock;	242	bool lock;
238		243
239	if (AS == NULL) {	244	if (AS == NULL) {
240	as = AS_KERNEL;	245	as = AS_KERNEL;
241	lock = false;	246	lock = false;
242	} else {	247	} else {
243	as = AS;	248	as = AS;
244	lock = true;	249	lock = true;
245	}	250	}
246		251
247	if (n == VECTOR_DATA_STORAGE)	252	if (n == VECTOR_DATA_STORAGE)
248	badvaddr = istate->dar;	253	badvaddr = istate->dar;
249	else	254	else
250	badvaddr = istate->pc;	255	badvaddr = istate->pc;
251		256
252	page_table_lock(as, lock);	257	page_table_lock(as, lock);
253		258
254	pte = find_mapping_and_check(as, lock, badvaddr,	259	pte = find_mapping_and_check(as, lock, badvaddr,
255	PF_ACCESS_READ /* FIXME */, istate, &pfrc);	260	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
256	if (!pte) {	261	if (!pte) {
257	switch (pfrc) {	262	switch (pfrc) {
258	case AS_PF_FAULT:	263	case AS_PF_FAULT:
259	goto fail;	264	goto fail;
260	break;	265	break;
261	case AS_PF_DEFER:	266	case AS_PF_DEFER:
262	/*	267	/*
263	* The page fault came during copy_from_uspace()	268	* The page fault came during copy_from_uspace()
264	* or copy_to_uspace().	269	* or copy_to_uspace().
265	*/	270	*/
266	page_table_unlock(as, lock);	271	page_table_unlock(as, lock);
267	return;	272	return;
268	default:	273	default:
269	panic("Unexpected pfrc (%d).", pfrc);	274	panic("Unexpected pfrc (%d).", pfrc);
270	}	275	}
271	}	276	}
272		277
273	pte->accessed = 1; /* Record access to PTE */	278	pte->accessed = 1; /* Record access to PTE */
274	pht_insert(badvaddr, pte);	279	pht_insert(badvaddr, pte);
275		280
276	page_table_unlock(as, lock);	281	page_table_unlock(as, lock);
277	return;	282	return;
278		283
279	fail:	284	fail:
280	page_table_unlock(as, lock);	285	page_table_unlock(as, lock);
281	pht_refill_fail(badvaddr, istate);	286	pht_refill_fail(badvaddr, istate);
282	}	287	}
283		288
284		289
285	/** Process Instruction/Data Storage Interrupt in Real Mode	290	/** Process Instruction/Data Storage Interrupt in Real Mode
286	*	291	*
287	* @param n Interrupt vector number.	292	* @param n Interrupt vector number.
288	* @param istate Interrupted register context.	293	* @param istate Interrupted register context.
289	*	294	*
290	*/	295	*/
291	bool pht_refill_real(int n, istate_t *istate)	296	bool pht_refill_real(int n, istate_t *istate)
292	{	297	{
293	uintptr_t badvaddr;	298	uintptr_t badvaddr;
294		299
295	if (n == VECTOR_DATA_STORAGE)	300	if (n == VECTOR_DATA_STORAGE)
296	badvaddr = istate->dar;	301	badvaddr = istate->dar;
297	else	302	else
298	badvaddr = istate->pc;	303	badvaddr = istate->pc;
299		304
300	uint32_t physmem;	305	uint32_t physmem;
301	asm volatile (	306	asm volatile (
302	"mfsprg3 %0\n"	307	"mfsprg3 %0\n"
303	: "=r" (physmem)	308	: "=r" (physmem)
304	);	309	);
305		310
306	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))	311	if ((badvaddr < PA2KA(0)) \|\| (badvaddr >= PA2KA(physmem)))
307	return false;	312	return false;
308		313
309	uint32_t page = (badvaddr >> 12) & 0xffff;	314	uint32_t page = (badvaddr >> 12) & 0xffff;
310	uint32_t api = (badvaddr >> 22) & 0x3f;	315	uint32_t api = (badvaddr >> 22) & 0x3f;
311		316
312	uint32_t vsid;	317	uint32_t vsid;
313	asm volatile (	318	asm volatile (
314	"mfsrin %0, %1\n"	319	"mfsrin %0, %1\n"
315	: "=r" (vsid)	320	: "=r" (vsid)
316	: "r" (badvaddr)	321	: "r" (badvaddr)
317	);	322	);
318		323
319	uint32_t sdr1;	324	uint32_t sdr1;
320	asm volatile (	325	asm volatile (
321	"mfsdr1 %0\n"	326	"mfsdr1 %0\n"
322	: "=r" (sdr1)	327	: "=r" (sdr1)
323	);	328	);
324	phte_t phte_real = (phte_t ) (sdr1 & 0xffff0000);	329	phte_t phte_real = (phte_t ) (sdr1 & 0xffff0000);
325		330
326	/* Primary hash (xor) */	331	/* Primary hash (xor) */
327	uint32_t h = 0;	332	uint32_t h = 0;
328	uint32_t hash = vsid ^ page;	333	uint32_t hash = vsid ^ page;
329	uint32_t base = (hash & 0x3ff) << 3;	334	uint32_t base = (hash & 0x3ff) << 3;
330	uint32_t i;	335	uint32_t i;
331	bool found = false;	336	bool found = false;
332		337
333	/* Find colliding PTE in PTEG */	338	/* Find colliding PTE in PTEG */
334	for (i = 0; i < 8; i++) {	339	for (i = 0; i < 8; i++) {
335	if ((phte_real[base + i].v)	340	if ((phte_real[base + i].v)
336	&& (phte_real[base + i].vsid == vsid)	341	&& (phte_real[base + i].vsid == vsid)
337	&& (phte_real[base + i].api == api)	342	&& (phte_real[base + i].api == api)
338	&& (phte_real[base + i].h == 0)) {	343	&& (phte_real[base + i].h == 0)) {
339	found = true;	344	found = true;
340	break;	345	break;
341	}	346	}
342	}	347	}
343		348
344	if (!found) {	349	if (!found) {
345	/* Find unused PTE in PTEG */	350	/* Find unused PTE in PTEG */
346	for (i = 0; i < 8; i++) {	351	for (i = 0; i < 8; i++) {
347	if (!phte_real[base + i].v) {	352	if (!phte_real[base + i].v) {
348	found = true;	353	found = true;
349	break;	354	break;
350	}	355	}
351	}	356	}
352	}	357	}
353		358
354	if (!found) {	359	if (!found) {
355	/* Secondary hash (not) */	360	/* Secondary hash (not) */
356	uint32_t base2 = (~hash & 0x3ff) << 3;	361	uint32_t base2 = (~hash & 0x3ff) << 3;
357		362
358	/* Find colliding PTE in PTEG */	363	/* Find colliding PTE in PTEG */
359	for (i = 0; i < 8; i++) {	364	for (i = 0; i < 8; i++) {
360	if ((phte_real[base2 + i].v)	365	if ((phte_real[base2 + i].v)
361	&& (phte_real[base2 + i].vsid == vsid)	366	&& (phte_real[base2 + i].vsid == vsid)
362	&& (phte_real[base2 + i].api == api)	367	&& (phte_real[base2 + i].api == api)
363	&& (phte_real[base2 + i].h == 1)) {	368	&& (phte_real[base2 + i].h == 1)) {
364	found = true;	369	found = true;
365	base = base2;	370	base = base2;
366	h = 1;	371	h = 1;
367	break;	372	break;
368	}	373	}
369	}	374	}
370		375
371	if (!found) {	376	if (!found) {
372	/* Find unused PTE in PTEG */	377	/* Find unused PTE in PTEG */
373	for (i = 0; i < 8; i++) {	378	for (i = 0; i < 8; i++) {
374	if (!phte_real[base2 + i].v) {	379	if (!phte_real[base2 + i].v) {
375	found = true;	380	found = true;
376	base = base2;	381	base = base2;
377	h = 1;	382	h = 1;
378	break;	383	break;
379	}	384	}
380	}	385	}
381	}	386	}
382		387
383	if (!found) {	388	if (!found) {
384	/* Use secondary hash to avoid collisions	389	/* Use secondary hash to avoid collisions
385	with usual PHT refill handler. */	390	with usual PHT refill handler. */
386	i = RANDI(seed_real) % 8;	391	i = RANDI(seed_real) % 8;
387	base = base2;	392	base = base2;
388	h = 1;	393	h = 1;
389	}	394	}
390	}	395	}
391		396
392	phte_real[base + i].v = 1;	397	phte_real[base + i].v = 1;
393	phte_real[base + i].vsid = vsid;	398	phte_real[base + i].vsid = vsid;
394	phte_real[base + i].h = h;	399	phte_real[base + i].h = h;
395	phte_real[base + i].api = api;	400	phte_real[base + i].api = api;
396	phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;	401	phte_real[base + i].rpn = KA2PA(badvaddr) >> 12;
397	phte_real[base + i].r = 0;	402	phte_real[base + i].r = 0;
398	phte_real[base + i].c = 0;	403	phte_real[base + i].c = 0;
399	phte_real[base + i].wimg = 0;	404	phte_real[base + i].wimg = 0;
400	phte_real[base + i].pp = 2; // FIXME	405	phte_real[base + i].pp = 2; // FIXME
401		406
402	return true;	407	return true;
403	}	408	}
404		409
405		410
406	void tlb_arch_init(void)	411	void tlb_arch_init(void)
407	{	412	{
408	tlb_invalidate_all();	413	tlb_invalidate_all();
409	}	414	}
410		415
411		416
412	void tlb_invalidate_all(void)	417	void tlb_invalidate_all(void)
413	{	418	{
-		419	uint32_t index;
414	asm volatile (	420	asm volatile (
-		421	"li %0, 0\n"
-		422	"sync\n"
-		423
-		424	TLB_FLUSH
-		425	TLB_FLUSH
-		426	TLB_FLUSH
-		427	TLB_FLUSH
-		428	TLB_FLUSH
-		429	TLB_FLUSH
-		430	TLB_FLUSH
-		431	TLB_FLUSH
-		432
-		433	TLB_FLUSH
-		434	TLB_FLUSH
-		435	TLB_FLUSH
-		436	TLB_FLUSH
-		437	TLB_FLUSH
-		438	TLB_FLUSH
-		439	TLB_FLUSH
-		440	TLB_FLUSH
-		441
-		442	TLB_FLUSH
-		443	TLB_FLUSH
-		444	TLB_FLUSH
-		445	TLB_FLUSH
-		446	TLB_FLUSH
-		447	TLB_FLUSH
-		448	TLB_FLUSH
-		449	TLB_FLUSH
-		450
-		451	TLB_FLUSH
-		452	TLB_FLUSH
-		453	TLB_FLUSH
-		454	TLB_FLUSH
-		455	TLB_FLUSH
-		456	TLB_FLUSH
-		457	TLB_FLUSH
-		458	TLB_FLUSH
-		459
-		460	TLB_FLUSH
-		461	TLB_FLUSH
-		462	TLB_FLUSH
-		463	TLB_FLUSH
-		464	TLB_FLUSH
-		465	TLB_FLUSH
-		466	TLB_FLUSH
-		467	TLB_FLUSH
-		468
-		469	TLB_FLUSH
-		470	TLB_FLUSH
-		471	TLB_FLUSH
-		472	TLB_FLUSH
-		473	TLB_FLUSH
-		474	TLB_FLUSH
-		475	TLB_FLUSH
-		476	TLB_FLUSH
-		477
-		478	TLB_FLUSH
-		479	TLB_FLUSH
-		480	TLB_FLUSH
-		481	TLB_FLUSH
-		482	TLB_FLUSH
-		483	TLB_FLUSH
-		484	TLB_FLUSH
-		485	TLB_FLUSH
-		486
-		487	TLB_FLUSH
-		488	TLB_FLUSH
-		489	TLB_FLUSH
-		490	TLB_FLUSH
-		491	TLB_FLUSH
-		492	TLB_FLUSH
-		493	TLB_FLUSH
-		494	TLB_FLUSH
-		495
-		496	"eieio\n"
415	"tlbsync\n"	497	"tlbsync\n"
-		498	"sync\n"
-		499	: "=r" (index)
416	);	500	);

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ppc32/src/mm/tlb.c @ 3857 – Rev 3839 → 3856