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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <symtab.h> |
42 | #include <symtab.h> |
- | 43 | #include <macros.h> |
|
43 | 44 | ||
44 | 45 | ||
45 | static unsigned int seed = 10; |
46 | static unsigned int seed = 10; |
46 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
47 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
47 | 48 | ||
48 | 49 | ||
49 | /** Try to find PTE for faulting address |
50 | /** Try to find PTE for faulting address |
50 | * |
51 | * |
51 | * Try to find PTE for faulting address. |
52 | * Try to find PTE for faulting address. |
52 | * The as->lock must be held on entry to this function |
53 | * The as->lock must be held on entry to this function |
53 | * if lock is true. |
54 | * if lock is true. |
54 | * |
55 | * |
55 | * @param as Address space. |
56 | * @param as Address space. |
56 | * @param lock Lock/unlock the address space. |
57 | * @param lock Lock/unlock the address space. |
57 | * @param badvaddr Faulting virtual address. |
58 | * @param badvaddr Faulting virtual address. |
58 | * @param access Access mode that caused the fault. |
59 | * @param access Access mode that caused the fault. |
59 | * @param istate Pointer to interrupted state. |
60 | * @param istate Pointer to interrupted state. |
60 | * @param pfrc Pointer to variable where as_page_fault() return code |
61 | * @param pfrc Pointer to variable where as_page_fault() return code |
61 | * will be stored. |
62 | * will be stored. |
62 | * @return PTE on success, NULL otherwise. |
63 | * @return PTE on success, NULL otherwise. |
63 | * |
64 | * |
64 | */ |
65 | */ |
65 | static pte_t * |
66 | static pte_t * |
66 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
67 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
67 | istate_t *istate, int *pfrc) |
68 | istate_t *istate, int *pfrc) |
68 | { |
69 | { |
69 | /* |
70 | /* |
70 | * Check if the mapping exists in page tables. |
71 | * Check if the mapping exists in page tables. |
71 | */ |
72 | */ |
72 | pte_t *pte = page_mapping_find(as, badvaddr); |
73 | pte_t *pte = page_mapping_find(as, badvaddr); |
73 | if ((pte) && (pte->present)) { |
74 | if ((pte) && (pte->present)) { |
74 | /* |
75 | /* |
75 | * Mapping found in page tables. |
76 | * Mapping found in page tables. |
76 | * Immediately succeed. |
77 | * Immediately succeed. |
77 | */ |
78 | */ |
78 | return pte; |
79 | return pte; |
79 | } else { |
80 | } else { |
80 | int rc; |
81 | int rc; |
81 | 82 | ||
82 | /* |
83 | /* |
83 | * Mapping not found in page tables. |
84 | * Mapping not found in page tables. |
84 | * Resort to higher-level page fault handler. |
85 | * Resort to higher-level page fault handler. |
85 | */ |
86 | */ |
86 | page_table_unlock(as, lock); |
87 | page_table_unlock(as, lock); |
87 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
88 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
88 | case AS_PF_OK: |
89 | case AS_PF_OK: |
89 | /* |
90 | /* |
90 | * The higher-level page fault handler succeeded, |
91 | * The higher-level page fault handler succeeded, |
91 | * The mapping ought to be in place. |
92 | * The mapping ought to be in place. |
92 | */ |
93 | */ |
93 | page_table_lock(as, lock); |
94 | page_table_lock(as, lock); |
94 | pte = page_mapping_find(as, badvaddr); |
95 | pte = page_mapping_find(as, badvaddr); |
95 | ASSERT((pte) && (pte->present)); |
96 | ASSERT((pte) && (pte->present)); |
96 | *pfrc = 0; |
97 | *pfrc = 0; |
97 | return pte; |
98 | return pte; |
98 | case AS_PF_DEFER: |
99 | case AS_PF_DEFER: |
99 | page_table_lock(as, lock); |
100 | page_table_lock(as, lock); |
100 | *pfrc = rc; |
101 | *pfrc = rc; |
101 | return NULL; |
102 | return NULL; |
102 | case AS_PF_FAULT: |
103 | case AS_PF_FAULT: |
103 | page_table_lock(as, lock); |
104 | page_table_lock(as, lock); |
104 | *pfrc = rc; |
105 | *pfrc = rc; |
105 | return NULL; |
106 | return NULL; |
106 | default: |
107 | default: |
107 | panic("Unexpected rc (%d).", rc); |
108 | panic("Unexpected rc (%d).", rc); |
108 | } |
109 | } |
109 | } |
110 | } |
110 | } |
111 | } |
111 | 112 | ||
112 | 113 | ||
113 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
114 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
114 | { |
115 | { |
115 | char *symbol = ""; |
116 | char *symbol = ""; |
116 | char *sym2 = ""; |
117 | char *sym2 = ""; |
117 | 118 | ||
118 | char *str = get_symtab_entry(istate->pc); |
119 | char *str = get_symtab_entry(istate->pc); |
119 | if (str) |
120 | if (str) |
120 | symbol = str; |
121 | symbol = str; |
121 | str = get_symtab_entry(istate->lr); |
122 | str = get_symtab_entry(istate->lr); |
122 | if (str) |
123 | if (str) |
123 | sym2 = str; |
124 | sym2 = str; |
124 | 125 | ||
125 | fault_if_from_uspace(istate, |
126 | fault_if_from_uspace(istate, |
126 | "PHT Refill Exception on %p.", badvaddr); |
127 | "PHT Refill Exception on %p.", badvaddr); |
127 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
128 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
128 | istate->pc, symbol, sym2); |
129 | istate->pc, symbol, sym2); |
129 | } |
130 | } |
130 | 131 | ||
131 | - | ||
132 | /** Pseudorandom generator |
- | |
133 | * |
- | |
134 | * A pretty standard linear congruential pseudorandom |
- | |
135 | * number generator (m = 2^32). |
- | |
136 | * |
- | |
137 | */ |
- | |
138 | #define RANDI(seed) \ |
- | |
139 | ({ \ |
- | |
140 | (seed) = 1103515245 * (seed) + 12345; \ |
- | |
141 | (seed); \ |
- | |
142 | }) |
- | |
143 | - | ||
144 | 132 | ||
145 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
133 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
146 | { |
134 | { |
147 | uint32_t page = (vaddr >> 12) & 0xffff; |
135 | uint32_t page = (vaddr >> 12) & 0xffff; |
148 | uint32_t api = (vaddr >> 22) & 0x3f; |
136 | uint32_t api = (vaddr >> 22) & 0x3f; |
149 | 137 | ||
150 | uint32_t vsid; |
138 | uint32_t vsid; |
151 | asm volatile ( |
139 | asm volatile ( |
152 | "mfsrin %0, %1\n" |
140 | "mfsrin %0, %1\n" |
153 | : "=r" (vsid) |
141 | : "=r" (vsid) |
154 | : "r" (vaddr) |
142 | : "r" (vaddr) |
155 | ); |
143 | ); |
156 | 144 | ||
157 | uint32_t sdr1; |
145 | uint32_t sdr1; |
158 | asm volatile ( |
146 | asm volatile ( |
159 | "mfsdr1 %0\n" |
147 | "mfsdr1 %0\n" |
160 | : "=r" (sdr1) |
148 | : "=r" (sdr1) |
161 | ); |
149 | ); |
162 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
150 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
163 | 151 | ||
164 | /* Primary hash (xor) */ |
152 | /* Primary hash (xor) */ |
165 | uint32_t h = 0; |
153 | uint32_t h = 0; |
166 | uint32_t hash = vsid ^ page; |
154 | uint32_t hash = vsid ^ page; |
167 | uint32_t base = (hash & 0x3ff) << 3; |
155 | uint32_t base = (hash & 0x3ff) << 3; |
168 | uint32_t i; |
156 | uint32_t i; |
169 | bool found = false; |
157 | bool found = false; |
170 | 158 | ||
171 | /* Find unused or colliding PTE in PTEG */ |
159 | /* Find unused or colliding PTE in PTEG */ |
172 | for (i = 0; i < 8; i++) { |
160 | for (i = 0; i < 8; i++) { |
173 | if ((!phte[base + i].v) || |
161 | if ((!phte[base + i].v) || |
174 | ((phte[base + i].vsid == vsid) |
162 | ((phte[base + i].vsid == vsid) |
175 | && (phte[base + i].api == api) |
163 | && (phte[base + i].api == api) |
176 | && (phte[base + i].h == 0))) { |
164 | && (phte[base + i].h == 0))) { |
177 | found = true; |
165 | found = true; |
178 | break; |
166 | break; |
179 | } |
167 | } |
180 | } |
168 | } |
181 | 169 | ||
182 | if (!found) { |
170 | if (!found) { |
183 | /* Secondary hash (not) */ |
171 | /* Secondary hash (not) */ |
184 | uint32_t base2 = (~hash & 0x3ff) << 3; |
172 | uint32_t base2 = (~hash & 0x3ff) << 3; |
185 | 173 | ||
186 | /* Find unused or colliding PTE in PTEG */ |
174 | /* Find unused or colliding PTE in PTEG */ |
187 | for (i = 0; i < 8; i++) { |
175 | for (i = 0; i < 8; i++) { |
188 | if ((!phte[base2 + i].v) || |
176 | if ((!phte[base2 + i].v) || |
189 | ((phte[base2 + i].vsid == vsid) |
177 | ((phte[base2 + i].vsid == vsid) |
190 | && (phte[base2 + i].api == api) |
178 | && (phte[base2 + i].api == api) |
191 | && (phte[base2 + i].h == 1))) { |
179 | && (phte[base2 + i].h == 1))) { |
192 | found = true; |
180 | found = true; |
193 | base = base2; |
181 | base = base2; |
194 | h = 1; |
182 | h = 1; |
195 | break; |
183 | break; |
196 | } |
184 | } |
197 | } |
185 | } |
198 | 186 | ||
199 | if (!found) |
187 | if (!found) |
200 | i = RANDI(seed) % 8; |
188 | i = RANDI(seed) % 8; |
201 | } |
189 | } |
202 | 190 | ||
203 | phte[base + i].v = 1; |
191 | phte[base + i].v = 1; |
204 | phte[base + i].vsid = vsid; |
192 | phte[base + i].vsid = vsid; |
205 | phte[base + i].h = h; |
193 | phte[base + i].h = h; |
206 | phte[base + i].api = api; |
194 | phte[base + i].api = api; |
207 | phte[base + i].rpn = pte->pfn; |
195 | phte[base + i].rpn = pte->pfn; |
208 | phte[base + i].r = 0; |
196 | phte[base + i].r = 0; |
209 | phte[base + i].c = 0; |
197 | phte[base + i].c = 0; |
210 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
198 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
211 | phte[base + i].pp = 2; // FIXME |
199 | phte[base + i].pp = 2; // FIXME |
212 | } |
200 | } |
213 | 201 | ||
214 | 202 | ||
215 | /** Process Instruction/Data Storage Interrupt |
203 | /** Process Instruction/Data Storage Interrupt |
216 | * |
204 | * |
217 | * @param n Interrupt vector number. |
205 | * @param n Interrupt vector number. |
218 | * @param istate Interrupted register context. |
206 | * @param istate Interrupted register context. |
219 | * |
207 | * |
220 | */ |
208 | */ |
221 | void pht_refill(int n, istate_t *istate) |
209 | void pht_refill(int n, istate_t *istate) |
222 | { |
210 | { |
223 | uintptr_t badvaddr; |
211 | uintptr_t badvaddr; |
224 | pte_t *pte; |
212 | pte_t *pte; |
225 | int pfrc; |
213 | int pfrc; |
226 | as_t *as; |
214 | as_t *as; |
227 | bool lock; |
215 | bool lock; |
228 | 216 | ||
229 | if (AS == NULL) { |
217 | if (AS == NULL) { |
230 | as = AS_KERNEL; |
218 | as = AS_KERNEL; |
231 | lock = false; |
219 | lock = false; |
232 | } else { |
220 | } else { |
233 | as = AS; |
221 | as = AS; |
234 | lock = true; |
222 | lock = true; |
235 | } |
223 | } |
236 | 224 | ||
237 | if (n == VECTOR_DATA_STORAGE) |
225 | if (n == VECTOR_DATA_STORAGE) |
238 | badvaddr = istate->dar; |
226 | badvaddr = istate->dar; |
239 | else |
227 | else |
240 | badvaddr = istate->pc; |
228 | badvaddr = istate->pc; |
241 | 229 | ||
242 | page_table_lock(as, lock); |
230 | page_table_lock(as, lock); |
243 | 231 | ||
244 | pte = find_mapping_and_check(as, lock, badvaddr, |
232 | pte = find_mapping_and_check(as, lock, badvaddr, |
245 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
233 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
246 | if (!pte) { |
234 | if (!pte) { |
247 | switch (pfrc) { |
235 | switch (pfrc) { |
248 | case AS_PF_FAULT: |
236 | case AS_PF_FAULT: |
249 | goto fail; |
237 | goto fail; |
250 | break; |
238 | break; |
251 | case AS_PF_DEFER: |
239 | case AS_PF_DEFER: |
252 | /* |
240 | /* |
253 | * The page fault came during copy_from_uspace() |
241 | * The page fault came during copy_from_uspace() |
254 | * or copy_to_uspace(). |
242 | * or copy_to_uspace(). |
255 | */ |
243 | */ |
256 | page_table_unlock(as, lock); |
244 | page_table_unlock(as, lock); |
257 | return; |
245 | return; |
258 | default: |
246 | default: |
259 | panic("Unexpected pfrc (%d).", pfrc); |
247 | panic("Unexpected pfrc (%d).", pfrc); |
260 | } |
248 | } |
261 | } |
249 | } |
262 | 250 | ||
263 | pte->accessed = 1; /* Record access to PTE */ |
251 | pte->accessed = 1; /* Record access to PTE */ |
264 | pht_insert(badvaddr, pte); |
252 | pht_insert(badvaddr, pte); |
265 | 253 | ||
266 | page_table_unlock(as, lock); |
254 | page_table_unlock(as, lock); |
267 | return; |
255 | return; |
268 | 256 | ||
269 | fail: |
257 | fail: |
270 | page_table_unlock(as, lock); |
258 | page_table_unlock(as, lock); |
271 | pht_refill_fail(badvaddr, istate); |
259 | pht_refill_fail(badvaddr, istate); |
272 | } |
260 | } |
273 | 261 | ||
274 | 262 | ||
275 | /** Process Instruction/Data Storage Interrupt in Real Mode |
263 | /** Process Instruction/Data Storage Interrupt in Real Mode |
276 | * |
264 | * |
277 | * @param n Interrupt vector number. |
265 | * @param n Interrupt vector number. |
278 | * @param istate Interrupted register context. |
266 | * @param istate Interrupted register context. |
279 | * |
267 | * |
280 | */ |
268 | */ |
281 | bool pht_refill_real(int n, istate_t *istate) |
269 | bool pht_refill_real(int n, istate_t *istate) |
282 | { |
270 | { |
283 | uintptr_t badvaddr; |
271 | uintptr_t badvaddr; |
284 | 272 | ||
285 | if (n == VECTOR_DATA_STORAGE) |
273 | if (n == VECTOR_DATA_STORAGE) |
286 | badvaddr = istate->dar; |
274 | badvaddr = istate->dar; |
287 | else |
275 | else |
288 | badvaddr = istate->pc; |
276 | badvaddr = istate->pc; |
289 | 277 | ||
290 | uint32_t physmem; |
278 | uint32_t physmem; |
291 | asm volatile ( |
279 | asm volatile ( |
292 | "mfsprg3 %0\n" |
280 | "mfsprg3 %0\n" |
293 | : "=r" (physmem) |
281 | : "=r" (physmem) |
294 | ); |
282 | ); |
295 | 283 | ||
296 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
284 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
297 | return false; |
285 | return false; |
298 | 286 | ||
299 | uint32_t page = (badvaddr >> 12) & 0xffff; |
287 | uint32_t page = (badvaddr >> 12) & 0xffff; |
300 | uint32_t api = (badvaddr >> 22) & 0x3f; |
288 | uint32_t api = (badvaddr >> 22) & 0x3f; |
301 | 289 | ||
302 | uint32_t vsid; |
290 | uint32_t vsid; |
303 | asm volatile ( |
291 | asm volatile ( |
304 | "mfsrin %0, %1\n" |
292 | "mfsrin %0, %1\n" |
305 | : "=r" (vsid) |
293 | : "=r" (vsid) |
306 | : "r" (badvaddr) |
294 | : "r" (badvaddr) |
307 | ); |
295 | ); |
308 | 296 | ||
309 | uint32_t sdr1; |
297 | uint32_t sdr1; |
310 | asm volatile ( |
298 | asm volatile ( |
311 | "mfsdr1 %0\n" |
299 | "mfsdr1 %0\n" |
312 | : "=r" (sdr1) |
300 | : "=r" (sdr1) |
313 | ); |
301 | ); |
314 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
302 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
315 | 303 | ||
316 | /* Primary hash (xor) */ |
304 | /* Primary hash (xor) */ |
317 | uint32_t h = 0; |
305 | uint32_t h = 0; |
318 | uint32_t hash = vsid ^ page; |
306 | uint32_t hash = vsid ^ page; |
319 | uint32_t base = (hash & 0x3ff) << 3; |
307 | uint32_t base = (hash & 0x3ff) << 3; |
320 | uint32_t i; |
308 | uint32_t i; |
321 | bool found = false; |
309 | bool found = false; |
322 | 310 | ||
323 | /* Find unused or colliding PTE in PTEG */ |
311 | /* Find unused or colliding PTE in PTEG */ |
324 | for (i = 0; i < 8; i++) { |
312 | for (i = 0; i < 8; i++) { |
325 | if ((!phte_real[base + i].v) || |
313 | if ((!phte_real[base + i].v) || |
326 | ((phte_real[base + i].vsid == vsid) |
314 | ((phte_real[base + i].vsid == vsid) |
327 | && (phte_real[base + i].api == api) |
315 | && (phte_real[base + i].api == api) |
328 | && (phte_real[base + i].h == 0))) { |
316 | && (phte_real[base + i].h == 0))) { |
329 | found = true; |
317 | found = true; |
330 | break; |
318 | break; |
331 | } |
319 | } |
332 | } |
320 | } |
333 | 321 | ||
334 | if (!found) { |
322 | if (!found) { |
335 | /* Secondary hash (not) */ |
323 | /* Secondary hash (not) */ |
336 | uint32_t base2 = (~hash & 0x3ff) << 3; |
324 | uint32_t base2 = (~hash & 0x3ff) << 3; |
337 | 325 | ||
338 | /* Find unused or colliding PTE in PTEG */ |
326 | /* Find unused or colliding PTE in PTEG */ |
339 | for (i = 0; i < 8; i++) { |
327 | for (i = 0; i < 8; i++) { |
340 | if ((!phte_real[base2 + i].v) || |
328 | if ((!phte_real[base2 + i].v) || |
341 | ((phte_real[base2 + i].vsid == vsid) |
329 | ((phte_real[base2 + i].vsid == vsid) |
342 | && (phte_real[base2 + i].api == api) |
330 | && (phte_real[base2 + i].api == api) |
343 | && (phte_real[base2 + i].h == 1))) { |
331 | && (phte_real[base2 + i].h == 1))) { |
344 | found = true; |
332 | found = true; |
345 | base = base2; |
333 | base = base2; |
346 | h = 1; |
334 | h = 1; |
347 | break; |
335 | break; |
348 | } |
336 | } |
349 | } |
337 | } |
350 | 338 | ||
351 | if (!found) { |
339 | if (!found) { |
352 | /* Use secondary hash to avoid collisions |
340 | /* Use secondary hash to avoid collisions |
353 | with usual PHT refill handler. */ |
341 | with usual PHT refill handler. */ |
354 | i = RANDI(seed_real) % 8; |
342 | i = RANDI(seed_real) % 8; |
355 | base = base2; |
343 | base = base2; |
356 | h = 1; |
344 | h = 1; |
357 | } |
345 | } |
358 | } |
346 | } |
359 | 347 | ||
360 | phte_real[base + i].v = 1; |
348 | phte_real[base + i].v = 1; |
361 | phte_real[base + i].vsid = vsid; |
349 | phte_real[base + i].vsid = vsid; |
362 | phte_real[base + i].h = h; |
350 | phte_real[base + i].h = h; |
363 | phte_real[base + i].api = api; |
351 | phte_real[base + i].api = api; |
364 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
352 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
365 | phte_real[base + i].r = 0; |
353 | phte_real[base + i].r = 0; |
366 | phte_real[base + i].c = 0; |
354 | phte_real[base + i].c = 0; |
367 | phte_real[base + i].wimg = 0; |
355 | phte_real[base + i].wimg = 0; |
368 | phte_real[base + i].pp = 2; // FIXME |
356 | phte_real[base + i].pp = 2; // FIXME |
369 | 357 | ||
370 | return true; |
358 | return true; |
371 | } |
359 | } |
372 | 360 | ||
373 | 361 | ||
374 | void tlb_arch_init(void) |
362 | void tlb_arch_init(void) |
375 | { |
363 | { |
376 | tlb_invalidate_all(); |
364 | tlb_invalidate_all(); |
377 | } |
365 | } |
378 | 366 | ||
379 | 367 | ||
380 | void tlb_invalidate_all(void) |
368 | void tlb_invalidate_all(void) |
381 | { |
369 | { |
382 | asm volatile ( |
370 | asm volatile ( |
383 | "tlbsync\n" |
371 | "tlbsync\n" |
384 | ); |
372 | ); |
385 | } |
373 | } |
386 | 374 | ||
387 | 375 | ||
388 | void tlb_invalidate_asid(asid_t asid) |
376 | void tlb_invalidate_asid(asid_t asid) |
389 | { |
377 | { |
390 | uint32_t sdr1; |
378 | uint32_t sdr1; |
391 | asm volatile ( |
379 | asm volatile ( |
392 | "mfsdr1 %0\n" |
380 | "mfsdr1 %0\n" |
393 | : "=r" (sdr1) |
381 | : "=r" (sdr1) |
394 | ); |
382 | ); |
395 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
383 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
396 | 384 | ||
397 | uint32_t i; |
385 | uint32_t i; |
398 | for (i = 0; i < 8192; i++) { |
386 | for (i = 0; i < 8192; i++) { |
399 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
387 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
400 | (phte[i].vsid < ((asid << 4) + 16))) |
388 | (phte[i].vsid < ((asid << 4) + 16))) |
401 | phte[i].v = 0; |
389 | phte[i].v = 0; |
402 | } |
390 | } |
403 | tlb_invalidate_all(); |
391 | tlb_invalidate_all(); |
404 | } |
392 | } |
405 | 393 | ||
406 | 394 | ||
407 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
395 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
408 | { |
396 | { |
409 | // TODO |
397 | // TODO |
410 | tlb_invalidate_all(); |
398 | tlb_invalidate_all(); |
411 | } |
399 | } |
412 | 400 | ||
413 | 401 | ||
414 | #define PRINT_BAT(name, ureg, lreg) \ |
402 | #define PRINT_BAT(name, ureg, lreg) \ |
415 | asm volatile ( \ |
403 | asm volatile ( \ |
416 | "mfspr %0," #ureg "\n" \ |
404 | "mfspr %0," #ureg "\n" \ |
417 | "mfspr %1," #lreg "\n" \ |
405 | "mfspr %1," #lreg "\n" \ |
418 | : "=r" (upper), "=r" (lower) \ |
406 | : "=r" (upper), "=r" (lower) \ |
419 | ); \ |
407 | ); \ |
420 | mask = (upper & 0x1ffc) >> 2; \ |
408 | mask = (upper & 0x1ffc) >> 2; \ |
421 | if (upper & 3) { \ |
409 | if (upper & 3) { \ |
422 | uint32_t tmp = mask; \ |
410 | uint32_t tmp = mask; \ |
423 | length = 128; \ |
411 | length = 128; \ |
424 | while (tmp) { \ |
412 | while (tmp) { \ |
425 | if ((tmp & 1) == 0) { \ |
413 | if ((tmp & 1) == 0) { \ |
426 | printf("ibat[0]: error in mask\n"); \ |
414 | printf("ibat[0]: error in mask\n"); \ |
427 | break; \ |
415 | break; \ |
428 | } \ |
416 | } \ |
429 | length <<= 1; \ |
417 | length <<= 1; \ |
430 | tmp >>= 1; \ |
418 | tmp >>= 1; \ |
431 | } \ |
419 | } \ |
432 | } else \ |
420 | } else \ |
433 | length = 0; \ |
421 | length = 0; \ |
434 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
422 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
435 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
423 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
436 | lower & 0xffff0000, length, mask, \ |
424 | lower & 0xffff0000, length, mask, \ |
437 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
425 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
438 | (upper & 1) ? " user" : ""); |
426 | (upper & 1) ? " user" : ""); |
439 | 427 | ||
440 | 428 | ||
441 | void tlb_print(void) |
429 | void tlb_print(void) |
442 | { |
430 | { |
443 | uint32_t sr; |
431 | uint32_t sr; |
444 | 432 | ||
445 | for (sr = 0; sr < 16; sr++) { |
433 | for (sr = 0; sr < 16; sr++) { |
446 | uint32_t vsid; |
434 | uint32_t vsid; |
447 | asm volatile ( |
435 | asm volatile ( |
448 | "mfsrin %0, %1\n" |
436 | "mfsrin %0, %1\n" |
449 | : "=r" (vsid) |
437 | : "=r" (vsid) |
450 | : "r" (sr << 28) |
438 | : "r" (sr << 28) |
451 | ); |
439 | ); |
452 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
440 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
453 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
441 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
454 | ((vsid >> 30) & 1) ? " supervisor" : "", |
442 | ((vsid >> 30) & 1) ? " supervisor" : "", |
455 | ((vsid >> 29) & 1) ? " user" : ""); |
443 | ((vsid >> 29) & 1) ? " user" : ""); |
456 | } |
444 | } |
457 | 445 | ||
458 | uint32_t upper; |
446 | uint32_t upper; |
459 | uint32_t lower; |
447 | uint32_t lower; |
460 | uint32_t mask; |
448 | uint32_t mask; |
461 | uint32_t length; |
449 | uint32_t length; |
462 | 450 | ||
463 | PRINT_BAT("ibat[0]", 528, 529); |
451 | PRINT_BAT("ibat[0]", 528, 529); |
464 | PRINT_BAT("ibat[1]", 530, 531); |
452 | PRINT_BAT("ibat[1]", 530, 531); |
465 | PRINT_BAT("ibat[2]", 532, 533); |
453 | PRINT_BAT("ibat[2]", 532, 533); |
466 | PRINT_BAT("ibat[3]", 534, 535); |
454 | PRINT_BAT("ibat[3]", 534, 535); |
467 | 455 | ||
468 | PRINT_BAT("dbat[0]", 536, 537); |
456 | PRINT_BAT("dbat[0]", 536, 537); |
469 | PRINT_BAT("dbat[1]", 538, 539); |
457 | PRINT_BAT("dbat[1]", 538, 539); |
470 | PRINT_BAT("dbat[2]", 540, 541); |
458 | PRINT_BAT("dbat[2]", 540, 541); |
471 | PRINT_BAT("dbat[3]", 542, 543); |
459 | PRINT_BAT("dbat[3]", 542, 543); |
472 | } |
460 | } |
473 | 461 | ||
474 | /** @} |
462 | /** @} |
475 | */ |
463 | */ |
476 | 464 |