WebSVN – HelenOS – Diff – /trunk/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->present)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->present));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        default:
            panic("Unexpected rc (%d).", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *str = get_symtab_entry(istate->pc);
    if (str)
        symbol = str;
    str = get_symtab_entry(istate->lr);
    if (str)
        sym2 = str;
 
    fault_if_from_uspace(istate,
        "PHT Refill Exception on %p.", badvaddr);
    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding PTE in PTEG */
 
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) ||
            ((phte[base + i].vsid == vsid)
            && (phte[base + i].api == api)
            && (phte[base + i].h == 0))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding PTE in PTEG */
 
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) ||
                ((phte[base2 + i].vsid == vsid)
                && (phte[base2 + i].api == api)
                && (phte[base2 + i].h == 1))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found)
 
            i = page % 8;
 
    }
   
   
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pte->pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding PTE in PTEG */
 
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) ||
            ((phte_physical[base + i].vsid == vsid)
            && (phte_physical[base + i].api == api)
            && (phte_physical[base + i].h == 0))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding PTE in PTEG */
 
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) ||
                ((phte_physical[base2 + i].vsid == vsid)
                && (phte_physical[base2 + i].api == api)
                && (phte_physical[base2 + i].h == 1))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
 
            i = page % 8;
            base = base2;
            h = 1;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].wimg = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
   
    pte->accessed = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE)
        badvaddr = istate->dar;
    else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 3833	Rev 3836
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <interrupt.h>	38	#include <interrupt.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch.h>	40	#include <arch.h>
41	#include <print.h>	41	#include <print.h>
42	#include <symtab.h>	42	#include <symtab.h>
43		43
44		44
45	/** Try to find PTE for faulting address	45	/** Try to find PTE for faulting address
46	*	46	*
47	* Try to find PTE for faulting address.	47	* Try to find PTE for faulting address.
48	* The as->lock must be held on entry to this function	48	* The as->lock must be held on entry to this function
49	* if lock is true.	49	* if lock is true.
50	*	50	*
51	* @param as Address space.	51	* @param as Address space.
52	* @param lock Lock/unlock the address space.	52	* @param lock Lock/unlock the address space.
53	* @param badvaddr Faulting virtual address.	53	* @param badvaddr Faulting virtual address.
54	* @param access Access mode that caused the fault.	54	* @param access Access mode that caused the fault.
55	* @param istate Pointer to interrupted state.	55	* @param istate Pointer to interrupted state.
56	* @param pfrc Pointer to variable where as_page_fault() return code	56	* @param pfrc Pointer to variable where as_page_fault() return code
57	* will be stored.	57	* will be stored.
58	* @return PTE on success, NULL otherwise.	58	* @return PTE on success, NULL otherwise.
59	*	59	*
60	*/	60	*/
61	static pte_t *	61	static pte_t *
62	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,	62	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
63	istate_t istate, int pfrc)	63	istate_t istate, int pfrc)
64	{	64	{
65	/*	65	/*
66	* Check if the mapping exists in page tables.	66	* Check if the mapping exists in page tables.
67	*/	67	*/
68	pte_t *pte = page_mapping_find(as, badvaddr);	68	pte_t *pte = page_mapping_find(as, badvaddr);
69	if ((pte) && (pte->present)) {	69	if ((pte) && (pte->present)) {
70	/*	70	/*
71	* Mapping found in page tables.	71	* Mapping found in page tables.
72	* Immediately succeed.	72	* Immediately succeed.
73	*/	73	*/
74	return pte;	74	return pte;
75	} else {	75	} else {
76	int rc;	76	int rc;
77		77
78	/*	78	/*
79	* Mapping not found in page tables.	79	* Mapping not found in page tables.
80	* Resort to higher-level page fault handler.	80	* Resort to higher-level page fault handler.
81	*/	81	*/
82	page_table_unlock(as, lock);	82	page_table_unlock(as, lock);
83	switch (rc = as_page_fault(badvaddr, access, istate)) {	83	switch (rc = as_page_fault(badvaddr, access, istate)) {
84	case AS_PF_OK:	84	case AS_PF_OK:
85	/*	85	/*
86	* The higher-level page fault handler succeeded,	86	* The higher-level page fault handler succeeded,
87	* The mapping ought to be in place.	87	* The mapping ought to be in place.
88	*/	88	*/
89	page_table_lock(as, lock);	89	page_table_lock(as, lock);
90	pte = page_mapping_find(as, badvaddr);	90	pte = page_mapping_find(as, badvaddr);
91	ASSERT((pte) && (pte->present));	91	ASSERT((pte) && (pte->present));
92	*pfrc = 0;	92	*pfrc = 0;
93	return pte;	93	return pte;
94	case AS_PF_DEFER:	94	case AS_PF_DEFER:
95	page_table_lock(as, lock);	95	page_table_lock(as, lock);
96	*pfrc = rc;	96	*pfrc = rc;
97	return NULL;	97	return NULL;
98	case AS_PF_FAULT:	98	case AS_PF_FAULT:
99	page_table_lock(as, lock);	99	page_table_lock(as, lock);
100	*pfrc = rc;	100	*pfrc = rc;
101	return NULL;	101	return NULL;
102	default:	102	default:
103	panic("Unexpected rc (%d).", rc);	103	panic("Unexpected rc (%d).", rc);
104	}	104	}
105	}	105	}
106	}	106	}
107		107
108		108
109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
110	{	110	{
111	char *symbol = "";	111	char *symbol = "";
112	char *sym2 = "";	112	char *sym2 = "";
113		113
114	char *str = get_symtab_entry(istate->pc);	114	char *str = get_symtab_entry(istate->pc);
115	if (str)	115	if (str)
116	symbol = str;	116	symbol = str;
117	str = get_symtab_entry(istate->lr);	117	str = get_symtab_entry(istate->lr);
118	if (str)	118	if (str)
119	sym2 = str;	119	sym2 = str;
120		120
121	fault_if_from_uspace(istate,	121	fault_if_from_uspace(istate,
122	"PHT Refill Exception on %p.", badvaddr);	122	"PHT Refill Exception on %p.", badvaddr);
123	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,	123	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
124	istate->pc, symbol, sym2);	124	istate->pc, symbol, sym2);
125	}	125	}
126		126
127		127
128	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)	128	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
129	{	129	{
130	uint32_t page = (vaddr >> 12) & 0xffff;	130	uint32_t page = (vaddr >> 12) & 0xffff;
131	uint32_t api = (vaddr >> 22) & 0x3f;	131	uint32_t api = (vaddr >> 22) & 0x3f;
132		132
133	uint32_t vsid;	133	uint32_t vsid;
134	asm volatile (	134	asm volatile (
135	"mfsrin %0, %1\n"	135	"mfsrin %0, %1\n"
136	: "=r" (vsid)	136	: "=r" (vsid)
137	: "r" (vaddr)	137	: "r" (vaddr)
138	);	138	);
139		139
140	uint32_t sdr1;	140	uint32_t sdr1;
141	asm volatile (	141	asm volatile (
142	"mfsdr1 %0\n"	142	"mfsdr1 %0\n"
143	: "=r" (sdr1)	143	: "=r" (sdr1)
144	);	144	);
145	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	145	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
146		146
147	/* Primary hash (xor) */	147	/* Primary hash (xor) */
148	uint32_t h = 0;	148	uint32_t h = 0;
149	uint32_t hash = vsid ^ page;	149	uint32_t hash = vsid ^ page;
150	uint32_t base = (hash & 0x3ff) << 3;	150	uint32_t base = (hash & 0x3ff) << 3;
151	uint32_t i;	151	uint32_t i;
152	bool found = false;	152	bool found = false;
153		153
154	/* Find unused or colliding	154	/* Find unused or colliding PTE in PTEG */
155	PTE in PTEG */	-
156	for (i = 0; i < 8; i++) {	155	for (i = 0; i < 8; i++) {
-		156	if ((!phte[base + i].v) \|\|
157	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&	157	((phte[base + i].vsid == vsid)
158	(phte[base + i].api == api))) {	158	&& (phte[base + i].api == api)
-		159	&& (phte[base + i].h == 0))) {
159	found = true;	160	found = true;
160	break;	161	break;
161	}	162	}
162	}	163	}
163		164
164	if (!found) {	165	if (!found) {
165	/* Secondary hash (not) */	166	/* Secondary hash (not) */
166	uint32_t base2 = (~hash & 0x3ff) << 3;	167	uint32_t base2 = (~hash & 0x3ff) << 3;
167		168
168	/* Find unused or colliding	169	/* Find unused or colliding PTE in PTEG */
169	PTE in PTEG */	-
170	for (i = 0; i < 8; i++) {	170	for (i = 0; i < 8; i++) {
171	if ((!phte[base2 + i].v) \|\|	171	if ((!phte[base2 + i].v) \|\|
172	((phte[base2 + i].vsid == vsid) &&	172	((phte[base2 + i].vsid == vsid)
173	(phte[base2 + i].api == api))) {	173	&& (phte[base2 + i].api == api)
-		174	&& (phte[base2 + i].h == 1))) {
174	found = true;	175	found = true;
175	base = base2;	176	base = base2;
176	h = 1;	177	h = 1;
177	break;	178	break;
178	}	179	}
179	}	180	}
180		181
181	if (!found) {	182	if (!found)
182	// TODO: A/C precedence groups	-
183	i = page % 8;	183	i = page % 8;
184	}	-
185	}	184	}
186		185
-		186
-		187
187	phte[base + i].v = 1;	188	phte[base + i].v = 1;
188	phte[base + i].vsid = vsid;	189	phte[base + i].vsid = vsid;
189	phte[base + i].h = h;	190	phte[base + i].h = h;
190	phte[base + i].api = api;	191	phte[base + i].api = api;
191	phte[base + i].rpn = pte->pfn;	192	phte[base + i].rpn = pte->pfn;
192	phte[base + i].r = 0;	193	phte[base + i].r = 0;
193	phte[base + i].c = 0;	194	phte[base + i].c = 0;
194	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);	195	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
195	phte[base + i].pp = 2; // FIXME	196	phte[base + i].pp = 2; // FIXME
196	}	197	}
197		198
198		199
199	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)	200	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
200	{	201	{
201	uint32_t page = (vaddr >> 12) & 0xffff;	202	uint32_t page = (vaddr >> 12) & 0xffff;
202	uint32_t api = (vaddr >> 22) & 0x3f;	203	uint32_t api = (vaddr >> 22) & 0x3f;
203		204
204	uint32_t vsid;	205	uint32_t vsid;
205	asm volatile (	206	asm volatile (
206	"mfsrin %0, %1\n"	207	"mfsrin %0, %1\n"
207	: "=r" (vsid)	208	: "=r" (vsid)
208	: "r" (vaddr)	209	: "r" (vaddr)
209	);	210	);
210		211
211	uint32_t sdr1;	212	uint32_t sdr1;
212	asm volatile (	213	asm volatile (
213	"mfsdr1 %0\n"	214	"mfsdr1 %0\n"
214	: "=r" (sdr1)	215	: "=r" (sdr1)
215	);	216	);
216	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	217	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
217		218
218	/* Primary hash (xor) */	219	/* Primary hash (xor) */
219	uint32_t h = 0;	220	uint32_t h = 0;
220	uint32_t hash = vsid ^ page;	221	uint32_t hash = vsid ^ page;
221	uint32_t base = (hash & 0x3ff) << 3;	222	uint32_t base = (hash & 0x3ff) << 3;
222	uint32_t i;	223	uint32_t i;
223	bool found = false;	224	bool found = false;
224		225
225	/* Find unused or colliding	226	/* Find unused or colliding PTE in PTEG */
226	PTE in PTEG */	-
227	for (i = 0; i < 8; i++) {	227	for (i = 0; i < 8; i++) {
228	if ((!phte_physical[base + i].v) \|\|	228	if ((!phte_physical[base + i].v) \|\|
229	((phte_physical[base + i].vsid == vsid) &&	229	((phte_physical[base + i].vsid == vsid)
230	(phte_physical[base + i].api == api))) {	230	&& (phte_physical[base + i].api == api)
-		231	&& (phte_physical[base + i].h == 0))) {
231	found = true;	232	found = true;
232	break;	233	break;
233	}	234	}
234	}	235	}
235		236
236	if (!found) {	237	if (!found) {
237	/* Secondary hash (not) */	238	/* Secondary hash (not) */
238	uint32_t base2 = (~hash & 0x3ff) << 3;	239	uint32_t base2 = (~hash & 0x3ff) << 3;
239		240
240	/* Find unused or colliding	241	/* Find unused or colliding PTE in PTEG */
241	PTE in PTEG */	-
242	for (i = 0; i < 8; i++) {	242	for (i = 0; i < 8; i++) {
243	if ((!phte_physical[base2 + i].v) \|\|	243	if ((!phte_physical[base2 + i].v) \|\|
244	((phte_physical[base2 + i].vsid == vsid) &&	244	((phte_physical[base2 + i].vsid == vsid)
245	(phte_physical[base2 + i].api == api))) {	245	&& (phte_physical[base2 + i].api == api)
-		246	&& (phte_physical[base2 + i].h == 1))) {
246	found = true;	247	found = true;
247	base = base2;	248	base = base2;
248	h = 1;	249	h = 1;
249	break;	250	break;
250	}	251	}
251	}	252	}
252		253
253	if (!found) {	254	if (!found) {
254	// TODO: A/C precedence groups	-
255	i = page % 8;	255	i = page % 8;
-		256	base = base2;
-		257	h = 1;
256	}	258	}
257	}	259	}
258		260
259	phte_physical[base + i].v = 1;	261	phte_physical[base + i].v = 1;
260	phte_physical[base + i].vsid = vsid;	262	phte_physical[base + i].vsid = vsid;
261	phte_physical[base + i].h = h;	263	phte_physical[base + i].h = h;
262	phte_physical[base + i].api = api;	264	phte_physical[base + i].api = api;
263	phte_physical[base + i].rpn = pfn;	265	phte_physical[base + i].rpn = pfn;
264	phte_physical[base + i].r = 0;	266	phte_physical[base + i].r = 0;
265	phte_physical[base + i].c = 0;	267	phte_physical[base + i].c = 0;
266	phte_physical[base + i].wimg = 0;	268	phte_physical[base + i].wimg = 0;
267	phte_physical[base + i].pp = 2; // FIXME	269	phte_physical[base + i].pp = 2; // FIXME
268	}	270	}
269		271
270		272
271	/** Process Instruction/Data Storage Interrupt	273	/** Process Instruction/Data Storage Interrupt
272	*	274	*
273	* @param n Interrupt vector number.	275	* @param n Interrupt vector number.
274	* @param istate Interrupted register context.	276	* @param istate Interrupted register context.
275	*	277	*
276	*/	278	*/
277	void pht_refill(int n, istate_t *istate)	279	void pht_refill(int n, istate_t *istate)
278	{	280	{
279	uintptr_t badvaddr;	281	uintptr_t badvaddr;
280	pte_t *pte;	282	pte_t *pte;
281	int pfrc;	283	int pfrc;
282	as_t *as;	284	as_t *as;
283	bool lock;	285	bool lock;
284		286
285	if (AS == NULL) {	287	if (AS == NULL) {
286	as = AS_KERNEL;	288	as = AS_KERNEL;
287	lock = false;	289	lock = false;
288	} else {	290	} else {
289	as = AS;	291	as = AS;
290	lock = true;	292	lock = true;
291	}	293	}
292		294
293	if (n == VECTOR_DATA_STORAGE)	295	if (n == VECTOR_DATA_STORAGE)
294	badvaddr = istate->dar;	296	badvaddr = istate->dar;
295	else	297	else
296	badvaddr = istate->pc;	298	badvaddr = istate->pc;
297		299
298	page_table_lock(as, lock);	300	page_table_lock(as, lock);
299		301
300	pte = find_mapping_and_check(as, lock, badvaddr,	302	pte = find_mapping_and_check(as, lock, badvaddr,
301	PF_ACCESS_READ /* FIXME */, istate, &pfrc);	303	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
302	if (!pte) {	304	if (!pte) {
303	switch (pfrc) {	305	switch (pfrc) {
304	case AS_PF_FAULT:	306	case AS_PF_FAULT:
305	goto fail;	307	goto fail;
306	break;	308	break;
307	case AS_PF_DEFER:	309	case AS_PF_DEFER:
308	/*	310	/*
309	* The page fault came during copy_from_uspace()	311	* The page fault came during copy_from_uspace()
310	* or copy_to_uspace().	312	* or copy_to_uspace().
311	*/	313	*/
312	page_table_unlock(as, lock);	314	page_table_unlock(as, lock);
313	return;	315	return;
314	default:	316	default:
315	panic("Unexpected pfrc (%d).", pfrc);	317	panic("Unexpected pfrc (%d).", pfrc);
316	}	318	}
317	}	319	}
318		320
319	pte->accessed = 1; /* Record access to PTE */	321	pte->accessed = 1; /* Record access to PTE */
320	pht_insert(badvaddr, pte);	322	pht_insert(badvaddr, pte);
321		323
322	page_table_unlock(as, lock);	324	page_table_unlock(as, lock);
323	return;	325	return;
324		326
325	fail:	327	fail:
326	page_table_unlock(as, lock);	328	page_table_unlock(as, lock);
327	pht_refill_fail(badvaddr, istate);	329	pht_refill_fail(badvaddr, istate);
328	}	330	}
329		331
330		332
331	/** Process Instruction/Data Storage Interrupt in Real Mode	333	/** Process Instruction/Data Storage Interrupt in Real Mode
332	*	334	*
333	* @param n Interrupt vector number.	335	* @param n Interrupt vector number.
334	* @param istate Interrupted register context.	336	* @param istate Interrupted register context.
335	*	337	*
336	*/	338	*/
337	bool pht_real_refill(int n, istate_t *istate)	339	bool pht_real_refill(int n, istate_t *istate)
338	{	340	{
339	uintptr_t badvaddr;	341	uintptr_t badvaddr;
340		342
341	if (n == VECTOR_DATA_STORAGE)	343	if (n == VECTOR_DATA_STORAGE)
342	badvaddr = istate->dar;	344	badvaddr = istate->dar;
343	else	345	else
344	badvaddr = istate->pc;	346	badvaddr = istate->pc;
345		347
346	uint32_t physmem;	348	uint32_t physmem;
347	asm volatile (	349	asm volatile (
348	"mfsprg3 %0\n"	350	"mfsprg3 %0\n"
349	: "=r" (physmem)	351	: "=r" (physmem)
350	);	352	);
351		353
352	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	354	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
353	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	355	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
354	return true;	356	return true;
355	}	357	}
356		358
357	return false;	359	return false;
358	}	360	}
359		361
360		362
361	void tlb_arch_init(void)	363	void tlb_arch_init(void)
362	{	364	{
363	tlb_invalidate_all();	365	tlb_invalidate_all();
364	}	366	}
365		367
366		368
367	void tlb_invalidate_all(void)	369	void tlb_invalidate_all(void)
368	{	370	{
369	asm volatile (	371	asm volatile (
370	"tlbsync\n"	372	"tlbsync\n"
371	);	373	);
372	}	374	}
373		375
374		376
375	void tlb_invalidate_asid(asid_t asid)	377	void tlb_invalidate_asid(asid_t asid)
376	{	378	{
377	uint32_t sdr1;	379	uint32_t sdr1;
378	asm volatile (	380	asm volatile (
379	"mfsdr1 %0\n"	381	"mfsdr1 %0\n"
380	: "=r" (sdr1)	382	: "=r" (sdr1)
381	);	383	);
382	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	384	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
383		385
384	uint32_t i;	386	uint32_t i;
385	for (i = 0; i < 8192; i++) {	387	for (i = 0; i < 8192; i++) {
386	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&	388	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
387	(phte[i].vsid < ((asid << 4) + 16)))	389	(phte[i].vsid < ((asid << 4) + 16)))
388	phte[i].v = 0;	390	phte[i].v = 0;
389	}	391	}
390	tlb_invalidate_all();	392	tlb_invalidate_all();
391	}	393	}
392		394
393		395
394	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	396	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
395	{	397	{
396	// TODO	398	// TODO
397	tlb_invalidate_all();	399	tlb_invalidate_all();
398	}	400	}
399		401
400		402
401	#define PRINT_BAT(name, ureg, lreg) \	403	#define PRINT_BAT(name, ureg, lreg) \
402	asm volatile ( \	404	asm volatile ( \
403	"mfspr %0," #ureg "\n" \	405	"mfspr %0," #ureg "\n" \
404	"mfspr %1," #lreg "\n" \	406	"mfspr %1," #lreg "\n" \
405	: "=r" (upper), "=r" (lower) \	407	: "=r" (upper), "=r" (lower) \
406	); \	408	); \
407	mask = (upper & 0x1ffc) >> 2; \	409	mask = (upper & 0x1ffc) >> 2; \
408	if (upper & 3) { \	410	if (upper & 3) { \
409	uint32_t tmp = mask; \	411	uint32_t tmp = mask; \
410	length = 128; \	412	length = 128; \
411	while (tmp) { \	413	while (tmp) { \
412	if ((tmp & 1) == 0) { \	414	if ((tmp & 1) == 0) { \
413	printf("ibat[0]: error in mask\n"); \	415	printf("ibat[0]: error in mask\n"); \
414	break; \	416	break; \
415	} \	417	} \
416	length <<= 1; \	418	length <<= 1; \
417	tmp >>= 1; \	419	tmp >>= 1; \
418	} \	420	} \
419	} else \	421	} else \
420	length = 0; \	422	length = 0; \
421	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \	423	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \
422	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \	424	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
423	lower & 0xffff0000, length, mask, \	425	lower & 0xffff0000, length, mask, \
424	((upper >> 1) & 1) ? " supervisor" : "", \	426	((upper >> 1) & 1) ? " supervisor" : "", \
425	(upper & 1) ? " user" : "");	427	(upper & 1) ? " user" : "");
426		428
427		429
428	void tlb_print(void)	430	void tlb_print(void)
429	{	431	{
430	uint32_t sr;	432	uint32_t sr;
431		433
432	for (sr = 0; sr < 16; sr++) {	434	for (sr = 0; sr < 16; sr++) {
433	uint32_t vsid;	435	uint32_t vsid;
434	asm volatile (	436	asm volatile (
435	"mfsrin %0, %1\n"	437	"mfsrin %0, %1\n"
436	: "=r" (vsid)	438	: "=r" (vsid)
437	: "r" (sr << 28)	439	: "r" (sr << 28)
438	);	440	);
439	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,	441	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
440	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,	442	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
441	((vsid >> 30) & 1) ? " supervisor" : "",	443	((vsid >> 30) & 1) ? " supervisor" : "",
442	((vsid >> 29) & 1) ? " user" : "");	444	((vsid >> 29) & 1) ? " user" : "");
443	}	445	}
444		446
445	uint32_t upper;	447	uint32_t upper;
446	uint32_t lower;	448	uint32_t lower;
447	uint32_t mask;	449	uint32_t mask;
448	uint32_t length;	450	uint32_t length;
449		451
450	PRINT_BAT("ibat[0]", 528, 529);	452	PRINT_BAT("ibat[0]", 528, 529);
451	PRINT_BAT("ibat[1]", 530, 531);	453	PRINT_BAT("ibat[1]", 530, 531);
452	PRINT_BAT("ibat[2]", 532, 533);	454	PRINT_BAT("ibat[2]", 532, 533);
453	PRINT_BAT("ibat[3]", 534, 535);	455	PRINT_BAT("ibat[3]", 534, 535);
454		456
455	PRINT_BAT("dbat[0]", 536, 537);	457	PRINT_BAT("dbat[0]", 536, 537);
456	PRINT_BAT("dbat[1]", 538, 539);	458	PRINT_BAT("dbat[1]", 538, 539);
457	PRINT_BAT("dbat[2]", 540, 541);	459	PRINT_BAT("dbat[2]", 540, 541);
458	PRINT_BAT("dbat[3]", 542, 543);	460	PRINT_BAT("dbat[3]", 542, 543);
459	}	461	}
460		462
461	/** @}	463	/** @}
462	*/	464	*/
463		465

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(root)/trunk/kernel/arch/ppc32/src/mm/tlb.c – Rev 3833 → 3836