WebSVN – HelenOS – Diff – /trunk/kernel/arch/ppc32/src/mm/tlb.c


/*
 * Copyright (c) 2006 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32mm
 * @{
 */
/** @file
 */
 
#include <mm/tlb.h>
#include <arch/mm/tlb.h>
#include <arch/interrupt.h>
#include <interrupt.h>
#include <mm/as.h>
#include <arch.h>
#include <print.h>
#include <symtab.h>
 
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The as->lock must be held on entry to this function
 * if lock is true.
 *
 * @param as        Address space.
 * @param lock      Lock/unlock the address space.
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 * @return      PTE on success, NULL otherwise.
 *
 */
static pte_t *
find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
    istate_t *istate, int *pfrc)
{
    /*
     * Check if the mapping exists in page tables.
     */
    pte_t *pte = page_mapping_find(as, badvaddr);
    if ((pte) && (pte->present)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
   
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(as, lock);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(as, lock);
            pte = page_mapping_find(as, badvaddr);
            ASSERT((pte) && (pte->present));
            *pfrc = 0;
            return pte;
        case AS_PF_DEFER:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        case AS_PF_FAULT:
            page_table_lock(as, lock);
            *pfrc = rc;
            return NULL;
        default:
            panic("Unexpected rc (%d).", rc);
        }  
    }
}
 
 
static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->pc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->lr);
    if (s)
        sym2 = s;
 
    fault_if_from_uspace(istate,
        "%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
        istate->pc, symbol, sym2);
    panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
        istate->pc, symbol, sym2);
}
 
 
static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) &&
            (phte[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte[base2 + i].v) ||
                ((phte[base2 + i].vsid == vsid) &&
                (phte[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte[base + i].v = 1;
    phte[base + i].vsid = vsid;
    phte[base + i].h = h;
    phte[base + i].api = api;
    phte[base + i].rpn = pte->pfn;
    phte[base + i].r = 0;
    phte[base + i].c = 0;
    phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
    phte[base + i].pp = 2; // FIXME
}
 
 
static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
{
    uint32_t page = (vaddr >> 12) & 0xffff;
    uint32_t api = (vaddr >> 22) & 0x3f;
   
    uint32_t vsid;
    asm volatile (
        "mfsrin %0, %1\n"
        : "=r" (vsid)
        : "r" (vaddr)
    );
   
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000);
   
    /* Primary hash (xor) */
    uint32_t h = 0;
    uint32_t hash = vsid ^ page;
    uint32_t base = (hash & 0x3ff) << 3;
    uint32_t i;
    bool found = false;
   
    /* Find unused or colliding
       PTE in PTEG */
    for (i = 0; i < 8; i++) {
        if ((!phte_physical[base + i].v) ||
            ((phte_physical[base + i].vsid == vsid) &&
            (phte_physical[base + i].api == api))) {
            found = true;
            break;
        }
    }
   
    if (!found) {
        /* Secondary hash (not) */
        uint32_t base2 = (~hash & 0x3ff) << 3;
       
        /* Find unused or colliding
           PTE in PTEG */
        for (i = 0; i < 8; i++) {
            if ((!phte_physical[base2 + i].v) ||
                ((phte_physical[base2 + i].vsid == vsid) &&
                (phte_physical[base2 + i].api == api))) {
                found = true;
                base = base2;
                h = 1;
                break;
            }
        }
       
        if (!found) {
            // TODO: A/C precedence groups
            i = page % 8;
        }
    }
   
    phte_physical[base + i].v = 1;
    phte_physical[base + i].vsid = vsid;
    phte_physical[base + i].h = h;
    phte_physical[base + i].api = api;
    phte_physical[base + i].rpn = pfn;
    phte_physical[base + i].r = 0;
    phte_physical[base + i].c = 0;
    phte_physical[base + i].wimg = 0;
    phte_physical[base + i].pp = 2; // FIXME
}
 
 
/** Process Instruction/Data Storage Interrupt
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
void pht_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
    as_t *as;
    bool lock;
   
    if (AS == NULL) {
        as = AS_KERNEL;
        lock = false;
    } else {
        as = AS;
        lock = true;
    }
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
       
    page_table_lock(as, lock);
   
    pte = find_mapping_and_check(as, lock, badvaddr,
        PF_ACCESS_READ /* FIXME */, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(as, lock);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
   
    pte->accessed = 1; /* Record access to PTE */
    pht_insert(badvaddr, pte);
   
    page_table_unlock(as, lock);
    return;
   
fail:
    page_table_unlock(as, lock);
    pht_refill_fail(badvaddr, istate);
}
 
 
/** Process Instruction/Data Storage Interrupt in Real Mode
 *
 * @param n     Interrupt vector number.
 * @param istate    Interrupted register context.
 *
 */
bool pht_real_refill(int n, istate_t *istate)
{
    uintptr_t badvaddr;
   
    if (n == VECTOR_DATA_STORAGE) {
        asm volatile (
            "mfdar %0\n"
            : "=r" (badvaddr)
        );
    } else
        badvaddr = istate->pc;
   
    uint32_t physmem;
    asm volatile (
        "mfsprg3 %0\n"
        : "=r" (physmem)
    );
   
    if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
        pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
        return true;
    }
   
    return false;
}
 
 
void tlb_arch_init(void)
{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_all(void)
{
    asm volatile (
        "tlbsync\n"
    );
}
 
 
void tlb_invalidate_asid(asid_t asid)
{
    uint32_t sdr1;
    asm volatile (
        "mfsdr1 %0\n"
        : "=r" (sdr1)
    );
    phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000);
   
    uint32_t i;
    for (i = 0; i < 8192; i++) {
        if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
            (phte[i].vsid < ((asid << 4) + 16)))
            phte[i].v = 0;
    }
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    // TODO
    tlb_invalidate_all();
}
 
 
#define PRINT_BAT(name, ureg, lreg) \
    asm volatile ( \
        "mfspr %0," #ureg "\n" \
        "mfspr %1," #lreg "\n" \
        : "=r" (upper), "=r" (lower) \
    ); \
    mask = (upper & 0x1ffc) >> 2; \
    if (upper & 3) { \
        uint32_t tmp = mask; \
        length = 128; \
        while (tmp) { \
            if ((tmp & 1) == 0) { \
                printf("ibat[0]: error in mask\n"); \
                break; \
            } \
            length <<= 1; \
            tmp >>= 1; \
        } \
    } else \
        length = 0; \
    printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \
        sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
        lower & 0xffff0000, length, mask, \
        ((upper >> 1) & 1) ? " supervisor" : "", \
        (upper & 1) ? " user" : "");
 
 
void tlb_print(void)
{
    uint32_t sr;
   
    for (sr = 0; sr < 16; sr++) {
        uint32_t vsid;
        asm volatile (
            "mfsrin %0, %1\n"
            : "=r" (vsid)
            : "r" (sr << 28)
        );
        printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
            sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
            ((vsid >> 30) & 1) ? " supervisor" : "",
            ((vsid >> 29) & 1) ? " user" : "");
    }
   
    uint32_t upper;
    uint32_t lower;
    uint32_t mask;
    uint32_t length;
   
    PRINT_BAT("ibat[0]", 528, 529);
    PRINT_BAT("ibat[1]", 530, 531);
    PRINT_BAT("ibat[2]", 532, 533);
    PRINT_BAT("ibat[3]", 534, 535);
   
    PRINT_BAT("dbat[0]", 536, 537);
    PRINT_BAT("dbat[1]", 538, 539);
    PRINT_BAT("dbat[2]", 540, 541);
    PRINT_BAT("dbat[3]", 542, 543);
}
 
/** @}
 */
 

Rev 3827	Rev 3830
1	/*	1	/*
2	* Copyright (c) 2006 Martin Decky	2	* Copyright (c) 2006 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32mm	29	/** @addtogroup ppc32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <mm/tlb.h>	35	#include <mm/tlb.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <arch/interrupt.h>	37	#include <arch/interrupt.h>
38	#include <interrupt.h>	38	#include <interrupt.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch.h>	40	#include <arch.h>
41	#include <print.h>	41	#include <print.h>
42	#include <symtab.h>	42	#include <symtab.h>
43		43
44		44
45	/** Try to find PTE for faulting address	45	/** Try to find PTE for faulting address
46	*	46	*
47	* Try to find PTE for faulting address.	47	* Try to find PTE for faulting address.
48	* The as->lock must be held on entry to this function	48	* The as->lock must be held on entry to this function
49	* if lock is true.	49	* if lock is true.
50	*	50	*
51	* @param as Address space.	51	* @param as Address space.
52	* @param lock Lock/unlock the address space.	52	* @param lock Lock/unlock the address space.
53	* @param badvaddr Faulting virtual address.	53	* @param badvaddr Faulting virtual address.
54	* @param access Access mode that caused the fault.	54	* @param access Access mode that caused the fault.
55	* @param istate Pointer to interrupted state.	55	* @param istate Pointer to interrupted state.
56	* @param pfrc Pointer to variable where as_page_fault() return code	56	* @param pfrc Pointer to variable where as_page_fault() return code
57	* will be stored.	57	* will be stored.
58	* @return PTE on success, NULL otherwise.	58	* @return PTE on success, NULL otherwise.
59	*	59	*
60	*/	60	*/
61	static pte_t *	61	static pte_t *
62	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,	62	find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,
63	istate_t istate, int pfrc)	63	istate_t istate, int pfrc)
64	{	64	{
65	/*	65	/*
66	* Check if the mapping exists in page tables.	66	* Check if the mapping exists in page tables.
67	*/	67	*/
68	pte_t *pte = page_mapping_find(as, badvaddr);	68	pte_t *pte = page_mapping_find(as, badvaddr);
69	if ((pte) && (pte->p)) {	69	if ((pte) && (pte->present)) {
70	/*	70	/*
71	* Mapping found in page tables.	71	* Mapping found in page tables.
72	* Immediately succeed.	72	* Immediately succeed.
73	*/	73	*/
74	return pte;	74	return pte;
75	} else {	75	} else {
76	int rc;	76	int rc;
77		77
78	/*	78	/*
79	* Mapping not found in page tables.	79	* Mapping not found in page tables.
80	* Resort to higher-level page fault handler.	80	* Resort to higher-level page fault handler.
81	*/	81	*/
82	page_table_unlock(as, lock);	82	page_table_unlock(as, lock);
83	switch (rc = as_page_fault(badvaddr, access, istate)) {	83	switch (rc = as_page_fault(badvaddr, access, istate)) {
84	case AS_PF_OK:	84	case AS_PF_OK:
85	/*	85	/*
86	* The higher-level page fault handler succeeded,	86	* The higher-level page fault handler succeeded,
87	* The mapping ought to be in place.	87	* The mapping ought to be in place.
88	*/	88	*/
89	page_table_lock(as, lock);	89	page_table_lock(as, lock);
90	pte = page_mapping_find(as, badvaddr);	90	pte = page_mapping_find(as, badvaddr);
91	ASSERT((pte) && (pte->p));	91	ASSERT((pte) && (pte->present));
92	*pfrc = 0;	92	*pfrc = 0;
93	return pte;	93	return pte;
94	case AS_PF_DEFER:	94	case AS_PF_DEFER:
95	page_table_lock(as, lock);	95	page_table_lock(as, lock);
96	*pfrc = rc;	96	*pfrc = rc;
97	return NULL;	97	return NULL;
98	case AS_PF_FAULT:	98	case AS_PF_FAULT:
99	page_table_lock(as, lock);	99	page_table_lock(as, lock);
100	*pfrc = rc;	100	*pfrc = rc;
101	return NULL;	101	return NULL;
102	default:	102	default:
103	panic("Unexpected rc (%d).", rc);	103	panic("Unexpected rc (%d).", rc);
104	}	104	}
105	}	105	}
106	}	106	}
107		107
108		108
109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)	109	static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
110	{	110	{
111	char *symbol = "";	111	char *symbol = "";
112	char *sym2 = "";	112	char *sym2 = "";
113		113
114	char *s = get_symtab_entry(istate->pc);	114	char *s = get_symtab_entry(istate->pc);
115	if (s)	115	if (s)
116	symbol = s;	116	symbol = s;
117	s = get_symtab_entry(istate->lr);	117	s = get_symtab_entry(istate->lr);
118	if (s)	118	if (s)
119	sym2 = s;	119	sym2 = s;
120		120
121	fault_if_from_uspace(istate,	121	fault_if_from_uspace(istate,
122	"%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,	122	"%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
123	istate->pc, symbol, sym2);	123	istate->pc, symbol, sym2);
124	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,	124	panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr,
125	istate->pc, symbol, sym2);	125	istate->pc, symbol, sym2);
126	}	126	}
127		127
128		128
129	static void pht_insert(const uintptr_t vaddr, const pfn_t pfn)	129	static void pht_insert(const uintptr_t vaddr, const pte_t *pte)
130	{	130	{
131	uint32_t page = (vaddr >> 12) & 0xffff;	131	uint32_t page = (vaddr >> 12) & 0xffff;
132	uint32_t api = (vaddr >> 22) & 0x3f;	132	uint32_t api = (vaddr >> 22) & 0x3f;
133		133
134	uint32_t vsid;	134	uint32_t vsid;
135	asm volatile (	135	asm volatile (
136	"mfsrin %0, %1\n"	136	"mfsrin %0, %1\n"
137	: "=r" (vsid)	137	: "=r" (vsid)
138	: "r" (vaddr)	138	: "r" (vaddr)
139	);	139	);
140		140
141	uint32_t sdr1;	141	uint32_t sdr1;
142	asm volatile (	142	asm volatile (
143	"mfsdr1 %0\n"	143	"mfsdr1 %0\n"
144	: "=r" (sdr1)	144	: "=r" (sdr1)
145	);	145	);
146	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	146	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
147		147
148	/* Primary hash (xor) */	148	/* Primary hash (xor) */
149	uint32_t h = 0;	149	uint32_t h = 0;
150	uint32_t hash = vsid ^ page;	150	uint32_t hash = vsid ^ page;
151	uint32_t base = (hash & 0x3ff) << 3;	151	uint32_t base = (hash & 0x3ff) << 3;
152	uint32_t i;	152	uint32_t i;
153	bool found = false;	153	bool found = false;
154		154
155	/* Find unused or colliding	155	/* Find unused or colliding
156	PTE in PTEG */	156	PTE in PTEG */
157	for (i = 0; i < 8; i++) {	157	for (i = 0; i < 8; i++) {
158	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&	158	if ((!phte[base + i].v) \|\| ((phte[base + i].vsid == vsid) &&
159	(phte[base + i].api == api))) {	159	(phte[base + i].api == api))) {
160	found = true;	160	found = true;
161	break;	161	break;
162	}	162	}
163	}	163	}
164		164
165	if (!found) {	165	if (!found) {
166	/* Secondary hash (not) */	166	/* Secondary hash (not) */
167	uint32_t base2 = (~hash & 0x3ff) << 3;	167	uint32_t base2 = (~hash & 0x3ff) << 3;
168		168
169	/* Find unused or colliding	169	/* Find unused or colliding
170	PTE in PTEG */	170	PTE in PTEG */
171	for (i = 0; i < 8; i++) {	171	for (i = 0; i < 8; i++) {
172	if ((!phte[base2 + i].v) \|\|	172	if ((!phte[base2 + i].v) \|\|
173	((phte[base2 + i].vsid == vsid) &&	173	((phte[base2 + i].vsid == vsid) &&
174	(phte[base2 + i].api == api))) {	174	(phte[base2 + i].api == api))) {
175	found = true;	175	found = true;
176	base = base2;	176	base = base2;
177	h = 1;	177	h = 1;
178	break;	178	break;
179	}	179	}
180	}	180	}
181		181
182	if (!found) {	182	if (!found) {
183	// TODO: A/C precedence groups	183	// TODO: A/C precedence groups
184	i = page % 8;	184	i = page % 8;
185	}	185	}
186	}	186	}
187		187
188	phte[base + i].v = 1;	188	phte[base + i].v = 1;
189	phte[base + i].vsid = vsid;	189	phte[base + i].vsid = vsid;
190	phte[base + i].h = h;	190	phte[base + i].h = h;
191	phte[base + i].api = api;	191	phte[base + i].api = api;
192	phte[base + i].rpn = pfn;	192	phte[base + i].rpn = pte->pfn;
193	phte[base + i].r = 0;	193	phte[base + i].r = 0;
194	phte[base + i].c = 0;	194	phte[base + i].c = 0;
-		195	phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0);
195	phte[base + i].pp = 2; // FIXME	196	phte[base + i].pp = 2; // FIXME
196	}	197	}
197		198
198		199
199	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)	200	static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn)
200	{	201	{
201	uint32_t page = (vaddr >> 12) & 0xffff;	202	uint32_t page = (vaddr >> 12) & 0xffff;
202	uint32_t api = (vaddr >> 22) & 0x3f;	203	uint32_t api = (vaddr >> 22) & 0x3f;
203		204
204	uint32_t vsid;	205	uint32_t vsid;
205	asm volatile (	206	asm volatile (
206	"mfsrin %0, %1\n"	207	"mfsrin %0, %1\n"
207	: "=r" (vsid)	208	: "=r" (vsid)
208	: "r" (vaddr)	209	: "r" (vaddr)
209	);	210	);
210		211
211	uint32_t sdr1;	212	uint32_t sdr1;
212	asm volatile (	213	asm volatile (
213	"mfsdr1 %0\n"	214	"mfsdr1 %0\n"
214	: "=r" (sdr1)	215	: "=r" (sdr1)
215	);	216	);
216	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);	217	phte_t phte_physical = (phte_t ) (sdr1 & 0xffff0000);
217		218
218	/* Primary hash (xor) */	219	/* Primary hash (xor) */
219	uint32_t h = 0;	220	uint32_t h = 0;
220	uint32_t hash = vsid ^ page;	221	uint32_t hash = vsid ^ page;
221	uint32_t base = (hash & 0x3ff) << 3;	222	uint32_t base = (hash & 0x3ff) << 3;
222	uint32_t i;	223	uint32_t i;
223	bool found = false;	224	bool found = false;
224		225
225	/* Find unused or colliding	226	/* Find unused or colliding
226	PTE in PTEG */	227	PTE in PTEG */
227	for (i = 0; i < 8; i++) {	228	for (i = 0; i < 8; i++) {
228	if ((!phte_physical[base + i].v) \|\|	229	if ((!phte_physical[base + i].v) \|\|
229	((phte_physical[base + i].vsid == vsid) &&	230	((phte_physical[base + i].vsid == vsid) &&
230	(phte_physical[base + i].api == api))) {	231	(phte_physical[base + i].api == api))) {
231	found = true;	232	found = true;
232	break;	233	break;
233	}	234	}
234	}	235	}
235		236
236	if (!found) {	237	if (!found) {
237	/* Secondary hash (not) */	238	/* Secondary hash (not) */
238	uint32_t base2 = (~hash & 0x3ff) << 3;	239	uint32_t base2 = (~hash & 0x3ff) << 3;
239		240
240	/* Find unused or colliding	241	/* Find unused or colliding
241	PTE in PTEG */	242	PTE in PTEG */
242	for (i = 0; i < 8; i++) {	243	for (i = 0; i < 8; i++) {
243	if ((!phte_physical[base2 + i].v) \|\|	244	if ((!phte_physical[base2 + i].v) \|\|
244	((phte_physical[base2 + i].vsid == vsid) &&	245	((phte_physical[base2 + i].vsid == vsid) &&
245	(phte_physical[base2 + i].api == api))) {	246	(phte_physical[base2 + i].api == api))) {
246	found = true;	247	found = true;
247	base = base2;	248	base = base2;
248	h = 1;	249	h = 1;
249	break;	250	break;
250	}	251	}
251	}	252	}
252		253
253	if (!found) {	254	if (!found) {
254	// TODO: A/C precedence groups	255	// TODO: A/C precedence groups
255	i = page % 8;	256	i = page % 8;
256	}	257	}
257	}	258	}
258		259
259	phte_physical[base + i].v = 1;	260	phte_physical[base + i].v = 1;
260	phte_physical[base + i].vsid = vsid;	261	phte_physical[base + i].vsid = vsid;
261	phte_physical[base + i].h = h;	262	phte_physical[base + i].h = h;
262	phte_physical[base + i].api = api;	263	phte_physical[base + i].api = api;
263	phte_physical[base + i].rpn = pfn;	264	phte_physical[base + i].rpn = pfn;
264	phte_physical[base + i].r = 0;	265	phte_physical[base + i].r = 0;
265	phte_physical[base + i].c = 0;	266	phte_physical[base + i].c = 0;
-		267	phte_physical[base + i].wimg = 0;
266	phte_physical[base + i].pp = 2; // FIXME	268	phte_physical[base + i].pp = 2; // FIXME
267	}	269	}
268		270
269		271
270	/** Process Instruction/Data Storage Interrupt	272	/** Process Instruction/Data Storage Interrupt
271	*	273	*
272	* @param n Interrupt vector number.	274	* @param n Interrupt vector number.
273	* @param istate Interrupted register context.	275	* @param istate Interrupted register context.
274	*	276	*
275	*/	277	*/
276	void pht_refill(int n, istate_t *istate)	278	void pht_refill(int n, istate_t *istate)
277	{	279	{
278	uintptr_t badvaddr;	280	uintptr_t badvaddr;
279	pte_t *pte;	281	pte_t *pte;
280	int pfrc;	282	int pfrc;
281	as_t *as;	283	as_t *as;
282	bool lock;	284	bool lock;
283		285
284	if (AS == NULL) {	286	if (AS == NULL) {
285	as = AS_KERNEL;	287	as = AS_KERNEL;
286	lock = false;	288	lock = false;
287	} else {	289	} else {
288	as = AS;	290	as = AS;
289	lock = true;	291	lock = true;
290	}	292	}
291		293
292	if (n == VECTOR_DATA_STORAGE) {	294	if (n == VECTOR_DATA_STORAGE) {
293	asm volatile (	295	asm volatile (
294	"mfdar %0\n"	296	"mfdar %0\n"
295	: "=r" (badvaddr)	297	: "=r" (badvaddr)
296	);	298	);
297	} else	299	} else
298	badvaddr = istate->pc;	300	badvaddr = istate->pc;
299		301
300	page_table_lock(as, lock);	302	page_table_lock(as, lock);
301		303
302	pte = find_mapping_and_check(as, lock, badvaddr,	304	pte = find_mapping_and_check(as, lock, badvaddr,
303	PF_ACCESS_READ /* FIXME */, istate, &pfrc);	305	PF_ACCESS_READ /* FIXME */, istate, &pfrc);
304	if (!pte) {	306	if (!pte) {
305	switch (pfrc) {	307	switch (pfrc) {
306	case AS_PF_FAULT:	308	case AS_PF_FAULT:
307	goto fail;	309	goto fail;
308	break;	310	break;
309	case AS_PF_DEFER:	311	case AS_PF_DEFER:
310	/*	312	/*
311	* The page fault came during copy_from_uspace()	313	* The page fault came during copy_from_uspace()
312	* or copy_to_uspace().	314	* or copy_to_uspace().
313	*/	315	*/
314	page_table_unlock(as, lock);	316	page_table_unlock(as, lock);
315	return;	317	return;
316	default:	318	default:
317	panic("Unexpected pfrc (%d).", pfrc);	319	panic("Unexpected pfrc (%d).", pfrc);
318	}	320	}
319	}	321	}
320		322
321	pte->a = 1; /* Record access to PTE */	323	pte->accessed = 1; /* Record access to PTE */
322	pht_insert(badvaddr, pte->pfn);	324	pht_insert(badvaddr, pte);
323		325
324	page_table_unlock(as, lock);	326	page_table_unlock(as, lock);
325	return;	327	return;
326		328
327	fail:	329	fail:
328	page_table_unlock(as, lock);	330	page_table_unlock(as, lock);
329	pht_refill_fail(badvaddr, istate);	331	pht_refill_fail(badvaddr, istate);
330	}	332	}
331		333
332		334
333	/** Process Instruction/Data Storage Interrupt in Real Mode	335	/** Process Instruction/Data Storage Interrupt in Real Mode
334	*	336	*
335	* @param n Interrupt vector number.	337	* @param n Interrupt vector number.
336	* @param istate Interrupted register context.	338	* @param istate Interrupted register context.
337	*	339	*
338	*/	340	*/
339	bool pht_real_refill(int n, istate_t *istate)	341	bool pht_real_refill(int n, istate_t *istate)
340	{	342	{
341	uintptr_t badvaddr;	343	uintptr_t badvaddr;
342		344
343	if (n == VECTOR_DATA_STORAGE) {	345	if (n == VECTOR_DATA_STORAGE) {
344	asm volatile (	346	asm volatile (
345	"mfdar %0\n"	347	"mfdar %0\n"
346	: "=r" (badvaddr)	348	: "=r" (badvaddr)
347	);	349	);
348	} else	350	} else
349	badvaddr = istate->pc;	351	badvaddr = istate->pc;
350		352
351	uint32_t physmem;	353	uint32_t physmem;
352	asm volatile (	354	asm volatile (
353	"mfsprg3 %0\n"	355	"mfsprg3 %0\n"
354	: "=r" (physmem)	356	: "=r" (physmem)
355	);	357	);
356		358
357	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {	359	if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) {
358	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);	360	pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12);
359	return true;	361	return true;
360	}	362	}
361		363
362	return false;	364	return false;
363	}	365	}
364		366
365		367
366	void tlb_arch_init(void)	368	void tlb_arch_init(void)
367	{	369	{
368	tlb_invalidate_all();	370	tlb_invalidate_all();
369	}	371	}
370		372
371		373
372	void tlb_invalidate_all(void)	374	void tlb_invalidate_all(void)
373	{	375	{
374	asm volatile (	376	asm volatile (
375	"tlbsync\n"	377	"tlbsync\n"
376	);	378	);
377	}	379	}
378		380
379		381
380	void tlb_invalidate_asid(asid_t asid)	382	void tlb_invalidate_asid(asid_t asid)
381	{	383	{
382	uint32_t sdr1;	384	uint32_t sdr1;
383	asm volatile (	385	asm volatile (
384	"mfsdr1 %0\n"	386	"mfsdr1 %0\n"
385	: "=r" (sdr1)	387	: "=r" (sdr1)
386	);	388	);
387	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);	389	phte_t phte = (phte_t ) PA2KA(sdr1 & 0xffff0000);
388		390
389	uint32_t i;	391	uint32_t i;
390	for (i = 0; i < 8192; i++) {	392	for (i = 0; i < 8192; i++) {
391	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&	393	if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) &&
392	(phte[i].vsid < ((asid << 4) + 16)))	394	(phte[i].vsid < ((asid << 4) + 16)))
393	phte[i].v = 0;	395	phte[i].v = 0;
394	}	396	}
395	tlb_invalidate_all();	397	tlb_invalidate_all();
396	}	398	}
397		399
398		400
399	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	401	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
400	{	402	{
401	// TODO	403	// TODO
402	tlb_invalidate_all();	404	tlb_invalidate_all();
403	}	405	}
404		406
405		407
406	#define PRINT_BAT(name, ureg, lreg) \	408	#define PRINT_BAT(name, ureg, lreg) \
407	asm volatile ( \	409	asm volatile ( \
408	"mfspr %0," #ureg "\n" \	410	"mfspr %0," #ureg "\n" \
409	"mfspr %1," #lreg "\n" \	411	"mfspr %1," #lreg "\n" \
410	: "=r" (upper), "=r" (lower) \	412	: "=r" (upper), "=r" (lower) \
411	); \	413	); \
412	mask = (upper & 0x1ffc) >> 2; \	414	mask = (upper & 0x1ffc) >> 2; \
413	if (upper & 3) { \	415	if (upper & 3) { \
414	uint32_t tmp = mask; \	416	uint32_t tmp = mask; \
415	length = 128; \	417	length = 128; \
416	while (tmp) { \	418	while (tmp) { \
417	if ((tmp & 1) == 0) { \	419	if ((tmp & 1) == 0) { \
418	printf("ibat[0]: error in mask\n"); \	420	printf("ibat[0]: error in mask\n"); \
419	break; \	421	break; \
420	} \	422	} \
421	length <<= 1; \	423	length <<= 1; \
422	tmp >>= 1; \	424	tmp >>= 1; \
423	} \	425	} \
424	} else \	426	} else \
425	length = 0; \	427	length = 0; \
426	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \	428	printf(name ": page=%.p frame=%.p length=%d KB (mask=%#x)%s%s\n", \
427	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \	429	sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \
428	lower & 0xffff0000, length, mask, \	430	lower & 0xffff0000, length, mask, \
429	((upper >> 1) & 1) ? " supervisor" : "", \	431	((upper >> 1) & 1) ? " supervisor" : "", \
430	(upper & 1) ? " user" : "");	432	(upper & 1) ? " user" : "");
431		433
432		434
433	void tlb_print(void)	435	void tlb_print(void)
434	{	436	{
435	uint32_t sr;	437	uint32_t sr;
436		438
437	for (sr = 0; sr < 16; sr++) {	439	for (sr = 0; sr < 16; sr++) {
438	uint32_t vsid;	440	uint32_t vsid;
439	asm volatile (	441	asm volatile (
440	"mfsrin %0, %1\n"	442	"mfsrin %0, %1\n"
441	: "=r" (vsid)	443	: "=r" (vsid)
442	: "r" (sr << 28)	444	: "r" (sr << 28)
443	);	445	);
444	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,	446	printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr,
445	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,	447	sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
446	((vsid >> 30) & 1) ? " supervisor" : "",	448	((vsid >> 30) & 1) ? " supervisor" : "",
447	((vsid >> 29) & 1) ? " user" : "");	449	((vsid >> 29) & 1) ? " user" : "");
448	}	450	}
449		451
450	uint32_t upper;	452	uint32_t upper;
451	uint32_t lower;	453	uint32_t lower;
452	uint32_t mask;	454	uint32_t mask;
453	uint32_t length;	455	uint32_t length;
454		456
455	PRINT_BAT("ibat[0]", 528, 529);	457	PRINT_BAT("ibat[0]", 528, 529);
456	PRINT_BAT("ibat[1]", 530, 531);	458	PRINT_BAT("ibat[1]", 530, 531);
457	PRINT_BAT("ibat[2]", 532, 533);	459	PRINT_BAT("ibat[2]", 532, 533);
458	PRINT_BAT("ibat[3]", 534, 535);	460	PRINT_BAT("ibat[3]", 534, 535);
459		461
460	PRINT_BAT("dbat[0]", 536, 537);	462	PRINT_BAT("dbat[0]", 536, 537);
461	PRINT_BAT("dbat[1]", 538, 539);	463	PRINT_BAT("dbat[1]", 538, 539);
462	PRINT_BAT("dbat[2]", 540, 541);	464	PRINT_BAT("dbat[2]", 540, 541);
463	PRINT_BAT("dbat[3]", 542, 543);	465	PRINT_BAT("dbat[3]", 542, 543);
464	}	466	}
465		467
466	/** @}	468	/** @}
467	*/	469	*/
468		470

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(root)/trunk/kernel/arch/ppc32/src/mm/tlb.c – Rev 3827 → 3830