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1 | /* |
1 | /* |
2 | * Copyright (c) 2006 Martin Decky |
2 | * Copyright (c) 2006 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup ppc32mm |
29 | /** @addtogroup ppc32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
38 | #include <interrupt.h> |
38 | #include <interrupt.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <symtab.h> |
- | |
43 | #include <macros.h> |
42 | #include <macros.h> |
44 | 43 | ||
- | 44 | #ifdef CONFIG_SYMTAB |
|
- | 45 | #include <symtab.h> |
|
- | 46 | #endif |
|
45 | 47 | ||
46 | static unsigned int seed = 10; |
48 | static unsigned int seed = 10; |
47 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
49 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
48 | 50 | ||
49 | 51 | ||
50 | #define TLB_FLUSH \ |
52 | #define TLB_FLUSH \ |
51 | "tlbie %0\n" \ |
53 | "tlbie %0\n" \ |
52 | "addi %0, %0, 0x1000\n" |
54 | "addi %0, %0, 0x1000\n" |
53 | 55 | ||
54 | 56 | ||
55 | /** Try to find PTE for faulting address |
57 | /** Try to find PTE for faulting address |
56 | * |
58 | * |
57 | * Try to find PTE for faulting address. |
59 | * Try to find PTE for faulting address. |
58 | * The as->lock must be held on entry to this function |
60 | * The as->lock must be held on entry to this function |
59 | * if lock is true. |
61 | * if lock is true. |
60 | * |
62 | * |
61 | * @param as Address space. |
63 | * @param as Address space. |
62 | * @param lock Lock/unlock the address space. |
64 | * @param lock Lock/unlock the address space. |
63 | * @param badvaddr Faulting virtual address. |
65 | * @param badvaddr Faulting virtual address. |
64 | * @param access Access mode that caused the fault. |
66 | * @param access Access mode that caused the fault. |
65 | * @param istate Pointer to interrupted state. |
67 | * @param istate Pointer to interrupted state. |
66 | * @param pfrc Pointer to variable where as_page_fault() return code |
68 | * @param pfrc Pointer to variable where as_page_fault() return code |
67 | * will be stored. |
69 | * will be stored. |
68 | * @return PTE on success, NULL otherwise. |
70 | * @return PTE on success, NULL otherwise. |
69 | * |
71 | * |
70 | */ |
72 | */ |
71 | static pte_t * |
73 | static pte_t * |
72 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
74 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
73 | istate_t *istate, int *pfrc) |
75 | istate_t *istate, int *pfrc) |
74 | { |
76 | { |
75 | /* |
77 | /* |
76 | * Check if the mapping exists in page tables. |
78 | * Check if the mapping exists in page tables. |
77 | */ |
79 | */ |
78 | pte_t *pte = page_mapping_find(as, badvaddr); |
80 | pte_t *pte = page_mapping_find(as, badvaddr); |
79 | if ((pte) && (pte->present)) { |
81 | if ((pte) && (pte->present)) { |
80 | /* |
82 | /* |
81 | * Mapping found in page tables. |
83 | * Mapping found in page tables. |
82 | * Immediately succeed. |
84 | * Immediately succeed. |
83 | */ |
85 | */ |
84 | return pte; |
86 | return pte; |
85 | } else { |
87 | } else { |
86 | int rc; |
88 | int rc; |
87 | 89 | ||
88 | /* |
90 | /* |
89 | * Mapping not found in page tables. |
91 | * Mapping not found in page tables. |
90 | * Resort to higher-level page fault handler. |
92 | * Resort to higher-level page fault handler. |
91 | */ |
93 | */ |
92 | page_table_unlock(as, lock); |
94 | page_table_unlock(as, lock); |
93 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
95 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
94 | case AS_PF_OK: |
96 | case AS_PF_OK: |
95 | /* |
97 | /* |
96 | * The higher-level page fault handler succeeded, |
98 | * The higher-level page fault handler succeeded, |
97 | * The mapping ought to be in place. |
99 | * The mapping ought to be in place. |
98 | */ |
100 | */ |
99 | page_table_lock(as, lock); |
101 | page_table_lock(as, lock); |
100 | pte = page_mapping_find(as, badvaddr); |
102 | pte = page_mapping_find(as, badvaddr); |
101 | ASSERT((pte) && (pte->present)); |
103 | ASSERT((pte) && (pte->present)); |
102 | *pfrc = 0; |
104 | *pfrc = 0; |
103 | return pte; |
105 | return pte; |
104 | case AS_PF_DEFER: |
106 | case AS_PF_DEFER: |
105 | page_table_lock(as, lock); |
107 | page_table_lock(as, lock); |
106 | *pfrc = rc; |
108 | *pfrc = rc; |
107 | return NULL; |
109 | return NULL; |
108 | case AS_PF_FAULT: |
110 | case AS_PF_FAULT: |
109 | page_table_lock(as, lock); |
111 | page_table_lock(as, lock); |
110 | *pfrc = rc; |
112 | *pfrc = rc; |
111 | return NULL; |
113 | return NULL; |
112 | default: |
114 | default: |
113 | panic("Unexpected rc (%d).", rc); |
115 | panic("Unexpected rc (%d).", rc); |
114 | } |
116 | } |
115 | } |
117 | } |
116 | } |
118 | } |
117 | 119 | ||
118 | 120 | ||
119 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
121 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
120 | { |
122 | { |
121 | char *symbol = ""; |
123 | char *symbol = ""; |
122 | char *sym2 = ""; |
124 | char *sym2 = ""; |
123 | 125 | ||
- | 126 | #ifdef CONFIG_SYMTAB |
|
124 | char *str = get_symtab_entry(istate->pc); |
127 | char *str = get_symtab_entry(istate->pc); |
125 | if (str) |
128 | if (str) |
126 | symbol = str; |
129 | symbol = str; |
127 | str = get_symtab_entry(istate->lr); |
130 | str = get_symtab_entry(istate->lr); |
128 | if (str) |
131 | if (str) |
129 | sym2 = str; |
132 | sym2 = str; |
- | 133 | #endif |
|
130 | 134 | ||
131 | fault_if_from_uspace(istate, |
135 | fault_if_from_uspace(istate, |
132 | "PHT Refill Exception on %p.", badvaddr); |
136 | "PHT Refill Exception on %p.", badvaddr); |
133 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
137 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
134 | istate->pc, symbol, sym2); |
138 | istate->pc, symbol, sym2); |
135 | } |
139 | } |
136 | 140 | ||
137 | 141 | ||
138 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
142 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
139 | { |
143 | { |
140 | uint32_t page = (vaddr >> 12) & 0xffff; |
144 | uint32_t page = (vaddr >> 12) & 0xffff; |
141 | uint32_t api = (vaddr >> 22) & 0x3f; |
145 | uint32_t api = (vaddr >> 22) & 0x3f; |
142 | 146 | ||
143 | uint32_t vsid; |
147 | uint32_t vsid; |
144 | asm volatile ( |
148 | asm volatile ( |
145 | "mfsrin %0, %1\n" |
149 | "mfsrin %0, %1\n" |
146 | : "=r" (vsid) |
150 | : "=r" (vsid) |
147 | : "r" (vaddr) |
151 | : "r" (vaddr) |
148 | ); |
152 | ); |
149 | 153 | ||
150 | uint32_t sdr1; |
154 | uint32_t sdr1; |
151 | asm volatile ( |
155 | asm volatile ( |
152 | "mfsdr1 %0\n" |
156 | "mfsdr1 %0\n" |
153 | : "=r" (sdr1) |
157 | : "=r" (sdr1) |
154 | ); |
158 | ); |
155 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
159 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
156 | 160 | ||
157 | /* Primary hash (xor) */ |
161 | /* Primary hash (xor) */ |
158 | uint32_t h = 0; |
162 | uint32_t h = 0; |
159 | uint32_t hash = vsid ^ page; |
163 | uint32_t hash = vsid ^ page; |
160 | uint32_t base = (hash & 0x3ff) << 3; |
164 | uint32_t base = (hash & 0x3ff) << 3; |
161 | uint32_t i; |
165 | uint32_t i; |
162 | bool found = false; |
166 | bool found = false; |
163 | 167 | ||
164 | /* Find colliding PTE in PTEG */ |
168 | /* Find colliding PTE in PTEG */ |
165 | for (i = 0; i < 8; i++) { |
169 | for (i = 0; i < 8; i++) { |
166 | if ((phte[base + i].v) |
170 | if ((phte[base + i].v) |
167 | && (phte[base + i].vsid == vsid) |
171 | && (phte[base + i].vsid == vsid) |
168 | && (phte[base + i].api == api) |
172 | && (phte[base + i].api == api) |
169 | && (phte[base + i].h == 0)) { |
173 | && (phte[base + i].h == 0)) { |
170 | found = true; |
174 | found = true; |
171 | break; |
175 | break; |
172 | } |
176 | } |
173 | } |
177 | } |
174 | 178 | ||
175 | if (!found) { |
179 | if (!found) { |
176 | /* Find unused PTE in PTEG */ |
180 | /* Find unused PTE in PTEG */ |
177 | for (i = 0; i < 8; i++) { |
181 | for (i = 0; i < 8; i++) { |
178 | if (!phte[base + i].v) { |
182 | if (!phte[base + i].v) { |
179 | found = true; |
183 | found = true; |
180 | break; |
184 | break; |
181 | } |
185 | } |
182 | } |
186 | } |
183 | } |
187 | } |
184 | 188 | ||
185 | if (!found) { |
189 | if (!found) { |
186 | /* Secondary hash (not) */ |
190 | /* Secondary hash (not) */ |
187 | uint32_t base2 = (~hash & 0x3ff) << 3; |
191 | uint32_t base2 = (~hash & 0x3ff) << 3; |
188 | 192 | ||
189 | /* Find colliding PTE in PTEG */ |
193 | /* Find colliding PTE in PTEG */ |
190 | for (i = 0; i < 8; i++) { |
194 | for (i = 0; i < 8; i++) { |
191 | if ((phte[base2 + i].v) |
195 | if ((phte[base2 + i].v) |
192 | && (phte[base2 + i].vsid == vsid) |
196 | && (phte[base2 + i].vsid == vsid) |
193 | && (phte[base2 + i].api == api) |
197 | && (phte[base2 + i].api == api) |
194 | && (phte[base2 + i].h == 1)) { |
198 | && (phte[base2 + i].h == 1)) { |
195 | found = true; |
199 | found = true; |
196 | base = base2; |
200 | base = base2; |
197 | h = 1; |
201 | h = 1; |
198 | break; |
202 | break; |
199 | } |
203 | } |
200 | } |
204 | } |
201 | 205 | ||
202 | if (!found) { |
206 | if (!found) { |
203 | /* Find unused PTE in PTEG */ |
207 | /* Find unused PTE in PTEG */ |
204 | for (i = 0; i < 8; i++) { |
208 | for (i = 0; i < 8; i++) { |
205 | if (!phte[base2 + i].v) { |
209 | if (!phte[base2 + i].v) { |
206 | found = true; |
210 | found = true; |
207 | base = base2; |
211 | base = base2; |
208 | h = 1; |
212 | h = 1; |
209 | break; |
213 | break; |
210 | } |
214 | } |
211 | } |
215 | } |
212 | } |
216 | } |
213 | 217 | ||
214 | if (!found) |
218 | if (!found) |
215 | i = RANDI(seed) % 8; |
219 | i = RANDI(seed) % 8; |
216 | } |
220 | } |
217 | 221 | ||
218 | phte[base + i].v = 1; |
222 | phte[base + i].v = 1; |
219 | phte[base + i].vsid = vsid; |
223 | phte[base + i].vsid = vsid; |
220 | phte[base + i].h = h; |
224 | phte[base + i].h = h; |
221 | phte[base + i].api = api; |
225 | phte[base + i].api = api; |
222 | phte[base + i].rpn = pte->pfn; |
226 | phte[base + i].rpn = pte->pfn; |
223 | phte[base + i].r = 0; |
227 | phte[base + i].r = 0; |
224 | phte[base + i].c = 0; |
228 | phte[base + i].c = 0; |
225 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
229 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
226 | phte[base + i].pp = 2; // FIXME |
230 | phte[base + i].pp = 2; // FIXME |
227 | } |
231 | } |
228 | 232 | ||
229 | 233 | ||
230 | /** Process Instruction/Data Storage Exception |
234 | /** Process Instruction/Data Storage Exception |
231 | * |
235 | * |
232 | * @param n Exception vector number. |
236 | * @param n Exception vector number. |
233 | * @param istate Interrupted register context. |
237 | * @param istate Interrupted register context. |
234 | * |
238 | * |
235 | */ |
239 | */ |
236 | void pht_refill(int n, istate_t *istate) |
240 | void pht_refill(int n, istate_t *istate) |
237 | { |
241 | { |
238 | uintptr_t badvaddr; |
242 | uintptr_t badvaddr; |
239 | pte_t *pte; |
243 | pte_t *pte; |
240 | int pfrc; |
244 | int pfrc; |
241 | as_t *as; |
245 | as_t *as; |
242 | bool lock; |
246 | bool lock; |
243 | 247 | ||
244 | if (AS == NULL) { |
248 | if (AS == NULL) { |
245 | as = AS_KERNEL; |
249 | as = AS_KERNEL; |
246 | lock = false; |
250 | lock = false; |
247 | } else { |
251 | } else { |
248 | as = AS; |
252 | as = AS; |
249 | lock = true; |
253 | lock = true; |
250 | } |
254 | } |
251 | 255 | ||
252 | if (n == VECTOR_DATA_STORAGE) |
256 | if (n == VECTOR_DATA_STORAGE) |
253 | badvaddr = istate->dar; |
257 | badvaddr = istate->dar; |
254 | else |
258 | else |
255 | badvaddr = istate->pc; |
259 | badvaddr = istate->pc; |
256 | 260 | ||
257 | page_table_lock(as, lock); |
261 | page_table_lock(as, lock); |
258 | 262 | ||
259 | pte = find_mapping_and_check(as, lock, badvaddr, |
263 | pte = find_mapping_and_check(as, lock, badvaddr, |
260 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
264 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
261 | if (!pte) { |
265 | if (!pte) { |
262 | switch (pfrc) { |
266 | switch (pfrc) { |
263 | case AS_PF_FAULT: |
267 | case AS_PF_FAULT: |
264 | goto fail; |
268 | goto fail; |
265 | break; |
269 | break; |
266 | case AS_PF_DEFER: |
270 | case AS_PF_DEFER: |
267 | /* |
271 | /* |
268 | * The page fault came during copy_from_uspace() |
272 | * The page fault came during copy_from_uspace() |
269 | * or copy_to_uspace(). |
273 | * or copy_to_uspace(). |
270 | */ |
274 | */ |
271 | page_table_unlock(as, lock); |
275 | page_table_unlock(as, lock); |
272 | return; |
276 | return; |
273 | default: |
277 | default: |
274 | panic("Unexpected pfrc (%d).", pfrc); |
278 | panic("Unexpected pfrc (%d).", pfrc); |
275 | } |
279 | } |
276 | } |
280 | } |
277 | 281 | ||
278 | pte->accessed = 1; /* Record access to PTE */ |
282 | pte->accessed = 1; /* Record access to PTE */ |
279 | pht_insert(badvaddr, pte); |
283 | pht_insert(badvaddr, pte); |
280 | 284 | ||
281 | page_table_unlock(as, lock); |
285 | page_table_unlock(as, lock); |
282 | return; |
286 | return; |
283 | 287 | ||
284 | fail: |
288 | fail: |
285 | page_table_unlock(as, lock); |
289 | page_table_unlock(as, lock); |
286 | pht_refill_fail(badvaddr, istate); |
290 | pht_refill_fail(badvaddr, istate); |
287 | } |
291 | } |
288 | 292 | ||
289 | 293 | ||
290 | /** Process Instruction/Data Storage Exception in Real Mode |
294 | /** Process Instruction/Data Storage Exception in Real Mode |
291 | * |
295 | * |
292 | * @param n Exception vector number. |
296 | * @param n Exception vector number. |
293 | * @param istate Interrupted register context. |
297 | * @param istate Interrupted register context. |
294 | * |
298 | * |
295 | */ |
299 | */ |
296 | bool pht_refill_real(int n, istate_t *istate) |
300 | bool pht_refill_real(int n, istate_t *istate) |
297 | { |
301 | { |
298 | uintptr_t badvaddr; |
302 | uintptr_t badvaddr; |
299 | 303 | ||
300 | if (n == VECTOR_DATA_STORAGE) |
304 | if (n == VECTOR_DATA_STORAGE) |
301 | badvaddr = istate->dar; |
305 | badvaddr = istate->dar; |
302 | else |
306 | else |
303 | badvaddr = istate->pc; |
307 | badvaddr = istate->pc; |
304 | 308 | ||
305 | uint32_t physmem; |
309 | uint32_t physmem; |
306 | asm volatile ( |
310 | asm volatile ( |
307 | "mfsprg3 %0\n" |
311 | "mfsprg3 %0\n" |
308 | : "=r" (physmem) |
312 | : "=r" (physmem) |
309 | ); |
313 | ); |
310 | 314 | ||
311 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
315 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
312 | return false; |
316 | return false; |
313 | 317 | ||
314 | uint32_t page = (badvaddr >> 12) & 0xffff; |
318 | uint32_t page = (badvaddr >> 12) & 0xffff; |
315 | uint32_t api = (badvaddr >> 22) & 0x3f; |
319 | uint32_t api = (badvaddr >> 22) & 0x3f; |
316 | 320 | ||
317 | uint32_t vsid; |
321 | uint32_t vsid; |
318 | asm volatile ( |
322 | asm volatile ( |
319 | "mfsrin %0, %1\n" |
323 | "mfsrin %0, %1\n" |
320 | : "=r" (vsid) |
324 | : "=r" (vsid) |
321 | : "r" (badvaddr) |
325 | : "r" (badvaddr) |
322 | ); |
326 | ); |
323 | 327 | ||
324 | uint32_t sdr1; |
328 | uint32_t sdr1; |
325 | asm volatile ( |
329 | asm volatile ( |
326 | "mfsdr1 %0\n" |
330 | "mfsdr1 %0\n" |
327 | : "=r" (sdr1) |
331 | : "=r" (sdr1) |
328 | ); |
332 | ); |
329 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
333 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
330 | 334 | ||
331 | /* Primary hash (xor) */ |
335 | /* Primary hash (xor) */ |
332 | uint32_t h = 0; |
336 | uint32_t h = 0; |
333 | uint32_t hash = vsid ^ page; |
337 | uint32_t hash = vsid ^ page; |
334 | uint32_t base = (hash & 0x3ff) << 3; |
338 | uint32_t base = (hash & 0x3ff) << 3; |
335 | uint32_t i; |
339 | uint32_t i; |
336 | bool found = false; |
340 | bool found = false; |
337 | 341 | ||
338 | /* Find colliding PTE in PTEG */ |
342 | /* Find colliding PTE in PTEG */ |
339 | for (i = 0; i < 8; i++) { |
343 | for (i = 0; i < 8; i++) { |
340 | if ((phte_real[base + i].v) |
344 | if ((phte_real[base + i].v) |
341 | && (phte_real[base + i].vsid == vsid) |
345 | && (phte_real[base + i].vsid == vsid) |
342 | && (phte_real[base + i].api == api) |
346 | && (phte_real[base + i].api == api) |
343 | && (phte_real[base + i].h == 0)) { |
347 | && (phte_real[base + i].h == 0)) { |
344 | found = true; |
348 | found = true; |
345 | break; |
349 | break; |
346 | } |
350 | } |
347 | } |
351 | } |
348 | 352 | ||
349 | if (!found) { |
353 | if (!found) { |
350 | /* Find unused PTE in PTEG */ |
354 | /* Find unused PTE in PTEG */ |
351 | for (i = 0; i < 8; i++) { |
355 | for (i = 0; i < 8; i++) { |
352 | if (!phte_real[base + i].v) { |
356 | if (!phte_real[base + i].v) { |
353 | found = true; |
357 | found = true; |
354 | break; |
358 | break; |
355 | } |
359 | } |
356 | } |
360 | } |
357 | } |
361 | } |
358 | 362 | ||
359 | if (!found) { |
363 | if (!found) { |
360 | /* Secondary hash (not) */ |
364 | /* Secondary hash (not) */ |
361 | uint32_t base2 = (~hash & 0x3ff) << 3; |
365 | uint32_t base2 = (~hash & 0x3ff) << 3; |
362 | 366 | ||
363 | /* Find colliding PTE in PTEG */ |
367 | /* Find colliding PTE in PTEG */ |
364 | for (i = 0; i < 8; i++) { |
368 | for (i = 0; i < 8; i++) { |
365 | if ((phte_real[base2 + i].v) |
369 | if ((phte_real[base2 + i].v) |
366 | && (phte_real[base2 + i].vsid == vsid) |
370 | && (phte_real[base2 + i].vsid == vsid) |
367 | && (phte_real[base2 + i].api == api) |
371 | && (phte_real[base2 + i].api == api) |
368 | && (phte_real[base2 + i].h == 1)) { |
372 | && (phte_real[base2 + i].h == 1)) { |
369 | found = true; |
373 | found = true; |
370 | base = base2; |
374 | base = base2; |
371 | h = 1; |
375 | h = 1; |
372 | break; |
376 | break; |
373 | } |
377 | } |
374 | } |
378 | } |
375 | 379 | ||
376 | if (!found) { |
380 | if (!found) { |
377 | /* Find unused PTE in PTEG */ |
381 | /* Find unused PTE in PTEG */ |
378 | for (i = 0; i < 8; i++) { |
382 | for (i = 0; i < 8; i++) { |
379 | if (!phte_real[base2 + i].v) { |
383 | if (!phte_real[base2 + i].v) { |
380 | found = true; |
384 | found = true; |
381 | base = base2; |
385 | base = base2; |
382 | h = 1; |
386 | h = 1; |
383 | break; |
387 | break; |
384 | } |
388 | } |
385 | } |
389 | } |
386 | } |
390 | } |
387 | 391 | ||
388 | if (!found) { |
392 | if (!found) { |
389 | /* Use secondary hash to avoid collisions |
393 | /* Use secondary hash to avoid collisions |
390 | with usual PHT refill handler. */ |
394 | with usual PHT refill handler. */ |
391 | i = RANDI(seed_real) % 8; |
395 | i = RANDI(seed_real) % 8; |
392 | base = base2; |
396 | base = base2; |
393 | h = 1; |
397 | h = 1; |
394 | } |
398 | } |
395 | } |
399 | } |
396 | 400 | ||
397 | phte_real[base + i].v = 1; |
401 | phte_real[base + i].v = 1; |
398 | phte_real[base + i].vsid = vsid; |
402 | phte_real[base + i].vsid = vsid; |
399 | phte_real[base + i].h = h; |
403 | phte_real[base + i].h = h; |
400 | phte_real[base + i].api = api; |
404 | phte_real[base + i].api = api; |
401 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
405 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
402 | phte_real[base + i].r = 0; |
406 | phte_real[base + i].r = 0; |
403 | phte_real[base + i].c = 0; |
407 | phte_real[base + i].c = 0; |
404 | phte_real[base + i].wimg = 0; |
408 | phte_real[base + i].wimg = 0; |
405 | phte_real[base + i].pp = 2; // FIXME |
409 | phte_real[base + i].pp = 2; // FIXME |
406 | 410 | ||
407 | return true; |
411 | return true; |
408 | } |
412 | } |
409 | 413 | ||
410 | 414 | ||
411 | /** Process ITLB/DTLB Miss Exception in Real Mode |
415 | /** Process ITLB/DTLB Miss Exception in Real Mode |
412 | * |
416 | * |
413 | * |
417 | * |
414 | */ |
418 | */ |
415 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
419 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
416 | { |
420 | { |
417 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
421 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
418 | 422 | ||
419 | uint32_t physmem; |
423 | uint32_t physmem; |
420 | asm volatile ( |
424 | asm volatile ( |
421 | "mfsprg3 %0\n" |
425 | "mfsprg3 %0\n" |
422 | : "=r" (physmem) |
426 | : "=r" (physmem) |
423 | ); |
427 | ); |
424 | 428 | ||
425 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
429 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
426 | return; // FIXME |
430 | return; // FIXME |
427 | 431 | ||
428 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
432 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
429 | ptelo.wimg = 0; |
433 | ptelo.wimg = 0; |
430 | ptelo.pp = 2; // FIXME |
434 | ptelo.pp = 2; // FIXME |
431 | 435 | ||
432 | uint32_t index = 0; |
436 | uint32_t index = 0; |
433 | asm volatile ( |
437 | asm volatile ( |
434 | "mtspr 981, %0\n" |
438 | "mtspr 981, %0\n" |
435 | "mtspr 982, %1\n" |
439 | "mtspr 982, %1\n" |
436 | "tlbld %2\n" |
440 | "tlbld %2\n" |
437 | "tlbli %2\n" |
441 | "tlbli %2\n" |
438 | : "=r" (index) |
442 | : "=r" (index) |
439 | : "r" (ptehi), |
443 | : "r" (ptehi), |
440 | "r" (ptelo) |
444 | "r" (ptelo) |
441 | ); |
445 | ); |
442 | } |
446 | } |
443 | 447 | ||
444 | 448 | ||
445 | void tlb_arch_init(void) |
449 | void tlb_arch_init(void) |
446 | { |
450 | { |
447 | tlb_invalidate_all(); |
451 | tlb_invalidate_all(); |
448 | } |
452 | } |
449 | 453 | ||
450 | 454 | ||
451 | void tlb_invalidate_all(void) |
455 | void tlb_invalidate_all(void) |
452 | { |
456 | { |
453 | uint32_t index; |
457 | uint32_t index; |
454 | asm volatile ( |
458 | asm volatile ( |
455 | "li %0, 0\n" |
459 | "li %0, 0\n" |
456 | "sync\n" |
460 | "sync\n" |
457 | 461 | ||
458 | TLB_FLUSH |
462 | TLB_FLUSH |
459 | TLB_FLUSH |
463 | TLB_FLUSH |
460 | TLB_FLUSH |
464 | TLB_FLUSH |
461 | TLB_FLUSH |
465 | TLB_FLUSH |
462 | TLB_FLUSH |
466 | TLB_FLUSH |
463 | TLB_FLUSH |
467 | TLB_FLUSH |
464 | TLB_FLUSH |
468 | TLB_FLUSH |
465 | TLB_FLUSH |
469 | TLB_FLUSH |
466 | 470 | ||
467 | TLB_FLUSH |
471 | TLB_FLUSH |
468 | TLB_FLUSH |
472 | TLB_FLUSH |
469 | TLB_FLUSH |
473 | TLB_FLUSH |
470 | TLB_FLUSH |
474 | TLB_FLUSH |
471 | TLB_FLUSH |
475 | TLB_FLUSH |
472 | TLB_FLUSH |
476 | TLB_FLUSH |
473 | TLB_FLUSH |
477 | TLB_FLUSH |
474 | TLB_FLUSH |
478 | TLB_FLUSH |
475 | 479 | ||
476 | TLB_FLUSH |
480 | TLB_FLUSH |
477 | TLB_FLUSH |
481 | TLB_FLUSH |
478 | TLB_FLUSH |
482 | TLB_FLUSH |
479 | TLB_FLUSH |
483 | TLB_FLUSH |
480 | TLB_FLUSH |
484 | TLB_FLUSH |
481 | TLB_FLUSH |
485 | TLB_FLUSH |
482 | TLB_FLUSH |
486 | TLB_FLUSH |
483 | TLB_FLUSH |
487 | TLB_FLUSH |
484 | 488 | ||
485 | TLB_FLUSH |
489 | TLB_FLUSH |
486 | TLB_FLUSH |
490 | TLB_FLUSH |
487 | TLB_FLUSH |
491 | TLB_FLUSH |
488 | TLB_FLUSH |
492 | TLB_FLUSH |
489 | TLB_FLUSH |
493 | TLB_FLUSH |
490 | TLB_FLUSH |
494 | TLB_FLUSH |
491 | TLB_FLUSH |
495 | TLB_FLUSH |
492 | TLB_FLUSH |
496 | TLB_FLUSH |
493 | 497 | ||
494 | TLB_FLUSH |
498 | TLB_FLUSH |
495 | TLB_FLUSH |
499 | TLB_FLUSH |
496 | TLB_FLUSH |
500 | TLB_FLUSH |
497 | TLB_FLUSH |
501 | TLB_FLUSH |
498 | TLB_FLUSH |
502 | TLB_FLUSH |
499 | TLB_FLUSH |
503 | TLB_FLUSH |
500 | TLB_FLUSH |
504 | TLB_FLUSH |
501 | TLB_FLUSH |
505 | TLB_FLUSH |
502 | 506 | ||
503 | TLB_FLUSH |
507 | TLB_FLUSH |
504 | TLB_FLUSH |
508 | TLB_FLUSH |
505 | TLB_FLUSH |
509 | TLB_FLUSH |
506 | TLB_FLUSH |
510 | TLB_FLUSH |
507 | TLB_FLUSH |
511 | TLB_FLUSH |
508 | TLB_FLUSH |
512 | TLB_FLUSH |
509 | TLB_FLUSH |
513 | TLB_FLUSH |
510 | TLB_FLUSH |
514 | TLB_FLUSH |
511 | 515 | ||
512 | TLB_FLUSH |
516 | TLB_FLUSH |
513 | TLB_FLUSH |
517 | TLB_FLUSH |
514 | TLB_FLUSH |
518 | TLB_FLUSH |
515 | TLB_FLUSH |
519 | TLB_FLUSH |
516 | TLB_FLUSH |
520 | TLB_FLUSH |
517 | TLB_FLUSH |
521 | TLB_FLUSH |
518 | TLB_FLUSH |
522 | TLB_FLUSH |
519 | TLB_FLUSH |
523 | TLB_FLUSH |
520 | 524 | ||
521 | TLB_FLUSH |
525 | TLB_FLUSH |
522 | TLB_FLUSH |
526 | TLB_FLUSH |
523 | TLB_FLUSH |
527 | TLB_FLUSH |
524 | TLB_FLUSH |
528 | TLB_FLUSH |
525 | TLB_FLUSH |
529 | TLB_FLUSH |
526 | TLB_FLUSH |
530 | TLB_FLUSH |
527 | TLB_FLUSH |
531 | TLB_FLUSH |
528 | TLB_FLUSH |
532 | TLB_FLUSH |
529 | 533 | ||
530 | "eieio\n" |
534 | "eieio\n" |
531 | "tlbsync\n" |
535 | "tlbsync\n" |
532 | "sync\n" |
536 | "sync\n" |
533 | : "=r" (index) |
537 | : "=r" (index) |
534 | ); |
538 | ); |
535 | } |
539 | } |
536 | 540 | ||
537 | 541 | ||
538 | void tlb_invalidate_asid(asid_t asid) |
542 | void tlb_invalidate_asid(asid_t asid) |
539 | { |
543 | { |
540 | uint32_t sdr1; |
544 | uint32_t sdr1; |
541 | asm volatile ( |
545 | asm volatile ( |
542 | "mfsdr1 %0\n" |
546 | "mfsdr1 %0\n" |
543 | : "=r" (sdr1) |
547 | : "=r" (sdr1) |
544 | ); |
548 | ); |
545 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
549 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
546 | 550 | ||
547 | uint32_t i; |
551 | uint32_t i; |
548 | for (i = 0; i < 8192; i++) { |
552 | for (i = 0; i < 8192; i++) { |
549 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
553 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
550 | (phte[i].vsid < ((asid << 4) + 16))) |
554 | (phte[i].vsid < ((asid << 4) + 16))) |
551 | phte[i].v = 0; |
555 | phte[i].v = 0; |
552 | } |
556 | } |
553 | tlb_invalidate_all(); |
557 | tlb_invalidate_all(); |
554 | } |
558 | } |
555 | 559 | ||
556 | 560 | ||
557 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
561 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
558 | { |
562 | { |
559 | // TODO |
563 | // TODO |
560 | tlb_invalidate_all(); |
564 | tlb_invalidate_all(); |
561 | } |
565 | } |
562 | 566 | ||
563 | 567 | ||
564 | #define PRINT_BAT(name, ureg, lreg) \ |
568 | #define PRINT_BAT(name, ureg, lreg) \ |
565 | asm volatile ( \ |
569 | asm volatile ( \ |
566 | "mfspr %0," #ureg "\n" \ |
570 | "mfspr %0," #ureg "\n" \ |
567 | "mfspr %1," #lreg "\n" \ |
571 | "mfspr %1," #lreg "\n" \ |
568 | : "=r" (upper), "=r" (lower) \ |
572 | : "=r" (upper), "=r" (lower) \ |
569 | ); \ |
573 | ); \ |
570 | mask = (upper & 0x1ffc) >> 2; \ |
574 | mask = (upper & 0x1ffc) >> 2; \ |
571 | if (upper & 3) { \ |
575 | if (upper & 3) { \ |
572 | uint32_t tmp = mask; \ |
576 | uint32_t tmp = mask; \ |
573 | length = 128; \ |
577 | length = 128; \ |
574 | while (tmp) { \ |
578 | while (tmp) { \ |
575 | if ((tmp & 1) == 0) { \ |
579 | if ((tmp & 1) == 0) { \ |
576 | printf("ibat[0]: error in mask\n"); \ |
580 | printf("ibat[0]: error in mask\n"); \ |
577 | break; \ |
581 | break; \ |
578 | } \ |
582 | } \ |
579 | length <<= 1; \ |
583 | length <<= 1; \ |
580 | tmp >>= 1; \ |
584 | tmp >>= 1; \ |
581 | } \ |
585 | } \ |
582 | } else \ |
586 | } else \ |
583 | length = 0; \ |
587 | length = 0; \ |
584 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
588 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
585 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
589 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
586 | lower & 0xffff0000, length, mask, \ |
590 | lower & 0xffff0000, length, mask, \ |
587 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
591 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
588 | (upper & 1) ? " user" : ""); |
592 | (upper & 1) ? " user" : ""); |
589 | 593 | ||
590 | 594 | ||
591 | void tlb_print(void) |
595 | void tlb_print(void) |
592 | { |
596 | { |
593 | uint32_t sr; |
597 | uint32_t sr; |
594 | 598 | ||
595 | for (sr = 0; sr < 16; sr++) { |
599 | for (sr = 0; sr < 16; sr++) { |
596 | uint32_t vsid; |
600 | uint32_t vsid; |
597 | asm volatile ( |
601 | asm volatile ( |
598 | "mfsrin %0, %1\n" |
602 | "mfsrin %0, %1\n" |
599 | : "=r" (vsid) |
603 | : "=r" (vsid) |
600 | : "r" (sr << 28) |
604 | : "r" (sr << 28) |
601 | ); |
605 | ); |
602 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
606 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
603 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
607 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
604 | ((vsid >> 30) & 1) ? " supervisor" : "", |
608 | ((vsid >> 30) & 1) ? " supervisor" : "", |
605 | ((vsid >> 29) & 1) ? " user" : ""); |
609 | ((vsid >> 29) & 1) ? " user" : ""); |
606 | } |
610 | } |
607 | 611 | ||
608 | uint32_t upper; |
612 | uint32_t upper; |
609 | uint32_t lower; |
613 | uint32_t lower; |
610 | uint32_t mask; |
614 | uint32_t mask; |
611 | uint32_t length; |
615 | uint32_t length; |
612 | 616 | ||
613 | PRINT_BAT("ibat[0]", 528, 529); |
617 | PRINT_BAT("ibat[0]", 528, 529); |
614 | PRINT_BAT("ibat[1]", 530, 531); |
618 | PRINT_BAT("ibat[1]", 530, 531); |
615 | PRINT_BAT("ibat[2]", 532, 533); |
619 | PRINT_BAT("ibat[2]", 532, 533); |
616 | PRINT_BAT("ibat[3]", 534, 535); |
620 | PRINT_BAT("ibat[3]", 534, 535); |
617 | 621 | ||
618 | PRINT_BAT("dbat[0]", 536, 537); |
622 | PRINT_BAT("dbat[0]", 536, 537); |
619 | PRINT_BAT("dbat[1]", 538, 539); |
623 | PRINT_BAT("dbat[1]", 538, 539); |
620 | PRINT_BAT("dbat[2]", 540, 541); |
624 | PRINT_BAT("dbat[2]", 540, 541); |
621 | PRINT_BAT("dbat[3]", 542, 543); |
625 | PRINT_BAT("dbat[3]", 542, 543); |
622 | } |
626 | } |
623 | 627 | ||
624 | /** @} |
628 | /** @} |
625 | */ |
629 | */ |
626 | 630 |