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1 | # |
1 | # |
2 | # Copyright (C) 2006 Martin Decky |
2 | # Copyright (c) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/asm/regname.h> |
29 | #include <arch/asm/regname.h> |
30 | #include <arch/context_offset.h> |
30 | #include <arch/context_offset.h> |
31 | 31 | ||
32 | .text |
32 | .text |
33 | 33 | ||
34 | .global fpu_context_save |
34 | .global fpu_context_save |
35 | .global fpu_context_restore |
35 | .global fpu_context_restore |
36 | .global fpu_init |
36 | .global fpu_init |
37 | .global fpu_enable |
37 | .global fpu_enable |
38 | .global fpu_disable |
38 | .global fpu_disable |
39 | 39 | ||
40 | .macro FPU_CONTEXT_STORE r |
40 | .macro FPU_CONTEXT_STORE r |
41 | stfd fr14, OFFSET_FR14(\r) |
41 | stfd fr14, OFFSET_FR14(\r) |
42 | stfd fr15, OFFSET_FR15(\r) |
42 | stfd fr15, OFFSET_FR15(\r) |
43 | stfd fr16, OFFSET_FR16(\r) |
43 | stfd fr16, OFFSET_FR16(\r) |
44 | stfd fr17, OFFSET_FR17(\r) |
44 | stfd fr17, OFFSET_FR17(\r) |
45 | stfd fr18, OFFSET_FR18(\r) |
45 | stfd fr18, OFFSET_FR18(\r) |
46 | stfd fr19, OFFSET_FR19(\r) |
46 | stfd fr19, OFFSET_FR19(\r) |
47 | stfd fr20, OFFSET_FR20(\r) |
47 | stfd fr20, OFFSET_FR20(\r) |
48 | stfd fr21, OFFSET_FR21(\r) |
48 | stfd fr21, OFFSET_FR21(\r) |
49 | stfd fr22, OFFSET_FR22(\r) |
49 | stfd fr22, OFFSET_FR22(\r) |
50 | stfd fr23, OFFSET_FR23(\r) |
50 | stfd fr23, OFFSET_FR23(\r) |
51 | stfd fr24, OFFSET_FR24(\r) |
51 | stfd fr24, OFFSET_FR24(\r) |
52 | stfd fr25, OFFSET_FR25(\r) |
52 | stfd fr25, OFFSET_FR25(\r) |
53 | stfd fr26, OFFSET_FR26(\r) |
53 | stfd fr26, OFFSET_FR26(\r) |
54 | stfd fr27, OFFSET_FR27(\r) |
54 | stfd fr27, OFFSET_FR27(\r) |
55 | stfd fr28, OFFSET_FR28(\r) |
55 | stfd fr28, OFFSET_FR28(\r) |
56 | stfd fr29, OFFSET_FR29(\r) |
56 | stfd fr29, OFFSET_FR29(\r) |
57 | stfd fr30, OFFSET_FR30(\r) |
57 | stfd fr30, OFFSET_FR30(\r) |
58 | stfd fr31, OFFSET_FR31(\r) |
58 | stfd fr31, OFFSET_FR31(\r) |
59 | .endm |
59 | .endm |
60 | 60 | ||
61 | .macro FPU_CONTEXT_LOAD r |
61 | .macro FPU_CONTEXT_LOAD r |
62 | lfd fr14, OFFSET_FR14(\r) |
62 | lfd fr14, OFFSET_FR14(\r) |
63 | lfd fr15, OFFSET_FR15(\r) |
63 | lfd fr15, OFFSET_FR15(\r) |
64 | lfd fr16, OFFSET_FR16(\r) |
64 | lfd fr16, OFFSET_FR16(\r) |
65 | lfd fr17, OFFSET_FR17(\r) |
65 | lfd fr17, OFFSET_FR17(\r) |
66 | lfd fr18, OFFSET_FR18(\r) |
66 | lfd fr18, OFFSET_FR18(\r) |
67 | lfd fr19, OFFSET_FR19(\r) |
67 | lfd fr19, OFFSET_FR19(\r) |
68 | lfd fr20, OFFSET_FR20(\r) |
68 | lfd fr20, OFFSET_FR20(\r) |
69 | lfd fr21, OFFSET_FR21(\r) |
69 | lfd fr21, OFFSET_FR21(\r) |
70 | lfd fr22, OFFSET_FR22(\r) |
70 | lfd fr22, OFFSET_FR22(\r) |
71 | lfd fr23, OFFSET_FR23(\r) |
71 | lfd fr23, OFFSET_FR23(\r) |
72 | lfd fr24, OFFSET_FR24(\r) |
72 | lfd fr24, OFFSET_FR24(\r) |
73 | lfd fr25, OFFSET_FR25(\r) |
73 | lfd fr25, OFFSET_FR25(\r) |
74 | lfd fr26, OFFSET_FR26(\r) |
74 | lfd fr26, OFFSET_FR26(\r) |
75 | lfd fr27, OFFSET_FR27(\r) |
75 | lfd fr27, OFFSET_FR27(\r) |
76 | lfd fr28, OFFSET_FR28(\r) |
76 | lfd fr28, OFFSET_FR28(\r) |
77 | lfd fr29, OFFSET_FR29(\r) |
77 | lfd fr29, OFFSET_FR29(\r) |
78 | lfd fr30, OFFSET_FR30(\r) |
78 | lfd fr30, OFFSET_FR30(\r) |
79 | lfd fr31, OFFSET_FR31(\r) |
79 | lfd fr31, OFFSET_FR31(\r) |
80 | .endm |
80 | .endm |
81 | 81 | ||
82 | fpu_context_save: |
82 | fpu_context_save: |
83 | // FPU_CONTEXT_STORE r3 |
83 | // FPU_CONTEXT_STORE r3 |
84 | // |
84 | // |
85 | // mffs fr0 |
85 | // mffs fr0 |
86 | // stfd fr0, OFFSET_FPSCR(r3) |
86 | // stfd fr0, OFFSET_FPSCR(r3) |
87 | 87 | ||
88 | blr |
88 | blr |
89 | 89 | ||
90 | fpu_context_restore: |
90 | fpu_context_restore: |
91 | // FPU_CONTEXT_LOAD r3 |
91 | // FPU_CONTEXT_LOAD r3 |
92 | // |
92 | // |
93 | // lfd fr0, OFFSET_FPSCR(r3) |
93 | // lfd fr0, OFFSET_FPSCR(r3) |
94 | // mtfsf 7, fr0 |
94 | // mtfsf 7, fr0 |
95 | 95 | ||
96 | blr |
96 | blr |
97 | 97 | ||
98 | fpu_init: |
98 | fpu_init: |
99 | blr |
99 | blr |
100 | 100 | ||
101 | fpu_enable: |
101 | fpu_enable: |
102 | blr |
102 | blr |
103 | 103 | ||
104 | fpu_disable: |
104 | fpu_disable: |
105 | blr |
105 | blr |
106 | 106 | ||
107 | 107 | ||
108 |
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108 |
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109 | 109 | ||
110 | 110 | ||
111 | 111 |