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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Martin Decky |
2 | * Copyright (C) 2005 Martin Decky |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ppc32_ASM_H__ |
29 | #ifndef __ppc32_ASM_H__ |
30 | #define __ppc32_ASM_H__ |
30 | #define __ppc32_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | 34 | ||
35 | /** Enable interrupts. |
35 | /** Enable interrupts. |
36 | * |
36 | * |
37 | * Enable interrupts and return previous |
37 | * Enable interrupts and return previous |
38 | * value of EE. |
38 | * value of EE. |
39 | * |
39 | * |
40 | * @return Old interrupt priority level. |
40 | * @return Old interrupt priority level. |
41 | */ |
41 | */ |
42 | static inline ipl_t interrupts_enable(void) { |
42 | static inline ipl_t interrupts_enable(void) { |
43 | ipl_t v; |
43 | ipl_t v; |
44 | ipl_t tmp; |
44 | ipl_t tmp; |
45 | 45 | ||
46 | __asm__ volatile ( |
46 | __asm__ volatile ( |
47 | "mfmsr %0\n" |
47 | "mfmsr %0\n" |
48 | "mfmsr %1\n" |
48 | "mfmsr %1\n" |
49 | // "ori %1, %1, 1 << 15\n" |
49 | "ori %1, %1, 1 << 15\n" |
50 | "mtmsr %1\n" |
50 | "mtmsr %1\n" |
51 | : "=r" (v), "=r" (tmp) |
51 | : "=r" (v), "=r" (tmp) |
52 | ); |
52 | ); |
53 | return v; |
53 | return v; |
54 | } |
54 | } |
55 | 55 | ||
56 | /** Disable interrupts. |
56 | /** Disable interrupts. |
57 | * |
57 | * |
58 | * Disable interrupts and return previous |
58 | * Disable interrupts and return previous |
59 | * value of EE. |
59 | * value of EE. |
60 | * |
60 | * |
61 | * @return Old interrupt priority level. |
61 | * @return Old interrupt priority level. |
62 | */ |
62 | */ |
63 | static inline ipl_t interrupts_disable(void) { |
63 | static inline ipl_t interrupts_disable(void) { |
64 | ipl_t v; |
64 | ipl_t v; |
65 | ipl_t tmp; |
65 | ipl_t tmp; |
66 | 66 | ||
67 | __asm__ volatile ( |
67 | __asm__ volatile ( |
68 | "mfmsr %0\n" |
68 | "mfmsr %0\n" |
69 | "mfmsr %1\n" |
69 | "mfmsr %1\n" |
70 | "rlwinm %1, %1, 0, 17, 15\n" |
70 | "rlwinm %1, %1, 0, 17, 15\n" |
71 | "mtmsr %1\n" |
71 | "mtmsr %1\n" |
72 | : "=r" (v), "=r" (tmp) |
72 | : "=r" (v), "=r" (tmp) |
73 | ); |
73 | ); |
74 | return v; |
74 | return v; |
75 | } |
75 | } |
76 | 76 | ||
77 | /** Restore interrupt priority level. |
77 | /** Restore interrupt priority level. |
78 | * |
78 | * |
79 | * Restore EE. |
79 | * Restore EE. |
80 | * |
80 | * |
81 | * @param ipl Saved interrupt priority level. |
81 | * @param ipl Saved interrupt priority level. |
82 | */ |
82 | */ |
83 | static inline void interrupts_restore(ipl_t ipl) { |
83 | static inline void interrupts_restore(ipl_t ipl) { |
84 | ipl_t tmp; |
84 | ipl_t tmp; |
85 | 85 | ||
86 | __asm__ volatile ( |
86 | __asm__ volatile ( |
87 | "mfmsr %1\n" |
87 | "mfmsr %1\n" |
88 | "rlwimi %0, %1, 0, 17, 15\n" |
88 | "rlwimi %0, %1, 0, 17, 15\n" |
89 | "cmpw 0, %0, %1\n" |
89 | "cmpw 0, %0, %1\n" |
90 | "beq 0f\n" |
90 | "beq 0f\n" |
91 | "mtmsr %0\n" |
91 | "mtmsr %0\n" |
92 | "0:\n" |
92 | "0:\n" |
93 | : "=r" (ipl), "=r" (tmp) |
93 | : "=r" (ipl), "=r" (tmp) |
94 | : "0" (ipl) |
94 | : "0" (ipl) |
95 | ); |
95 | ); |
96 | } |
96 | } |
97 | 97 | ||
98 | /** Return interrupt priority level. |
98 | /** Return interrupt priority level. |
99 | * |
99 | * |
100 | * Return EE. |
100 | * Return EE. |
101 | * |
101 | * |
102 | * @return Current interrupt priority level. |
102 | * @return Current interrupt priority level. |
103 | */ |
103 | */ |
104 | static inline ipl_t interrupts_read(void) { |
104 | static inline ipl_t interrupts_read(void) { |
105 | ipl_t v; |
105 | ipl_t v; |
106 | __asm__ volatile ( |
106 | __asm__ volatile ( |
107 | "mfmsr %0\n" |
107 | "mfmsr %0\n" |
108 | : "=r" (v) |
108 | : "=r" (v) |
109 | ); |
109 | ); |
110 | return v; |
110 | return v; |
111 | } |
111 | } |
112 | 112 | ||
113 | /** Return base address of current stack. |
113 | /** Return base address of current stack. |
114 | * |
114 | * |
115 | * Return the base address of the current stack. |
115 | * Return the base address of the current stack. |
116 | * The stack is assumed to be STACK_SIZE bytes long. |
116 | * The stack is assumed to be STACK_SIZE bytes long. |
117 | * The stack must start on page boundary. |
117 | * The stack must start on page boundary. |
118 | */ |
118 | */ |
119 | static inline __address get_stack_base(void) |
119 | static inline __address get_stack_base(void) |
120 | { |
120 | { |
121 | __address v; |
121 | __address v; |
122 | 122 | ||
123 | __asm__ volatile ("and %0, %%r1, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
123 | __asm__ volatile ("and %0, %%r1, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
124 | 124 | ||
125 | return v; |
125 | return v; |
126 | } |
126 | } |
127 | 127 | ||
128 | void cpu_halt(void); |
128 | void cpu_halt(void); |
129 | void cpu_sleep(void); |
129 | void cpu_sleep(void); |
130 | void asm_delay_loop(__u32 t); |
130 | void asm_delay_loop(__u32 t); |
131 | 131 | ||
132 | #endif |
132 | #endif |
133 | 133 |