WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/mm/tlb.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm   
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
 
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
 
static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
 
 
 
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception
 *
 * Process TLB Refill Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    spinlock_lock(&AS->lock);
    asid = AS->asid;
    spinlock_unlock(&AS->lock);
 
    page_table_lock(AS, true);
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_hi(&hi, asid, badvaddr);
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr/PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception
 *
 * Process TLB Invalid Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception
 *
 * Process TLB Modified Exception.
 *
 * @param istate Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("unexpected pfrc (%d)\n", pfrc);
        }
    }
 
    /*
     * Fail if the page is not writable.
     */
    if (!pte->w)
        goto fail;
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr/PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->ra);
    if (s)
        sym2 = s;
 
    fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
    panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
 
/** Try to find PTE for faulting address
 *
 * Try to find PTE for faulting address.
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr Faulting virtual address.
 * @param access Access mode that caused the fault.
 * @param istate Pointer to interrupted state.
 * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
            printf("Page fault.\n");
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("unexpected rc (%d)\n", rc);
        }
       
    }
}
 
void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    unsigned int i;
 
    hi_save.value = cp0_entry_hi_read();
   
    printf("#  ASID VPN2   MASK G V D C PFN\n");
    printf("-- ---- ------ ---- - - - - ------\n");
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
            i, hi.asid, hi.vpn2, mask.mask,
            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
        printf("                    %1u %1u %1u %1u %#6x\n",
            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified address space.
 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    unsigned int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt + 1; i += 2) {
        hi.value = 0;
        tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /* Entry was found, index register contains valid index. */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** @}
 */
 

Rev 2745	Rev 3228
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/asid.h>	36	#include <mm/asid.h>
37	#include <mm/tlb.h>	37	#include <mm/tlb.h>
38	#include <mm/page.h>	38	#include <mm/page.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/cp0.h>	40	#include <arch/cp0.h>
41	#include <panic.h>	41	#include <panic.h>
42	#include <arch.h>	42	#include <arch.h>
43	#include <symtab.h>	43	#include <symtab.h>
44	#include <synch/spinlock.h>	44	#include <synch/spinlock.h>
45	#include <print.h>	45	#include <print.h>
46	#include <debug.h>	46	#include <debug.h>
47	#include <align.h>	47	#include <align.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49		49
50	static void tlb_refill_fail(istate_t *istate);	50	static void tlb_refill_fail(istate_t *istate);
51	static void tlb_invalid_fail(istate_t *istate);	51	static void tlb_invalid_fail(istate_t *istate);
52	static void tlb_modified_fail(istate_t *istate);	52	static void tlb_modified_fail(istate_t *istate);
53		53
54	static pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc);	54	static pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc);
55		55
56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);	-
57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);	-
58		-
59	/** Initialize TLB	56	/** Initialize TLB
60	*	57	*
61	* Initialize TLB.	58	* Initialize TLB.
62	* Invalidate all entries and mark wired entries.	59	* Invalidate all entries and mark wired entries.
63	*/	60	*/
64	void tlb_arch_init(void)	61	void tlb_arch_init(void)
65	{	62	{
66	int i;	63	int i;
67		64
68	cp0_pagemask_write(TLB_PAGE_MASK_16K);	65	cp0_pagemask_write(TLB_PAGE_MASK_16K);
69	cp0_entry_hi_write(0);	66	cp0_entry_hi_write(0);
70	cp0_entry_lo0_write(0);	67	cp0_entry_lo0_write(0);
71	cp0_entry_lo1_write(0);	68	cp0_entry_lo1_write(0);
72		69
73	/* Clear and initialize TLB. */	70	/* Clear and initialize TLB. */
74		71
75	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	72	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
76	cp0_index_write(i);	73	cp0_index_write(i);
77	tlbwi();	74	tlbwi();
78	}	75	}
79		-
80		76
81	/*	77	/*
82	* The kernel is going to make use of some wired	78	* The kernel is going to make use of some wired
83	* entries (e.g. mapping kernel stacks in kseg3).	79	* entries (e.g. mapping kernel stacks in kseg3).
84	*/	80	*/
85	cp0_wired_write(TLB_WIRED);	81	cp0_wired_write(TLB_WIRED);
86	}	82	}
87		83
88	/** Process TLB Refill Exception	84	/** Process TLB Refill Exception
89	*	85	*
90	* Process TLB Refill Exception.	86	* Process TLB Refill Exception.
91	*	87	*
92	* @param istate Interrupted register context.	88	* @param istate Interrupted register context.
93	*/	89	*/
94	void tlb_refill(istate_t *istate)	90	void tlb_refill(istate_t *istate)
95	{	91	{
96	entry_lo_t lo;	92	entry_lo_t lo;
97	entry_hi_t hi;	93	entry_hi_t hi;
98	asid_t asid;	94	asid_t asid;
99	uintptr_t badvaddr;	95	uintptr_t badvaddr;
100	pte_t *pte;	96	pte_t *pte;
101	int pfrc;	97	int pfrc;
102		98
103	badvaddr = cp0_badvaddr_read();	99	badvaddr = cp0_badvaddr_read();
104		100
105	spinlock_lock(&AS->lock);	101	spinlock_lock(&AS->lock);
106	asid = AS->asid;	102	asid = AS->asid;
107	spinlock_unlock(&AS->lock);	103	spinlock_unlock(&AS->lock);
108		104
109	page_table_lock(AS, true);	105	page_table_lock(AS, true);
110		106
111	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	107	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
112	if (!pte) {	108	if (!pte) {
113	switch (pfrc) {	109	switch (pfrc) {
114	case AS_PF_FAULT:	110	case AS_PF_FAULT:
115	goto fail;	111	goto fail;
116	break;	112	break;
117	case AS_PF_DEFER:	113	case AS_PF_DEFER:
118	/*	114	/*
119	* The page fault came during copy_from_uspace()	115	* The page fault came during copy_from_uspace()
120	* or copy_to_uspace().	116	* or copy_to_uspace().
121	*/	117	*/
122	page_table_unlock(AS, true);	118	page_table_unlock(AS, true);
123	return;	119	return;
124	default:	120	default:
125	panic("unexpected pfrc (%d)\n", pfrc);	121	panic("unexpected pfrc (%d)\n", pfrc);
126	}	122	}
127	}	123	}
128		124
129	/*	125	/*
130	* Record access to PTE.	126	* Record access to PTE.
131	*/	127	*/
132	pte->a = 1;	128	pte->a = 1;
133		129
134	prepare_entry_hi(&hi, asid, badvaddr);	130	tlb_prepare_entry_hi(&hi, asid, badvaddr);
135	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	131	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
136		132
137	/*	133	/*
138	* New entry is to be inserted into TLB	134	* New entry is to be inserted into TLB
139	*/	135	*/
140	cp0_entry_hi_write(hi.value);	136	cp0_entry_hi_write(hi.value);
141	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	137	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
142	cp0_entry_lo0_write(lo.value);	138	cp0_entry_lo0_write(lo.value);
143	cp0_entry_lo1_write(0);	139	cp0_entry_lo1_write(0);
144	}	140	}
145	else {	141	else {
146	cp0_entry_lo0_write(0);	142	cp0_entry_lo0_write(0);
147	cp0_entry_lo1_write(lo.value);	143	cp0_entry_lo1_write(lo.value);
148	}	144	}
149	cp0_pagemask_write(TLB_PAGE_MASK_16K);	145	cp0_pagemask_write(TLB_PAGE_MASK_16K);
150	tlbwr();	146	tlbwr();
151		147
152	page_table_unlock(AS, true);	148	page_table_unlock(AS, true);
153	return;	149	return;
154		150
155	fail:	151	fail:
156	page_table_unlock(AS, true);	152	page_table_unlock(AS, true);
157	tlb_refill_fail(istate);	153	tlb_refill_fail(istate);
158	}	154	}
159		155
160	/** Process TLB Invalid Exception	156	/** Process TLB Invalid Exception
161	*	157	*
162	* Process TLB Invalid Exception.	158	* Process TLB Invalid Exception.
163	*	159	*
164	* @param istate Interrupted register context.	160	* @param istate Interrupted register context.
165	*/	161	*/
166	void tlb_invalid(istate_t *istate)	162	void tlb_invalid(istate_t *istate)
167	{	163	{
168	tlb_index_t index;	164	tlb_index_t index;
169	uintptr_t badvaddr;	165	uintptr_t badvaddr;
170	entry_lo_t lo;	166	entry_lo_t lo;
171	entry_hi_t hi;	167	entry_hi_t hi;
172	pte_t *pte;	168	pte_t *pte;
173	int pfrc;	169	int pfrc;
174		170
175	badvaddr = cp0_badvaddr_read();	171	badvaddr = cp0_badvaddr_read();
176		172
177	/*	173	/*
178	* Locate the faulting entry in TLB.	174	* Locate the faulting entry in TLB.
179	*/	175	*/
180	hi.value = cp0_entry_hi_read();	176	hi.value = cp0_entry_hi_read();
181	prepare_entry_hi(&hi, hi.asid, badvaddr);	177	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
182	cp0_entry_hi_write(hi.value);	178	cp0_entry_hi_write(hi.value);
183	tlbp();	179	tlbp();
184	index.value = cp0_index_read();	180	index.value = cp0_index_read();
185		181
186	page_table_lock(AS, true);	182	page_table_lock(AS, true);
187		183
188	/*	184	/*
189	* Fail if the entry is not in TLB.	185	* Fail if the entry is not in TLB.
190	*/	186	*/
191	if (index.p) {	187	if (index.p) {
192	printf("TLB entry not found.\n");	188	printf("TLB entry not found.\n");
193	goto fail;	189	goto fail;
194	}	190	}
195		191
196	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	192	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
197	if (!pte) {	193	if (!pte) {
198	switch (pfrc) {	194	switch (pfrc) {
199	case AS_PF_FAULT:	195	case AS_PF_FAULT:
200	goto fail;	196	goto fail;
201	break;	197	break;
202	case AS_PF_DEFER:	198	case AS_PF_DEFER:
203	/*	199	/*
204	* The page fault came during copy_from_uspace()	200	* The page fault came during copy_from_uspace()
205	* or copy_to_uspace().	201	* or copy_to_uspace().
206	*/	202	*/
207	page_table_unlock(AS, true);	203	page_table_unlock(AS, true);
208	return;	204	return;
209	default:	205	default:
210	panic("unexpected pfrc (%d)\n", pfrc);	206	panic("unexpected pfrc (%d)\n", pfrc);
211	}	207	}
212	}	208	}
213		209
214	/*	210	/*
215	* Read the faulting TLB entry.	211	* Read the faulting TLB entry.
216	*/	212	*/
217	tlbr();	213	tlbr();
218		214
219	/*	215	/*
220	* Record access to PTE.	216	* Record access to PTE.
221	*/	217	*/
222	pte->a = 1;	218	pte->a = 1;
223		219
224	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	220	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
225		221
226	/*	222	/*
227	* The entry is to be updated in TLB.	223	* The entry is to be updated in TLB.
228	*/	224	*/
229	if ((badvaddr/PAGE_SIZE) % 2 == 0)	225	if ((badvaddr/PAGE_SIZE) % 2 == 0)
230	cp0_entry_lo0_write(lo.value);	226	cp0_entry_lo0_write(lo.value);
231	else	227	else
232	cp0_entry_lo1_write(lo.value);	228	cp0_entry_lo1_write(lo.value);
233	cp0_pagemask_write(TLB_PAGE_MASK_16K);	229	cp0_pagemask_write(TLB_PAGE_MASK_16K);
234	tlbwi();	230	tlbwi();
235		231
236	page_table_unlock(AS, true);	232	page_table_unlock(AS, true);
237	return;	233	return;
238		234
239	fail:	235	fail:
240	page_table_unlock(AS, true);	236	page_table_unlock(AS, true);
241	tlb_invalid_fail(istate);	237	tlb_invalid_fail(istate);
242	}	238	}
243		239
244	/** Process TLB Modified Exception	240	/** Process TLB Modified Exception
245	*	241	*
246	* Process TLB Modified Exception.	242	* Process TLB Modified Exception.
247	*	243	*
248	* @param istate Interrupted register context.	244	* @param istate Interrupted register context.
249	*/	245	*/
250	void tlb_modified(istate_t *istate)	246	void tlb_modified(istate_t *istate)
251	{	247	{
252	tlb_index_t index;	248	tlb_index_t index;
253	uintptr_t badvaddr;	249	uintptr_t badvaddr;
254	entry_lo_t lo;	250	entry_lo_t lo;
255	entry_hi_t hi;	251	entry_hi_t hi;
256	pte_t *pte;	252	pte_t *pte;
257	int pfrc;	253	int pfrc;
258		254
259	badvaddr = cp0_badvaddr_read();	255	badvaddr = cp0_badvaddr_read();
260		256
261	/*	257	/*
262	* Locate the faulting entry in TLB.	258	* Locate the faulting entry in TLB.
263	*/	259	*/
264	hi.value = cp0_entry_hi_read();	260	hi.value = cp0_entry_hi_read();
265	prepare_entry_hi(&hi, hi.asid, badvaddr);	261	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
266	cp0_entry_hi_write(hi.value);	262	cp0_entry_hi_write(hi.value);
267	tlbp();	263	tlbp();
268	index.value = cp0_index_read();	264	index.value = cp0_index_read();
269		265
270	page_table_lock(AS, true);	266	page_table_lock(AS, true);
271		267
272	/*	268	/*
273	* Fail if the entry is not in TLB.	269	* Fail if the entry is not in TLB.
274	*/	270	*/
275	if (index.p) {	271	if (index.p) {
276	printf("TLB entry not found.\n");	272	printf("TLB entry not found.\n");
277	goto fail;	273	goto fail;
278	}	274	}
279		275
280	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);	276	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
281	if (!pte) {	277	if (!pte) {
282	switch (pfrc) {	278	switch (pfrc) {
283	case AS_PF_FAULT:	279	case AS_PF_FAULT:
284	goto fail;	280	goto fail;
285	break;	281	break;
286	case AS_PF_DEFER:	282	case AS_PF_DEFER:
287	/*	283	/*
288	* The page fault came during copy_from_uspace()	284	* The page fault came during copy_from_uspace()
289	* or copy_to_uspace().	285	* or copy_to_uspace().
290	*/	286	*/
291	page_table_unlock(AS, true);	287	page_table_unlock(AS, true);
292	return;	288	return;
293	default:	289	default:
294	panic("unexpected pfrc (%d)\n", pfrc);	290	panic("unexpected pfrc (%d)\n", pfrc);
295	}	291	}
296	}	292	}
297		293
298	/*	294	/*
299	* Fail if the page is not writable.	295	* Fail if the page is not writable.
300	*/	296	*/
301	if (!pte->w)	297	if (!pte->w)
302	goto fail;	298	goto fail;
303		299
304	/*	300	/*
305	* Read the faulting TLB entry.	301	* Read the faulting TLB entry.
306	*/	302	*/
307	tlbr();	303	tlbr();
308		304
309	/*	305	/*
310	* Record access and write to PTE.	306	* Record access and write to PTE.
311	*/	307	*/
312	pte->a = 1;	308	pte->a = 1;
313	pte->d = 1;	309	pte->d = 1;
314		310
315	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);	311	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
316		312
317	/*	313	/*
318	* The entry is to be updated in TLB.	314	* The entry is to be updated in TLB.
319	*/	315	*/
320	if ((badvaddr/PAGE_SIZE) % 2 == 0)	316	if ((badvaddr/PAGE_SIZE) % 2 == 0)
321	cp0_entry_lo0_write(lo.value);	317	cp0_entry_lo0_write(lo.value);
322	else	318	else
323	cp0_entry_lo1_write(lo.value);	319	cp0_entry_lo1_write(lo.value);
324	cp0_pagemask_write(TLB_PAGE_MASK_16K);	320	cp0_pagemask_write(TLB_PAGE_MASK_16K);
325	tlbwi();	321	tlbwi();
326		322
327	page_table_unlock(AS, true);	323	page_table_unlock(AS, true);
328	return;	324	return;
329		325
330	fail:	326	fail:
331	page_table_unlock(AS, true);	327	page_table_unlock(AS, true);
332	tlb_modified_fail(istate);	328	tlb_modified_fail(istate);
333	}	329	}
334		330
335	void tlb_refill_fail(istate_t *istate)	331	void tlb_refill_fail(istate_t *istate)
336	{	332	{
337	char *symbol = "";	333	char *symbol = "";
338	char *sym2 = "";	334	char *sym2 = "";
339		335
340	char *s = get_symtab_entry(istate->epc);	336	char *s = get_symtab_entry(istate->epc);
341	if (s)	337	if (s)
342	symbol = s;	338	symbol = s;
343	s = get_symtab_entry(istate->ra);	339	s = get_symtab_entry(istate->ra);
344	if (s)	340	if (s)
345	sym2 = s;	341	sym2 = s;
346		342
347	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());	343	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
348	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);	344	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
349	}	345	}
350		346
351		347
352	void tlb_invalid_fail(istate_t *istate)	348	void tlb_invalid_fail(istate_t *istate)
353	{	349	{
354	char *symbol = "";	350	char *symbol = "";
355		351
356	char *s = get_symtab_entry(istate->epc);	352	char *s = get_symtab_entry(istate->epc);
357	if (s)	353	if (s)
358	symbol = s;	354	symbol = s;
359	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());	355	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
360	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	356	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
361	}	357	}
362		358
363	void tlb_modified_fail(istate_t *istate)	359	void tlb_modified_fail(istate_t *istate)
364	{	360	{
365	char *symbol = "";	361	char *symbol = "";
366		362
367	char *s = get_symtab_entry(istate->epc);	363	char *s = get_symtab_entry(istate->epc);
368	if (s)	364	if (s)
369	symbol = s;	365	symbol = s;
370	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());	366	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
371	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	367	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
372	}	368	}
373		369
374	/** Try to find PTE for faulting address	370	/** Try to find PTE for faulting address
375	*	371	*
376	* Try to find PTE for faulting address.	372	* Try to find PTE for faulting address.
377	* The AS->lock must be held on entry to this function.	373	* The AS->lock must be held on entry to this function.
378	*	374	*
379	* @param badvaddr Faulting virtual address.	375	* @param badvaddr Faulting virtual address.
380	* @param access Access mode that caused the fault.	376	* @param access Access mode that caused the fault.
381	* @param istate Pointer to interrupted state.	377	* @param istate Pointer to interrupted state.
382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	378	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
383	*	379	*
384	* @return PTE on success, NULL otherwise.	380	* @return PTE on success, NULL otherwise.
385	*/	381	*/
386	pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc)	382	pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc)
387	{	383	{
388	entry_hi_t hi;	384	entry_hi_t hi;
389	pte_t *pte;	385	pte_t *pte;
390		386
391	hi.value = cp0_entry_hi_read();	387	hi.value = cp0_entry_hi_read();
392		388
393	/*	389	/*
394	* Handler cannot succeed if the ASIDs don't match.	390	* Handler cannot succeed if the ASIDs don't match.
395	*/	391	*/
396	if (hi.asid != AS->asid) {	392	if (hi.asid != AS->asid) {
397	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	393	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
398	return NULL;	394	return NULL;
399	}	395	}
400		396
401	/*	397	/*
402	* Check if the mapping exists in page tables.	398	* Check if the mapping exists in page tables.
403	*/	399	*/
404	pte = page_mapping_find(AS, badvaddr);	400	pte = page_mapping_find(AS, badvaddr);
405	if (pte && pte->p) {	401	if (pte && pte->p) {
406	/*	402	/*
407	* Mapping found in page tables.	403	* Mapping found in page tables.
408	* Immediately succeed.	404	* Immediately succeed.
409	*/	405	*/
410	return pte;	406	return pte;
411	} else {	407	} else {
412	int rc;	408	int rc;
413		409
414	/*	410	/*
415	* Mapping not found in page tables.	411	* Mapping not found in page tables.
416	* Resort to higher-level page fault handler.	412	* Resort to higher-level page fault handler.
417	*/	413	*/
418	page_table_unlock(AS, true);	414	page_table_unlock(AS, true);
419	switch (rc = as_page_fault(badvaddr, access, istate)) {	415	switch (rc = as_page_fault(badvaddr, access, istate)) {
420	case AS_PF_OK:	416	case AS_PF_OK:
421	/*	417	/*
422	* The higher-level page fault handler succeeded,	418	* The higher-level page fault handler succeeded,
423	* The mapping ought to be in place.	419	* The mapping ought to be in place.
424	*/	420	*/
425	page_table_lock(AS, true);	421	page_table_lock(AS, true);
426	pte = page_mapping_find(AS, badvaddr);	422	pte = page_mapping_find(AS, badvaddr);
427	ASSERT(pte && pte->p);	423	ASSERT(pte && pte->p);
428	return pte;	424	return pte;
429	break;	425	break;
430	case AS_PF_DEFER:	426	case AS_PF_DEFER:
431	page_table_lock(AS, true);	427	page_table_lock(AS, true);
432	*pfrc = AS_PF_DEFER;	428	*pfrc = AS_PF_DEFER;
433	return NULL;	429	return NULL;
434	break;	430	break;
435	case AS_PF_FAULT:	431	case AS_PF_FAULT:
436	page_table_lock(AS, true);	432	page_table_lock(AS, true);
437	printf("Page fault.\n");	433	printf("Page fault.\n");
438	*pfrc = AS_PF_FAULT;	434	*pfrc = AS_PF_FAULT;
439	return NULL;	435	return NULL;
440	break;	436	break;
441	default:	437	default:
442	panic("unexpected rc (%d)\n", rc);	438	panic("unexpected rc (%d)\n", rc);
443	}	439	}
444		440
445	}	441	}
446	}	442	}
447		443
448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)	444	void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
449	{	445	{
450	lo->value = 0;	446	lo->value = 0;
451	lo->g = g;	447	lo->g = g;
452	lo->v = v;	448	lo->v = v;
453	lo->d = d;	449	lo->d = d;
454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	450	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
455	lo->pfn = pfn;	451	lo->pfn = pfn;
456	}	452	}
457		453
458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)	454	void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
459	{	455	{
460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	456	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
461	hi->asid = asid;	457	hi->asid = asid;
462	}	458	}
463		459
464	/** Print contents of TLB. */	460	/** Print contents of TLB. */
465	void tlb_print(void)	461	void tlb_print(void)
466	{	462	{
467	page_mask_t mask;	463	page_mask_t mask;
468	entry_lo_t lo0, lo1;	464	entry_lo_t lo0, lo1;
469	entry_hi_t hi, hi_save;	465	entry_hi_t hi, hi_save;
470	unsigned int i;	466	unsigned int i;
471		467
472	hi_save.value = cp0_entry_hi_read();	468	hi_save.value = cp0_entry_hi_read();
473		469
474	printf("# ASID VPN2 MASK G V D C PFN\n");	470	printf("# ASID VPN2 MASK G V D C PFN\n");
475	printf("-- ---- ------ ---- - - - - ------\n");	471	printf("-- ---- ------ ---- - - - - ------\n");
476		472
477	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	473	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
478	cp0_index_write(i);	474	cp0_index_write(i);
479	tlbr();	475	tlbr();
480		476
481	mask.value = cp0_pagemask_read();	477	mask.value = cp0_pagemask_read();
482	hi.value = cp0_entry_hi_read();	478	hi.value = cp0_entry_hi_read();
483	lo0.value = cp0_entry_lo0_read();	479	lo0.value = cp0_entry_lo0_read();
484	lo1.value = cp0_entry_lo1_read();	480	lo1.value = cp0_entry_lo1_read();
485		481
486	printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",	482	printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
487	i, hi.asid, hi.vpn2, mask.mask,	483	i, hi.asid, hi.vpn2, mask.mask,
488	lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);	484	lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
489	printf(" %1u %1u %1u %1u %#6x\n",	485	printf(" %1u %1u %1u %1u %#6x\n",
490	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	486	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
491	}	487	}
492		488
493	cp0_entry_hi_write(hi_save.value);	489	cp0_entry_hi_write(hi_save.value);
494	}	490	}
495		491
496	/** Invalidate all not wired TLB entries. */	492	/** Invalidate all not wired TLB entries. */
497	void tlb_invalidate_all(void)	493	void tlb_invalidate_all(void)
498	{	494	{
499	ipl_t ipl;	495	ipl_t ipl;
500	entry_lo_t lo0, lo1;	496	entry_lo_t lo0, lo1;

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/src/mm/tlb.c – Rev 2745 → 3228