WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/mm/tlb.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <synch/mutex.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
 
 
#include <symtab.h>
 
 
static void tlb_refill_fail(istate_t *);
static void tlb_invalid_fail(istate_t *);
static void tlb_modified_fail(istate_t *);
 
static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
 
/** Initialize TLB.
 *
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception.
 *
 * @param istate    Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
   
    badvaddr = cp0_badvaddr_read();
   
    mutex_lock(&AS->lock);
    asid = AS->asid;
    mutex_unlock(&AS->lock);
   
    page_table_lock(AS, true);
   
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_hi(&hi, asid, badvaddr);
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
        pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr / PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception.
 *
 * @param istate    Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
        pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception.
 *
 * @param istate    Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
        pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol, *sym2;
 
 
 
 
 
 
 
 
 
 
 
    symbol = symtab_fmt_name_lookup(istate->epc);
    sym2 = symtab_fmt_name_lookup(istate->ra);
   
    fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(),
        istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol;
 
 
    symbol = symtab_fmt_name_lookup(istate->epc);
 
 
 
 
    fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(),
        istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol;
 
 
    symbol = symtab_fmt_name_lookup(istate->epc);
 
 
 
 
    fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(),
        istate->epc, symbol);
}
 
/** Try to find PTE for faulting address.
 *
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 *
 * @return      PTE on success, NULL otherwise.
 */
pte_t *
find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
    int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            ASSERT(pte->w || access != PF_ACCESS_WRITE);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("Unexpected rc (%d).", rc);
        }
       
    }
}
 
void
tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
    uintptr_t pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    unsigned int i;
 
    hi_save.value = cp0_entry_hi_read();
   
    printf("#  ASID VPN2   MASK G V D C PFN\n");
    printf("-- ---- ------ ---- - - - - ------\n");
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
            i, hi.asid, hi.vpn2, mask.mask,
            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
        printf("                    %1u %1u %1u %1u %#6x\n",
            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified
 * address space.
 *
 * @param asid      Address space identifier.
 * @param page      First page whose TLB entry is to be invalidated.
 * @param cnt       Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    unsigned int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt + 1; i += 2) {
        hi.value = 0;
        tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /*
             * Entry was found, index register contains valid
             * index.
             */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** @}
 */
 

Rev 4132	Rev 4137
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/asid.h>	36	#include <mm/asid.h>
37	#include <mm/tlb.h>	37	#include <mm/tlb.h>
38	#include <mm/page.h>	38	#include <mm/page.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/cp0.h>	40	#include <arch/cp0.h>
41	#include <panic.h>	41	#include <panic.h>
42	#include <arch.h>	42	#include <arch.h>
43	#include <synch/mutex.h>	43	#include <synch/mutex.h>
44	#include <print.h>	44	#include <print.h>
45	#include <debug.h>	45	#include <debug.h>
46	#include <align.h>	46	#include <align.h>
47	#include <interrupt.h>	47	#include <interrupt.h>
48		-
49	#ifdef CONFIG_SYMTAB	-
50	#include <symtab.h>	48	#include <symtab.h>
51	#endif	-
52		49
53	static void tlb_refill_fail(istate_t *);	50	static void tlb_refill_fail(istate_t *);
54	static void tlb_invalid_fail(istate_t *);	51	static void tlb_invalid_fail(istate_t *);
55	static void tlb_modified_fail(istate_t *);	52	static void tlb_modified_fail(istate_t *);
56		53
57	static pte_t find_mapping_and_check(uintptr_t, int, istate_t , int *);	54	static pte_t find_mapping_and_check(uintptr_t, int, istate_t , int *);
58		55
59	/** Initialize TLB.	56	/** Initialize TLB.
60	*	57	*
61	* Invalidate all entries and mark wired entries.	58	* Invalidate all entries and mark wired entries.
62	*/	59	*/
63	void tlb_arch_init(void)	60	void tlb_arch_init(void)
64	{	61	{
65	int i;	62	int i;
66		63
67	cp0_pagemask_write(TLB_PAGE_MASK_16K);	64	cp0_pagemask_write(TLB_PAGE_MASK_16K);
68	cp0_entry_hi_write(0);	65	cp0_entry_hi_write(0);
69	cp0_entry_lo0_write(0);	66	cp0_entry_lo0_write(0);
70	cp0_entry_lo1_write(0);	67	cp0_entry_lo1_write(0);
71		68
72	/* Clear and initialize TLB. */	69	/* Clear and initialize TLB. */
73		70
74	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	71	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
75	cp0_index_write(i);	72	cp0_index_write(i);
76	tlbwi();	73	tlbwi();
77	}	74	}
78		75
79	/*	76	/*
80	* The kernel is going to make use of some wired	77	* The kernel is going to make use of some wired
81	* entries (e.g. mapping kernel stacks in kseg3).	78	* entries (e.g. mapping kernel stacks in kseg3).
82	*/	79	*/
83	cp0_wired_write(TLB_WIRED);	80	cp0_wired_write(TLB_WIRED);
84	}	81	}
85		82
86	/** Process TLB Refill Exception.	83	/** Process TLB Refill Exception.
87	*	84	*
88	* @param istate Interrupted register context.	85	* @param istate Interrupted register context.
89	*/	86	*/
90	void tlb_refill(istate_t *istate)	87	void tlb_refill(istate_t *istate)
91	{	88	{
92	entry_lo_t lo;	89	entry_lo_t lo;
93	entry_hi_t hi;	90	entry_hi_t hi;
94	asid_t asid;	91	asid_t asid;
95	uintptr_t badvaddr;	92	uintptr_t badvaddr;
96	pte_t *pte;	93	pte_t *pte;
97	int pfrc;	94	int pfrc;
98		95
99	badvaddr = cp0_badvaddr_read();	96	badvaddr = cp0_badvaddr_read();
100		97
101	mutex_lock(&AS->lock);	98	mutex_lock(&AS->lock);
102	asid = AS->asid;	99	asid = AS->asid;
103	mutex_unlock(&AS->lock);	100	mutex_unlock(&AS->lock);
104		101
105	page_table_lock(AS, true);	102	page_table_lock(AS, true);
106		103
107	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	104	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
108	if (!pte) {	105	if (!pte) {
109	switch (pfrc) {	106	switch (pfrc) {
110	case AS_PF_FAULT:	107	case AS_PF_FAULT:
111	goto fail;	108	goto fail;
112	break;	109	break;
113	case AS_PF_DEFER:	110	case AS_PF_DEFER:
114	/*	111	/*
115	* The page fault came during copy_from_uspace()	112	* The page fault came during copy_from_uspace()
116	* or copy_to_uspace().	113	* or copy_to_uspace().
117	*/	114	*/
118	page_table_unlock(AS, true);	115	page_table_unlock(AS, true);
119	return;	116	return;
120	default:	117	default:
121	panic("Unexpected pfrc (%d).", pfrc);	118	panic("Unexpected pfrc (%d).", pfrc);
122	}	119	}
123	}	120	}
124		121
125	/*	122	/*
126	* Record access to PTE.	123	* Record access to PTE.
127	*/	124	*/
128	pte->a = 1;	125	pte->a = 1;
129		126
130	tlb_prepare_entry_hi(&hi, asid, badvaddr);	127	tlb_prepare_entry_hi(&hi, asid, badvaddr);
131	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,	128	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
132	pte->pfn);	129	pte->pfn);
133		130
134	/*	131	/*
135	* New entry is to be inserted into TLB	132	* New entry is to be inserted into TLB
136	*/	133	*/
137	cp0_entry_hi_write(hi.value);	134	cp0_entry_hi_write(hi.value);
138	if ((badvaddr / PAGE_SIZE) % 2 == 0) {	135	if ((badvaddr / PAGE_SIZE) % 2 == 0) {
139	cp0_entry_lo0_write(lo.value);	136	cp0_entry_lo0_write(lo.value);
140	cp0_entry_lo1_write(0);	137	cp0_entry_lo1_write(0);
141	}	138	}
142	else {	139	else {
143	cp0_entry_lo0_write(0);	140	cp0_entry_lo0_write(0);
144	cp0_entry_lo1_write(lo.value);	141	cp0_entry_lo1_write(lo.value);
145	}	142	}
146	cp0_pagemask_write(TLB_PAGE_MASK_16K);	143	cp0_pagemask_write(TLB_PAGE_MASK_16K);
147	tlbwr();	144	tlbwr();
148		145
149	page_table_unlock(AS, true);	146	page_table_unlock(AS, true);
150	return;	147	return;
151		148
152	fail:	149	fail:
153	page_table_unlock(AS, true);	150	page_table_unlock(AS, true);
154	tlb_refill_fail(istate);	151	tlb_refill_fail(istate);
155	}	152	}
156		153
157	/** Process TLB Invalid Exception.	154	/** Process TLB Invalid Exception.
158	*	155	*
159	* @param istate Interrupted register context.	156	* @param istate Interrupted register context.
160	*/	157	*/
161	void tlb_invalid(istate_t *istate)	158	void tlb_invalid(istate_t *istate)
162	{	159	{
163	tlb_index_t index;	160	tlb_index_t index;
164	uintptr_t badvaddr;	161	uintptr_t badvaddr;
165	entry_lo_t lo;	162	entry_lo_t lo;
166	entry_hi_t hi;	163	entry_hi_t hi;
167	pte_t *pte;	164	pte_t *pte;
168	int pfrc;	165	int pfrc;
169		166
170	badvaddr = cp0_badvaddr_read();	167	badvaddr = cp0_badvaddr_read();
171		168
172	/*	169	/*
173	* Locate the faulting entry in TLB.	170	* Locate the faulting entry in TLB.
174	*/	171	*/
175	hi.value = cp0_entry_hi_read();	172	hi.value = cp0_entry_hi_read();
176	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);	173	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
177	cp0_entry_hi_write(hi.value);	174	cp0_entry_hi_write(hi.value);
178	tlbp();	175	tlbp();
179	index.value = cp0_index_read();	176	index.value = cp0_index_read();
180		177
181	page_table_lock(AS, true);	178	page_table_lock(AS, true);
182		179
183	/*	180	/*
184	* Fail if the entry is not in TLB.	181	* Fail if the entry is not in TLB.
185	*/	182	*/
186	if (index.p) {	183	if (index.p) {
187	printf("TLB entry not found.\n");	184	printf("TLB entry not found.\n");
188	goto fail;	185	goto fail;
189	}	186	}
190		187
191	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	188	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
192	if (!pte) {	189	if (!pte) {
193	switch (pfrc) {	190	switch (pfrc) {
194	case AS_PF_FAULT:	191	case AS_PF_FAULT:
195	goto fail;	192	goto fail;
196	break;	193	break;
197	case AS_PF_DEFER:	194	case AS_PF_DEFER:
198	/*	195	/*
199	* The page fault came during copy_from_uspace()	196	* The page fault came during copy_from_uspace()
200	* or copy_to_uspace().	197	* or copy_to_uspace().
201	*/	198	*/
202	page_table_unlock(AS, true);	199	page_table_unlock(AS, true);
203	return;	200	return;
204	default:	201	default:
205	panic("Unexpected pfrc (%d).", pfrc);	202	panic("Unexpected pfrc (%d).", pfrc);
206	}	203	}
207	}	204	}
208		205
209	/*	206	/*
210	* Read the faulting TLB entry.	207	* Read the faulting TLB entry.
211	*/	208	*/
212	tlbr();	209	tlbr();
213		210
214	/*	211	/*
215	* Record access to PTE.	212	* Record access to PTE.
216	*/	213	*/
217	pte->a = 1;	214	pte->a = 1;
218		215
219	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,	216	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
220	pte->pfn);	217	pte->pfn);
221		218
222	/*	219	/*
223	* The entry is to be updated in TLB.	220	* The entry is to be updated in TLB.
224	*/	221	*/
225	if ((badvaddr / PAGE_SIZE) % 2 == 0)	222	if ((badvaddr / PAGE_SIZE) % 2 == 0)
226	cp0_entry_lo0_write(lo.value);	223	cp0_entry_lo0_write(lo.value);
227	else	224	else
228	cp0_entry_lo1_write(lo.value);	225	cp0_entry_lo1_write(lo.value);
229	cp0_pagemask_write(TLB_PAGE_MASK_16K);	226	cp0_pagemask_write(TLB_PAGE_MASK_16K);
230	tlbwi();	227	tlbwi();
231		228
232	page_table_unlock(AS, true);	229	page_table_unlock(AS, true);
233	return;	230	return;
234		231
235	fail:	232	fail:
236	page_table_unlock(AS, true);	233	page_table_unlock(AS, true);
237	tlb_invalid_fail(istate);	234	tlb_invalid_fail(istate);
238	}	235	}
239		236
240	/** Process TLB Modified Exception.	237	/** Process TLB Modified Exception.
241	*	238	*
242	* @param istate Interrupted register context.	239	* @param istate Interrupted register context.
243	*/	240	*/
244	void tlb_modified(istate_t *istate)	241	void tlb_modified(istate_t *istate)
245	{	242	{
246	tlb_index_t index;	243	tlb_index_t index;
247	uintptr_t badvaddr;	244	uintptr_t badvaddr;
248	entry_lo_t lo;	245	entry_lo_t lo;
249	entry_hi_t hi;	246	entry_hi_t hi;
250	pte_t *pte;	247	pte_t *pte;
251	int pfrc;	248	int pfrc;
252		249
253	badvaddr = cp0_badvaddr_read();	250	badvaddr = cp0_badvaddr_read();
254		251
255	/*	252	/*
256	* Locate the faulting entry in TLB.	253	* Locate the faulting entry in TLB.
257	*/	254	*/
258	hi.value = cp0_entry_hi_read();	255	hi.value = cp0_entry_hi_read();
259	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);	256	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
260	cp0_entry_hi_write(hi.value);	257	cp0_entry_hi_write(hi.value);
261	tlbp();	258	tlbp();
262	index.value = cp0_index_read();	259	index.value = cp0_index_read();
263		260
264	page_table_lock(AS, true);	261	page_table_lock(AS, true);
265		262
266	/*	263	/*
267	* Fail if the entry is not in TLB.	264	* Fail if the entry is not in TLB.
268	*/	265	*/
269	if (index.p) {	266	if (index.p) {
270	printf("TLB entry not found.\n");	267	printf("TLB entry not found.\n");
271	goto fail;	268	goto fail;
272	}	269	}
273		270
274	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);	271	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
275	if (!pte) {	272	if (!pte) {
276	switch (pfrc) {	273	switch (pfrc) {
277	case AS_PF_FAULT:	274	case AS_PF_FAULT:
278	goto fail;	275	goto fail;
279	break;	276	break;
280	case AS_PF_DEFER:	277	case AS_PF_DEFER:
281	/*	278	/*
282	* The page fault came during copy_from_uspace()	279	* The page fault came during copy_from_uspace()
283	* or copy_to_uspace().	280	* or copy_to_uspace().
284	*/	281	*/
285	page_table_unlock(AS, true);	282	page_table_unlock(AS, true);
286	return;	283	return;
287	default:	284	default:
288	panic("Unexpected pfrc (%d).", pfrc);	285	panic("Unexpected pfrc (%d).", pfrc);
289	}	286	}
290	}	287	}
291		288
292	/*	289	/*
293	* Read the faulting TLB entry.	290	* Read the faulting TLB entry.
294	*/	291	*/
295	tlbr();	292	tlbr();
296		293
297	/*	294	/*
298	* Record access and write to PTE.	295	* Record access and write to PTE.
299	*/	296	*/
300	pte->a = 1;	297	pte->a = 1;
301	pte->d = 1;	298	pte->d = 1;
302		299
303	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,	300	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
304	pte->pfn);	301	pte->pfn);
305		302
306	/*	303	/*
307	* The entry is to be updated in TLB.	304	* The entry is to be updated in TLB.
308	*/	305	*/
309	if ((badvaddr / PAGE_SIZE) % 2 == 0)	306	if ((badvaddr / PAGE_SIZE) % 2 == 0)
310	cp0_entry_lo0_write(lo.value);	307	cp0_entry_lo0_write(lo.value);
311	else	308	else
312	cp0_entry_lo1_write(lo.value);	309	cp0_entry_lo1_write(lo.value);
313	cp0_pagemask_write(TLB_PAGE_MASK_16K);	310	cp0_pagemask_write(TLB_PAGE_MASK_16K);
314	tlbwi();	311	tlbwi();
315		312
316	page_table_unlock(AS, true);	313	page_table_unlock(AS, true);
317	return;	314	return;
318		315
319	fail:	316	fail:
320	page_table_unlock(AS, true);	317	page_table_unlock(AS, true);
321	tlb_modified_fail(istate);	318	tlb_modified_fail(istate);
322	}	319	}
323		320
324	void tlb_refill_fail(istate_t *istate)	321	void tlb_refill_fail(istate_t *istate)
325	{	322	{
326	char *symbol = "";	323	char symbol, sym2;
327	char *sym2 = "";	-
328		-
329	#ifdef CONFIG_SYMTAB	-
330	char *s = get_symtab_entry(istate->epc);	-
331	if (s)	-
332	symbol = s;	-
333	s = get_symtab_entry(istate->ra);	-
334	if (s)	-
335	sym2 = s;	-
336	#endif	-
337		324
-		325	symbol = symtab_fmt_name_lookup(istate->epc);
-		326	sym2 = symtab_fmt_name_lookup(istate->ra);
-		327
338	fault_if_from_uspace(istate, "TLB Refill Exception on %p.",	328	fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
339	cp0_badvaddr_read());	329	cp0_badvaddr_read());
340	panic("%x: TLB Refill Exception at %x(%s<-%s).", cp0_badvaddr_read(),	330	panic("%x: TLB Refill Exception at %x (%s<-%s).", cp0_badvaddr_read(),
341	istate->epc, symbol, sym2);	331	istate->epc, symbol, sym2);
342	}	332	}
343		333
344		334
345	void tlb_invalid_fail(istate_t *istate)	335	void tlb_invalid_fail(istate_t *istate)
346	{	336	{
347	char *symbol = "";	337	char *symbol;
348		338
349	#ifdef CONFIG_SYMTAB	-
350	char *s = get_symtab_entry(istate->epc);	339	symbol = symtab_fmt_name_lookup(istate->epc);
351	if (s)	-
352	symbol = s;	-
353	#endif	-
354		340
355	fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",	341	fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
356	cp0_badvaddr_read());	342	cp0_badvaddr_read());
357	panic("%x: TLB Invalid Exception at %x(%s).", cp0_badvaddr_read(),	343	panic("%x: TLB Invalid Exception at %x (%s).", cp0_badvaddr_read(),
358	istate->epc, symbol);	344	istate->epc, symbol);
359	}	345	}
360		346
361	void tlb_modified_fail(istate_t *istate)	347	void tlb_modified_fail(istate_t *istate)
362	{	348	{
363	char *symbol = "";	349	char *symbol;
364		350
365	#ifdef CONFIG_SYMTAB	-
366	char *s = get_symtab_entry(istate->epc);	351	symbol = symtab_fmt_name_lookup(istate->epc);
367	if (s)	-
368	symbol = s;	-
369	#endif	-
370		352
371	fault_if_from_uspace(istate, "TLB Modified Exception on %p.",	353	fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
372	cp0_badvaddr_read());	354	cp0_badvaddr_read());
373	panic("%x: TLB Modified Exception at %x(%s).", cp0_badvaddr_read(),	355	panic("%x: TLB Modified Exception at %x (%s).", cp0_badvaddr_read(),
374	istate->epc, symbol);	356	istate->epc, symbol);
375	}	357	}
376		358
377	/** Try to find PTE for faulting address.	359	/** Try to find PTE for faulting address.
378	*	360	*
379	* The AS->lock must be held on entry to this function.	361	* The AS->lock must be held on entry to this function.
380	*	362	*
381	* @param badvaddr Faulting virtual address.	363	* @param badvaddr Faulting virtual address.
382	* @param access Access mode that caused the fault.	364	* @param access Access mode that caused the fault.
383	* @param istate Pointer to interrupted state.	365	* @param istate Pointer to interrupted state.
384	* @param pfrc Pointer to variable where as_page_fault() return code	366	* @param pfrc Pointer to variable where as_page_fault() return code
385	* will be stored.	367	* will be stored.
386	*	368	*
387	* @return PTE on success, NULL otherwise.	369	* @return PTE on success, NULL otherwise.
388	*/	370	*/
389	pte_t *	371	pte_t *
390	find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,	372	find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
391	int *pfrc)	373	int *pfrc)
392	{	374	{
393	entry_hi_t hi;	375	entry_hi_t hi;
394	pte_t *pte;	376	pte_t *pte;
395		377
396	hi.value = cp0_entry_hi_read();	378	hi.value = cp0_entry_hi_read();
397		379
398	/*	380	/*
399	* Handler cannot succeed if the ASIDs don't match.	381	* Handler cannot succeed if the ASIDs don't match.
400	*/	382	*/
401	if (hi.asid != AS->asid) {	383	if (hi.asid != AS->asid) {
402	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	384	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
403	return NULL;	385	return NULL;
404	}	386	}
405		387
406	/*	388	/*
407	* Check if the mapping exists in page tables.	389	* Check if the mapping exists in page tables.
408	*/	390	*/
409	pte = page_mapping_find(AS, badvaddr);	391	pte = page_mapping_find(AS, badvaddr);
410	if (pte && pte->p && (pte->w \|\| access != PF_ACCESS_WRITE)) {	392	if (pte && pte->p && (pte->w \|\| access != PF_ACCESS_WRITE)) {
411	/*	393	/*
412	* Mapping found in page tables.	394	* Mapping found in page tables.
413	* Immediately succeed.	395	* Immediately succeed.
414	*/	396	*/
415	return pte;	397	return pte;
416	} else {	398	} else {
417	int rc;	399	int rc;
418		400
419	/*	401	/*
420	* Mapping not found in page tables.	402	* Mapping not found in page tables.
421	* Resort to higher-level page fault handler.	403	* Resort to higher-level page fault handler.
422	*/	404	*/
423	page_table_unlock(AS, true);	405	page_table_unlock(AS, true);
424	switch (rc = as_page_fault(badvaddr, access, istate)) {	406	switch (rc = as_page_fault(badvaddr, access, istate)) {
425	case AS_PF_OK:	407	case AS_PF_OK:
426	/*	408	/*
427	* The higher-level page fault handler succeeded,	409	* The higher-level page fault handler succeeded,
428	* The mapping ought to be in place.	410	* The mapping ought to be in place.
429	*/	411	*/
430	page_table_lock(AS, true);	412	page_table_lock(AS, true);
431	pte = page_mapping_find(AS, badvaddr);	413	pte = page_mapping_find(AS, badvaddr);
432	ASSERT(pte && pte->p);	414	ASSERT(pte && pte->p);
433	ASSERT(pte->w \|\| access != PF_ACCESS_WRITE);	415	ASSERT(pte->w \|\| access != PF_ACCESS_WRITE);
434	return pte;	416	return pte;
435	break;	417	break;
436	case AS_PF_DEFER:	418	case AS_PF_DEFER:
437	page_table_lock(AS, true);	419	page_table_lock(AS, true);
438	*pfrc = AS_PF_DEFER;	420	*pfrc = AS_PF_DEFER;
439	return NULL;	421	return NULL;
440	break;	422	break;
441	case AS_PF_FAULT:	423	case AS_PF_FAULT:
442	page_table_lock(AS, true);	424	page_table_lock(AS, true);
443	*pfrc = AS_PF_FAULT;	425	*pfrc = AS_PF_FAULT;
444	return NULL;	426	return NULL;
445	break;	427	break;
446	default:	428	default:
447	panic("Unexpected rc (%d).", rc);	429	panic("Unexpected rc (%d).", rc);
448	}	430	}
449		431
450	}	432	}
451	}	433	}
452		434
453	void	435	void
454	tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,	436	tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
455	uintptr_t pfn)	437	uintptr_t pfn)
456	{	438	{
457	lo->value = 0;	439	lo->value = 0;
458	lo->g = g;	440	lo->g = g;
459	lo->v = v;	441	lo->v = v;
460	lo->d = d;	442	lo->d = d;
461	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	443	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
462	lo->pfn = pfn;	444	lo->pfn = pfn;
463	}	445	}
464		446
465	void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)	447	void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
466	{	448	{
467	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	449	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
468	hi->asid = asid;	450	hi->asid = asid;
469	}	451	}
470		452
471	/** Print contents of TLB. */	453	/** Print contents of TLB. */
472	void tlb_print(void)	454	void tlb_print(void)
473	{	455	{
474	page_mask_t mask;	456	page_mask_t mask;
475	entry_lo_t lo0, lo1;	457	entry_lo_t lo0, lo1;
476	entry_hi_t hi, hi_save;	458	entry_hi_t hi, hi_save;
477	unsigned int i;	459	unsigned int i;
478		460
479	hi_save.value = cp0_entry_hi_read();	461	hi_save.value = cp0_entry_hi_read();
480		462
481	printf("# ASID VPN2 MASK G V D C PFN\n");	463	printf("# ASID VPN2 MASK G V D C PFN\n");
482	printf("-- ---- ------ ---- - - - - ------\n");	464	printf("-- ---- ------ ---- - - - - ------\n");
483		465
484	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	466	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
485	cp0_index_write(i);	467	cp0_index_write(i);
486	tlbr();	468	tlbr();
487		469
488	mask.value = cp0_pagemask_read();	470	mask.value = cp0_pagemask_read();
489	hi.value = cp0_entry_hi_read();	471	hi.value = cp0_entry_hi_read();
490	lo0.value = cp0_entry_lo0_read();	472	lo0.value = cp0_entry_lo0_read();
491	lo1.value = cp0_entry_lo1_read();	473	lo1.value = cp0_entry_lo1_read();
492		474
493	printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",	475	printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
494	i, hi.asid, hi.vpn2, mask.mask,	476	i, hi.asid, hi.vpn2, mask.mask,
495	lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);	477	lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
496	printf(" %1u %1u %1u %1u %#6x\n",	478	printf(" %1u %1u %1u %1u %#6x\n",
497	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);	479	lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/mips32/src/mm/tlb.c @ 2071 – Rev 4132 → 4137