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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup mips32mm |
29 | /** @addtogroup mips32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/mm/tlb.h> |
35 | #include <arch/mm/tlb.h> |
36 | #include <mm/asid.h> |
36 | #include <mm/asid.h> |
37 | #include <mm/tlb.h> |
37 | #include <mm/tlb.h> |
38 | #include <mm/page.h> |
38 | #include <mm/page.h> |
39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
40 | #include <arch/cp0.h> |
40 | #include <arch/cp0.h> |
41 | #include <panic.h> |
41 | #include <panic.h> |
42 | #include <arch.h> |
42 | #include <arch.h> |
43 | #include <symtab.h> |
- | |
44 | #include <synch/mutex.h> |
43 | #include <synch/mutex.h> |
45 | #include <print.h> |
44 | #include <print.h> |
46 | #include <debug.h> |
45 | #include <debug.h> |
47 | #include <align.h> |
46 | #include <align.h> |
48 | #include <interrupt.h> |
47 | #include <interrupt.h> |
49 | 48 | ||
- | 49 | #ifdef CONFIG_SYMTAB |
|
- | 50 | #include <symtab.h> |
|
- | 51 | #endif |
|
- | 52 | ||
50 | static void tlb_refill_fail(istate_t *); |
53 | static void tlb_refill_fail(istate_t *); |
51 | static void tlb_invalid_fail(istate_t *); |
54 | static void tlb_invalid_fail(istate_t *); |
52 | static void tlb_modified_fail(istate_t *); |
55 | static void tlb_modified_fail(istate_t *); |
53 | 56 | ||
54 | static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *); |
57 | static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *); |
55 | 58 | ||
56 | /** Initialize TLB. |
59 | /** Initialize TLB. |
57 | * |
60 | * |
58 | * Invalidate all entries and mark wired entries. |
61 | * Invalidate all entries and mark wired entries. |
59 | */ |
62 | */ |
60 | void tlb_arch_init(void) |
63 | void tlb_arch_init(void) |
61 | { |
64 | { |
62 | int i; |
65 | int i; |
63 | 66 | ||
64 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
67 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
65 | cp0_entry_hi_write(0); |
68 | cp0_entry_hi_write(0); |
66 | cp0_entry_lo0_write(0); |
69 | cp0_entry_lo0_write(0); |
67 | cp0_entry_lo1_write(0); |
70 | cp0_entry_lo1_write(0); |
68 | 71 | ||
69 | /* Clear and initialize TLB. */ |
72 | /* Clear and initialize TLB. */ |
70 | 73 | ||
71 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
74 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
72 | cp0_index_write(i); |
75 | cp0_index_write(i); |
73 | tlbwi(); |
76 | tlbwi(); |
74 | } |
77 | } |
75 | 78 | ||
76 | /* |
79 | /* |
77 | * The kernel is going to make use of some wired |
80 | * The kernel is going to make use of some wired |
78 | * entries (e.g. mapping kernel stacks in kseg3). |
81 | * entries (e.g. mapping kernel stacks in kseg3). |
79 | */ |
82 | */ |
80 | cp0_wired_write(TLB_WIRED); |
83 | cp0_wired_write(TLB_WIRED); |
81 | } |
84 | } |
82 | 85 | ||
83 | /** Process TLB Refill Exception. |
86 | /** Process TLB Refill Exception. |
84 | * |
87 | * |
85 | * @param istate Interrupted register context. |
88 | * @param istate Interrupted register context. |
86 | */ |
89 | */ |
87 | void tlb_refill(istate_t *istate) |
90 | void tlb_refill(istate_t *istate) |
88 | { |
91 | { |
89 | entry_lo_t lo; |
92 | entry_lo_t lo; |
90 | entry_hi_t hi; |
93 | entry_hi_t hi; |
91 | asid_t asid; |
94 | asid_t asid; |
92 | uintptr_t badvaddr; |
95 | uintptr_t badvaddr; |
93 | pte_t *pte; |
96 | pte_t *pte; |
94 | int pfrc; |
97 | int pfrc; |
95 | 98 | ||
96 | badvaddr = cp0_badvaddr_read(); |
99 | badvaddr = cp0_badvaddr_read(); |
97 | 100 | ||
98 | mutex_lock(&AS->lock); |
101 | mutex_lock(&AS->lock); |
99 | asid = AS->asid; |
102 | asid = AS->asid; |
100 | mutex_unlock(&AS->lock); |
103 | mutex_unlock(&AS->lock); |
101 | 104 | ||
102 | page_table_lock(AS, true); |
105 | page_table_lock(AS, true); |
103 | 106 | ||
104 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
107 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
105 | if (!pte) { |
108 | if (!pte) { |
106 | switch (pfrc) { |
109 | switch (pfrc) { |
107 | case AS_PF_FAULT: |
110 | case AS_PF_FAULT: |
108 | goto fail; |
111 | goto fail; |
109 | break; |
112 | break; |
110 | case AS_PF_DEFER: |
113 | case AS_PF_DEFER: |
111 | /* |
114 | /* |
112 | * The page fault came during copy_from_uspace() |
115 | * The page fault came during copy_from_uspace() |
113 | * or copy_to_uspace(). |
116 | * or copy_to_uspace(). |
114 | */ |
117 | */ |
115 | page_table_unlock(AS, true); |
118 | page_table_unlock(AS, true); |
116 | return; |
119 | return; |
117 | default: |
120 | default: |
118 | panic("Unexpected pfrc (%d).", pfrc); |
121 | panic("Unexpected pfrc (%d).", pfrc); |
119 | } |
122 | } |
120 | } |
123 | } |
121 | 124 | ||
122 | /* |
125 | /* |
123 | * Record access to PTE. |
126 | * Record access to PTE. |
124 | */ |
127 | */ |
125 | pte->a = 1; |
128 | pte->a = 1; |
126 | 129 | ||
127 | tlb_prepare_entry_hi(&hi, asid, badvaddr); |
130 | tlb_prepare_entry_hi(&hi, asid, badvaddr); |
128 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
131 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
129 | pte->pfn); |
132 | pte->pfn); |
130 | 133 | ||
131 | /* |
134 | /* |
132 | * New entry is to be inserted into TLB |
135 | * New entry is to be inserted into TLB |
133 | */ |
136 | */ |
134 | cp0_entry_hi_write(hi.value); |
137 | cp0_entry_hi_write(hi.value); |
135 | if ((badvaddr / PAGE_SIZE) % 2 == 0) { |
138 | if ((badvaddr / PAGE_SIZE) % 2 == 0) { |
136 | cp0_entry_lo0_write(lo.value); |
139 | cp0_entry_lo0_write(lo.value); |
137 | cp0_entry_lo1_write(0); |
140 | cp0_entry_lo1_write(0); |
138 | } |
141 | } |
139 | else { |
142 | else { |
140 | cp0_entry_lo0_write(0); |
143 | cp0_entry_lo0_write(0); |
141 | cp0_entry_lo1_write(lo.value); |
144 | cp0_entry_lo1_write(lo.value); |
142 | } |
145 | } |
143 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
146 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
144 | tlbwr(); |
147 | tlbwr(); |
145 | 148 | ||
146 | page_table_unlock(AS, true); |
149 | page_table_unlock(AS, true); |
147 | return; |
150 | return; |
148 | 151 | ||
149 | fail: |
152 | fail: |
150 | page_table_unlock(AS, true); |
153 | page_table_unlock(AS, true); |
151 | tlb_refill_fail(istate); |
154 | tlb_refill_fail(istate); |
152 | } |
155 | } |
153 | 156 | ||
154 | /** Process TLB Invalid Exception. |
157 | /** Process TLB Invalid Exception. |
155 | * |
158 | * |
156 | * @param istate Interrupted register context. |
159 | * @param istate Interrupted register context. |
157 | */ |
160 | */ |
158 | void tlb_invalid(istate_t *istate) |
161 | void tlb_invalid(istate_t *istate) |
159 | { |
162 | { |
160 | tlb_index_t index; |
163 | tlb_index_t index; |
161 | uintptr_t badvaddr; |
164 | uintptr_t badvaddr; |
162 | entry_lo_t lo; |
165 | entry_lo_t lo; |
163 | entry_hi_t hi; |
166 | entry_hi_t hi; |
164 | pte_t *pte; |
167 | pte_t *pte; |
165 | int pfrc; |
168 | int pfrc; |
166 | 169 | ||
167 | badvaddr = cp0_badvaddr_read(); |
170 | badvaddr = cp0_badvaddr_read(); |
168 | 171 | ||
169 | /* |
172 | /* |
170 | * Locate the faulting entry in TLB. |
173 | * Locate the faulting entry in TLB. |
171 | */ |
174 | */ |
172 | hi.value = cp0_entry_hi_read(); |
175 | hi.value = cp0_entry_hi_read(); |
173 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
176 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
174 | cp0_entry_hi_write(hi.value); |
177 | cp0_entry_hi_write(hi.value); |
175 | tlbp(); |
178 | tlbp(); |
176 | index.value = cp0_index_read(); |
179 | index.value = cp0_index_read(); |
177 | 180 | ||
178 | page_table_lock(AS, true); |
181 | page_table_lock(AS, true); |
179 | 182 | ||
180 | /* |
183 | /* |
181 | * Fail if the entry is not in TLB. |
184 | * Fail if the entry is not in TLB. |
182 | */ |
185 | */ |
183 | if (index.p) { |
186 | if (index.p) { |
184 | printf("TLB entry not found.\n"); |
187 | printf("TLB entry not found.\n"); |
185 | goto fail; |
188 | goto fail; |
186 | } |
189 | } |
187 | 190 | ||
188 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
191 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
189 | if (!pte) { |
192 | if (!pte) { |
190 | switch (pfrc) { |
193 | switch (pfrc) { |
191 | case AS_PF_FAULT: |
194 | case AS_PF_FAULT: |
192 | goto fail; |
195 | goto fail; |
193 | break; |
196 | break; |
194 | case AS_PF_DEFER: |
197 | case AS_PF_DEFER: |
195 | /* |
198 | /* |
196 | * The page fault came during copy_from_uspace() |
199 | * The page fault came during copy_from_uspace() |
197 | * or copy_to_uspace(). |
200 | * or copy_to_uspace(). |
198 | */ |
201 | */ |
199 | page_table_unlock(AS, true); |
202 | page_table_unlock(AS, true); |
200 | return; |
203 | return; |
201 | default: |
204 | default: |
202 | panic("Unexpected pfrc (%d).", pfrc); |
205 | panic("Unexpected pfrc (%d).", pfrc); |
203 | } |
206 | } |
204 | } |
207 | } |
205 | 208 | ||
206 | /* |
209 | /* |
207 | * Read the faulting TLB entry. |
210 | * Read the faulting TLB entry. |
208 | */ |
211 | */ |
209 | tlbr(); |
212 | tlbr(); |
210 | 213 | ||
211 | /* |
214 | /* |
212 | * Record access to PTE. |
215 | * Record access to PTE. |
213 | */ |
216 | */ |
214 | pte->a = 1; |
217 | pte->a = 1; |
215 | 218 | ||
216 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
219 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, |
217 | pte->pfn); |
220 | pte->pfn); |
218 | 221 | ||
219 | /* |
222 | /* |
220 | * The entry is to be updated in TLB. |
223 | * The entry is to be updated in TLB. |
221 | */ |
224 | */ |
222 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
225 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
223 | cp0_entry_lo0_write(lo.value); |
226 | cp0_entry_lo0_write(lo.value); |
224 | else |
227 | else |
225 | cp0_entry_lo1_write(lo.value); |
228 | cp0_entry_lo1_write(lo.value); |
226 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
229 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
227 | tlbwi(); |
230 | tlbwi(); |
228 | 231 | ||
229 | page_table_unlock(AS, true); |
232 | page_table_unlock(AS, true); |
230 | return; |
233 | return; |
231 | 234 | ||
232 | fail: |
235 | fail: |
233 | page_table_unlock(AS, true); |
236 | page_table_unlock(AS, true); |
234 | tlb_invalid_fail(istate); |
237 | tlb_invalid_fail(istate); |
235 | } |
238 | } |
236 | 239 | ||
237 | /** Process TLB Modified Exception. |
240 | /** Process TLB Modified Exception. |
238 | * |
241 | * |
239 | * @param istate Interrupted register context. |
242 | * @param istate Interrupted register context. |
240 | */ |
243 | */ |
241 | void tlb_modified(istate_t *istate) |
244 | void tlb_modified(istate_t *istate) |
242 | { |
245 | { |
243 | tlb_index_t index; |
246 | tlb_index_t index; |
244 | uintptr_t badvaddr; |
247 | uintptr_t badvaddr; |
245 | entry_lo_t lo; |
248 | entry_lo_t lo; |
246 | entry_hi_t hi; |
249 | entry_hi_t hi; |
247 | pte_t *pte; |
250 | pte_t *pte; |
248 | int pfrc; |
251 | int pfrc; |
249 | 252 | ||
250 | badvaddr = cp0_badvaddr_read(); |
253 | badvaddr = cp0_badvaddr_read(); |
251 | 254 | ||
252 | /* |
255 | /* |
253 | * Locate the faulting entry in TLB. |
256 | * Locate the faulting entry in TLB. |
254 | */ |
257 | */ |
255 | hi.value = cp0_entry_hi_read(); |
258 | hi.value = cp0_entry_hi_read(); |
256 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
259 | tlb_prepare_entry_hi(&hi, hi.asid, badvaddr); |
257 | cp0_entry_hi_write(hi.value); |
260 | cp0_entry_hi_write(hi.value); |
258 | tlbp(); |
261 | tlbp(); |
259 | index.value = cp0_index_read(); |
262 | index.value = cp0_index_read(); |
260 | 263 | ||
261 | page_table_lock(AS, true); |
264 | page_table_lock(AS, true); |
262 | 265 | ||
263 | /* |
266 | /* |
264 | * Fail if the entry is not in TLB. |
267 | * Fail if the entry is not in TLB. |
265 | */ |
268 | */ |
266 | if (index.p) { |
269 | if (index.p) { |
267 | printf("TLB entry not found.\n"); |
270 | printf("TLB entry not found.\n"); |
268 | goto fail; |
271 | goto fail; |
269 | } |
272 | } |
270 | 273 | ||
271 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
274 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
272 | if (!pte) { |
275 | if (!pte) { |
273 | switch (pfrc) { |
276 | switch (pfrc) { |
274 | case AS_PF_FAULT: |
277 | case AS_PF_FAULT: |
275 | goto fail; |
278 | goto fail; |
276 | break; |
279 | break; |
277 | case AS_PF_DEFER: |
280 | case AS_PF_DEFER: |
278 | /* |
281 | /* |
279 | * The page fault came during copy_from_uspace() |
282 | * The page fault came during copy_from_uspace() |
280 | * or copy_to_uspace(). |
283 | * or copy_to_uspace(). |
281 | */ |
284 | */ |
282 | page_table_unlock(AS, true); |
285 | page_table_unlock(AS, true); |
283 | return; |
286 | return; |
284 | default: |
287 | default: |
285 | panic("Unexpected pfrc (%d).", pfrc); |
288 | panic("Unexpected pfrc (%d).", pfrc); |
286 | } |
289 | } |
287 | } |
290 | } |
288 | 291 | ||
289 | /* |
292 | /* |
290 | * Read the faulting TLB entry. |
293 | * Read the faulting TLB entry. |
291 | */ |
294 | */ |
292 | tlbr(); |
295 | tlbr(); |
293 | 296 | ||
294 | /* |
297 | /* |
295 | * Record access and write to PTE. |
298 | * Record access and write to PTE. |
296 | */ |
299 | */ |
297 | pte->a = 1; |
300 | pte->a = 1; |
298 | pte->d = 1; |
301 | pte->d = 1; |
299 | 302 | ||
300 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, |
303 | tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, |
301 | pte->pfn); |
304 | pte->pfn); |
302 | 305 | ||
303 | /* |
306 | /* |
304 | * The entry is to be updated in TLB. |
307 | * The entry is to be updated in TLB. |
305 | */ |
308 | */ |
306 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
309 | if ((badvaddr / PAGE_SIZE) % 2 == 0) |
307 | cp0_entry_lo0_write(lo.value); |
310 | cp0_entry_lo0_write(lo.value); |
308 | else |
311 | else |
309 | cp0_entry_lo1_write(lo.value); |
312 | cp0_entry_lo1_write(lo.value); |
310 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
313 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
311 | tlbwi(); |
314 | tlbwi(); |
312 | 315 | ||
313 | page_table_unlock(AS, true); |
316 | page_table_unlock(AS, true); |
314 | return; |
317 | return; |
315 | 318 | ||
316 | fail: |
319 | fail: |
317 | page_table_unlock(AS, true); |
320 | page_table_unlock(AS, true); |
318 | tlb_modified_fail(istate); |
321 | tlb_modified_fail(istate); |
319 | } |
322 | } |
320 | 323 | ||
321 | void tlb_refill_fail(istate_t *istate) |
324 | void tlb_refill_fail(istate_t *istate) |
322 | { |
325 | { |
323 | char *symbol = ""; |
326 | char *symbol = ""; |
324 | char *sym2 = ""; |
327 | char *sym2 = ""; |
325 | 328 | ||
- | 329 | #ifdef CONFIG_SYMTAB |
|
326 | char *s = get_symtab_entry(istate->epc); |
330 | char *s = get_symtab_entry(istate->epc); |
327 | if (s) |
331 | if (s) |
328 | symbol = s; |
332 | symbol = s; |
329 | s = get_symtab_entry(istate->ra); |
333 | s = get_symtab_entry(istate->ra); |
330 | if (s) |
334 | if (s) |
331 | sym2 = s; |
335 | sym2 = s; |
- | 336 | #endif |
|
332 | 337 | ||
333 | fault_if_from_uspace(istate, "TLB Refill Exception on %p.", |
338 | fault_if_from_uspace(istate, "TLB Refill Exception on %p.", |
334 | cp0_badvaddr_read()); |
339 | cp0_badvaddr_read()); |
335 | panic("%x: TLB Refill Exception at %x(%s<-%s).", cp0_badvaddr_read(), |
340 | panic("%x: TLB Refill Exception at %x(%s<-%s).", cp0_badvaddr_read(), |
336 | istate->epc, symbol, sym2); |
341 | istate->epc, symbol, sym2); |
337 | } |
342 | } |
338 | 343 | ||
339 | 344 | ||
340 | void tlb_invalid_fail(istate_t *istate) |
345 | void tlb_invalid_fail(istate_t *istate) |
341 | { |
346 | { |
342 | char *symbol = ""; |
347 | char *symbol = ""; |
343 | 348 | ||
- | 349 | #ifdef CONFIG_SYMTAB |
|
344 | char *s = get_symtab_entry(istate->epc); |
350 | char *s = get_symtab_entry(istate->epc); |
345 | if (s) |
351 | if (s) |
346 | symbol = s; |
352 | symbol = s; |
- | 353 | #endif |
|
- | 354 | ||
347 | fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", |
355 | fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", |
348 | cp0_badvaddr_read()); |
356 | cp0_badvaddr_read()); |
349 | panic("%x: TLB Invalid Exception at %x(%s).", cp0_badvaddr_read(), |
357 | panic("%x: TLB Invalid Exception at %x(%s).", cp0_badvaddr_read(), |
350 | istate->epc, symbol); |
358 | istate->epc, symbol); |
351 | } |
359 | } |
352 | 360 | ||
353 | void tlb_modified_fail(istate_t *istate) |
361 | void tlb_modified_fail(istate_t *istate) |
354 | { |
362 | { |
355 | char *symbol = ""; |
363 | char *symbol = ""; |
356 | 364 | ||
- | 365 | #ifdef CONFIG_SYMTAB |
|
357 | char *s = get_symtab_entry(istate->epc); |
366 | char *s = get_symtab_entry(istate->epc); |
358 | if (s) |
367 | if (s) |
359 | symbol = s; |
368 | symbol = s; |
- | 369 | #endif |
|
- | 370 | ||
360 | fault_if_from_uspace(istate, "TLB Modified Exception on %p.", |
371 | fault_if_from_uspace(istate, "TLB Modified Exception on %p.", |
361 | cp0_badvaddr_read()); |
372 | cp0_badvaddr_read()); |
362 | panic("%x: TLB Modified Exception at %x(%s).", cp0_badvaddr_read(), |
373 | panic("%x: TLB Modified Exception at %x(%s).", cp0_badvaddr_read(), |
363 | istate->epc, symbol); |
374 | istate->epc, symbol); |
364 | } |
375 | } |
365 | 376 | ||
366 | /** Try to find PTE for faulting address. |
377 | /** Try to find PTE for faulting address. |
367 | * |
378 | * |
368 | * The AS->lock must be held on entry to this function. |
379 | * The AS->lock must be held on entry to this function. |
369 | * |
380 | * |
370 | * @param badvaddr Faulting virtual address. |
381 | * @param badvaddr Faulting virtual address. |
371 | * @param access Access mode that caused the fault. |
382 | * @param access Access mode that caused the fault. |
372 | * @param istate Pointer to interrupted state. |
383 | * @param istate Pointer to interrupted state. |
373 | * @param pfrc Pointer to variable where as_page_fault() return code |
384 | * @param pfrc Pointer to variable where as_page_fault() return code |
374 | * will be stored. |
385 | * will be stored. |
375 | * |
386 | * |
376 | * @return PTE on success, NULL otherwise. |
387 | * @return PTE on success, NULL otherwise. |
377 | */ |
388 | */ |
378 | pte_t * |
389 | pte_t * |
379 | find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, |
390 | find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, |
380 | int *pfrc) |
391 | int *pfrc) |
381 | { |
392 | { |
382 | entry_hi_t hi; |
393 | entry_hi_t hi; |
383 | pte_t *pte; |
394 | pte_t *pte; |
384 | 395 | ||
385 | hi.value = cp0_entry_hi_read(); |
396 | hi.value = cp0_entry_hi_read(); |
386 | 397 | ||
387 | /* |
398 | /* |
388 | * Handler cannot succeed if the ASIDs don't match. |
399 | * Handler cannot succeed if the ASIDs don't match. |
389 | */ |
400 | */ |
390 | if (hi.asid != AS->asid) { |
401 | if (hi.asid != AS->asid) { |
391 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
402 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
392 | return NULL; |
403 | return NULL; |
393 | } |
404 | } |
394 | 405 | ||
395 | /* |
406 | /* |
396 | * Check if the mapping exists in page tables. |
407 | * Check if the mapping exists in page tables. |
397 | */ |
408 | */ |
398 | pte = page_mapping_find(AS, badvaddr); |
409 | pte = page_mapping_find(AS, badvaddr); |
399 | if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) { |
410 | if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) { |
400 | /* |
411 | /* |
401 | * Mapping found in page tables. |
412 | * Mapping found in page tables. |
402 | * Immediately succeed. |
413 | * Immediately succeed. |
403 | */ |
414 | */ |
404 | return pte; |
415 | return pte; |
405 | } else { |
416 | } else { |
406 | int rc; |
417 | int rc; |
407 | 418 | ||
408 | /* |
419 | /* |
409 | * Mapping not found in page tables. |
420 | * Mapping not found in page tables. |
410 | * Resort to higher-level page fault handler. |
421 | * Resort to higher-level page fault handler. |
411 | */ |
422 | */ |
412 | page_table_unlock(AS, true); |
423 | page_table_unlock(AS, true); |
413 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
424 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
414 | case AS_PF_OK: |
425 | case AS_PF_OK: |
415 | /* |
426 | /* |
416 | * The higher-level page fault handler succeeded, |
427 | * The higher-level page fault handler succeeded, |
417 | * The mapping ought to be in place. |
428 | * The mapping ought to be in place. |
418 | */ |
429 | */ |
419 | page_table_lock(AS, true); |
430 | page_table_lock(AS, true); |
420 | pte = page_mapping_find(AS, badvaddr); |
431 | pte = page_mapping_find(AS, badvaddr); |
421 | ASSERT(pte && pte->p); |
432 | ASSERT(pte && pte->p); |
422 | ASSERT(pte->w || access != PF_ACCESS_WRITE); |
433 | ASSERT(pte->w || access != PF_ACCESS_WRITE); |
423 | return pte; |
434 | return pte; |
424 | break; |
435 | break; |
425 | case AS_PF_DEFER: |
436 | case AS_PF_DEFER: |
426 | page_table_lock(AS, true); |
437 | page_table_lock(AS, true); |
427 | *pfrc = AS_PF_DEFER; |
438 | *pfrc = AS_PF_DEFER; |
428 | return NULL; |
439 | return NULL; |
429 | break; |
440 | break; |
430 | case AS_PF_FAULT: |
441 | case AS_PF_FAULT: |
431 | page_table_lock(AS, true); |
442 | page_table_lock(AS, true); |
432 | *pfrc = AS_PF_FAULT; |
443 | *pfrc = AS_PF_FAULT; |
433 | return NULL; |
444 | return NULL; |
434 | break; |
445 | break; |
435 | default: |
446 | default: |
436 | panic("Unexpected rc (%d).", rc); |
447 | panic("Unexpected rc (%d).", rc); |
437 | } |
448 | } |
438 | 449 | ||
439 | } |
450 | } |
440 | } |
451 | } |
441 | 452 | ||
442 | void |
453 | void |
443 | tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, |
454 | tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, |
444 | uintptr_t pfn) |
455 | uintptr_t pfn) |
445 | { |
456 | { |
446 | lo->value = 0; |
457 | lo->value = 0; |
447 | lo->g = g; |
458 | lo->g = g; |
448 | lo->v = v; |
459 | lo->v = v; |
449 | lo->d = d; |
460 | lo->d = d; |
450 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
461 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
451 | lo->pfn = pfn; |
462 | lo->pfn = pfn; |
452 | } |
463 | } |
453 | 464 | ||
454 | void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
465 | void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) |
455 | { |
466 | { |
456 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
467 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
457 | hi->asid = asid; |
468 | hi->asid = asid; |
458 | } |
469 | } |
459 | 470 | ||
460 | /** Print contents of TLB. */ |
471 | /** Print contents of TLB. */ |
461 | void tlb_print(void) |
472 | void tlb_print(void) |
462 | { |
473 | { |
463 | page_mask_t mask; |
474 | page_mask_t mask; |
464 | entry_lo_t lo0, lo1; |
475 | entry_lo_t lo0, lo1; |
465 | entry_hi_t hi, hi_save; |
476 | entry_hi_t hi, hi_save; |
466 | unsigned int i; |
477 | unsigned int i; |
467 | 478 | ||
468 | hi_save.value = cp0_entry_hi_read(); |
479 | hi_save.value = cp0_entry_hi_read(); |
469 | 480 | ||
470 | printf("# ASID VPN2 MASK G V D C PFN\n"); |
481 | printf("# ASID VPN2 MASK G V D C PFN\n"); |
471 | printf("-- ---- ------ ---- - - - - ------\n"); |
482 | printf("-- ---- ------ ---- - - - - ------\n"); |
472 | 483 | ||
473 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
484 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
474 | cp0_index_write(i); |
485 | cp0_index_write(i); |
475 | tlbr(); |
486 | tlbr(); |
476 | 487 | ||
477 | mask.value = cp0_pagemask_read(); |
488 | mask.value = cp0_pagemask_read(); |
478 | hi.value = cp0_entry_hi_read(); |
489 | hi.value = cp0_entry_hi_read(); |
479 | lo0.value = cp0_entry_lo0_read(); |
490 | lo0.value = cp0_entry_lo0_read(); |
480 | lo1.value = cp0_entry_lo1_read(); |
491 | lo1.value = cp0_entry_lo1_read(); |
481 | 492 | ||
482 | printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n", |
493 | printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n", |
483 | i, hi.asid, hi.vpn2, mask.mask, |
494 | i, hi.asid, hi.vpn2, mask.mask, |
484 | lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn); |
495 | lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn); |
485 | printf(" %1u %1u %1u %1u %#6x\n", |
496 | printf(" %1u %1u %1u %1u %#6x\n", |
486 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
497 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
487 | } |
498 | } |
488 | 499 | ||
489 | cp0_entry_hi_write(hi_save.value); |
500 | cp0_entry_hi_write(hi_save.value); |
490 | } |
501 | } |
491 | 502 | ||
492 | /** Invalidate all not wired TLB entries. */ |
503 | /** Invalidate all not wired TLB entries. */ |
493 | void tlb_invalidate_all(void) |
504 | void tlb_invalidate_all(void) |
494 | { |
505 | { |
495 | ipl_t ipl; |
506 | ipl_t ipl; |
496 | entry_lo_t lo0, lo1; |
507 | entry_lo_t lo0, lo1; |
497 | entry_hi_t hi_save; |
508 | entry_hi_t hi_save; |
498 | int i; |
509 | int i; |
499 | 510 | ||
500 | hi_save.value = cp0_entry_hi_read(); |
511 | hi_save.value = cp0_entry_hi_read(); |
501 | ipl = interrupts_disable(); |
512 | ipl = interrupts_disable(); |
502 | 513 | ||
503 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
514 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
504 | cp0_index_write(i); |
515 | cp0_index_write(i); |
505 | tlbr(); |
516 | tlbr(); |
506 | 517 | ||
507 | lo0.value = cp0_entry_lo0_read(); |
518 | lo0.value = cp0_entry_lo0_read(); |
508 | lo1.value = cp0_entry_lo1_read(); |
519 | lo1.value = cp0_entry_lo1_read(); |
509 | 520 | ||
510 | lo0.v = 0; |
521 | lo0.v = 0; |
511 | lo1.v = 0; |
522 | lo1.v = 0; |
512 | 523 | ||
513 | cp0_entry_lo0_write(lo0.value); |
524 | cp0_entry_lo0_write(lo0.value); |
514 | cp0_entry_lo1_write(lo1.value); |
525 | cp0_entry_lo1_write(lo1.value); |
515 | 526 | ||
516 | tlbwi(); |
527 | tlbwi(); |
517 | } |
528 | } |
518 | 529 | ||
519 | interrupts_restore(ipl); |
530 | interrupts_restore(ipl); |
520 | cp0_entry_hi_write(hi_save.value); |
531 | cp0_entry_hi_write(hi_save.value); |
521 | } |
532 | } |
522 | 533 | ||
523 | /** Invalidate all TLB entries belonging to specified address space. |
534 | /** Invalidate all TLB entries belonging to specified address space. |
524 | * |
535 | * |
525 | * @param asid Address space identifier. |
536 | * @param asid Address space identifier. |
526 | */ |
537 | */ |
527 | void tlb_invalidate_asid(asid_t asid) |
538 | void tlb_invalidate_asid(asid_t asid) |
528 | { |
539 | { |
529 | ipl_t ipl; |
540 | ipl_t ipl; |
530 | entry_lo_t lo0, lo1; |
541 | entry_lo_t lo0, lo1; |
531 | entry_hi_t hi, hi_save; |
542 | entry_hi_t hi, hi_save; |
532 | int i; |
543 | int i; |
533 | 544 | ||
534 | ASSERT(asid != ASID_INVALID); |
545 | ASSERT(asid != ASID_INVALID); |
535 | 546 | ||
536 | hi_save.value = cp0_entry_hi_read(); |
547 | hi_save.value = cp0_entry_hi_read(); |
537 | ipl = interrupts_disable(); |
548 | ipl = interrupts_disable(); |
538 | 549 | ||
539 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
550 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
540 | cp0_index_write(i); |
551 | cp0_index_write(i); |
541 | tlbr(); |
552 | tlbr(); |
542 | 553 | ||
543 | hi.value = cp0_entry_hi_read(); |
554 | hi.value = cp0_entry_hi_read(); |
544 | 555 | ||
545 | if (hi.asid == asid) { |
556 | if (hi.asid == asid) { |
546 | lo0.value = cp0_entry_lo0_read(); |
557 | lo0.value = cp0_entry_lo0_read(); |
547 | lo1.value = cp0_entry_lo1_read(); |
558 | lo1.value = cp0_entry_lo1_read(); |
548 | 559 | ||
549 | lo0.v = 0; |
560 | lo0.v = 0; |
550 | lo1.v = 0; |
561 | lo1.v = 0; |
551 | 562 | ||
552 | cp0_entry_lo0_write(lo0.value); |
563 | cp0_entry_lo0_write(lo0.value); |
553 | cp0_entry_lo1_write(lo1.value); |
564 | cp0_entry_lo1_write(lo1.value); |
554 | 565 | ||
555 | tlbwi(); |
566 | tlbwi(); |
556 | } |
567 | } |
557 | } |
568 | } |
558 | 569 | ||
559 | interrupts_restore(ipl); |
570 | interrupts_restore(ipl); |
560 | cp0_entry_hi_write(hi_save.value); |
571 | cp0_entry_hi_write(hi_save.value); |
561 | } |
572 | } |
562 | 573 | ||
563 | /** Invalidate TLB entries for specified page range belonging to specified |
574 | /** Invalidate TLB entries for specified page range belonging to specified |
564 | * address space. |
575 | * address space. |
565 | * |
576 | * |
566 | * @param asid Address space identifier. |
577 | * @param asid Address space identifier. |
567 | * @param page First page whose TLB entry is to be invalidated. |
578 | * @param page First page whose TLB entry is to be invalidated. |
568 | * @param cnt Number of entries to invalidate. |
579 | * @param cnt Number of entries to invalidate. |
569 | */ |
580 | */ |
570 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
581 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
571 | { |
582 | { |
572 | unsigned int i; |
583 | unsigned int i; |
573 | ipl_t ipl; |
584 | ipl_t ipl; |
574 | entry_lo_t lo0, lo1; |
585 | entry_lo_t lo0, lo1; |
575 | entry_hi_t hi, hi_save; |
586 | entry_hi_t hi, hi_save; |
576 | tlb_index_t index; |
587 | tlb_index_t index; |
577 | 588 | ||
578 | ASSERT(asid != ASID_INVALID); |
589 | ASSERT(asid != ASID_INVALID); |
579 | 590 | ||
580 | hi_save.value = cp0_entry_hi_read(); |
591 | hi_save.value = cp0_entry_hi_read(); |
581 | ipl = interrupts_disable(); |
592 | ipl = interrupts_disable(); |
582 | 593 | ||
583 | for (i = 0; i < cnt + 1; i += 2) { |
594 | for (i = 0; i < cnt + 1; i += 2) { |
584 | hi.value = 0; |
595 | hi.value = 0; |
585 | tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
596 | tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
586 | cp0_entry_hi_write(hi.value); |
597 | cp0_entry_hi_write(hi.value); |
587 | 598 | ||
588 | tlbp(); |
599 | tlbp(); |
589 | index.value = cp0_index_read(); |
600 | index.value = cp0_index_read(); |
590 | 601 | ||
591 | if (!index.p) { |
602 | if (!index.p) { |
592 | /* |
603 | /* |
593 | * Entry was found, index register contains valid |
604 | * Entry was found, index register contains valid |
594 | * index. |
605 | * index. |
595 | */ |
606 | */ |
596 | tlbr(); |
607 | tlbr(); |
597 | 608 | ||
598 | lo0.value = cp0_entry_lo0_read(); |
609 | lo0.value = cp0_entry_lo0_read(); |
599 | lo1.value = cp0_entry_lo1_read(); |
610 | lo1.value = cp0_entry_lo1_read(); |
600 | 611 | ||
601 | lo0.v = 0; |
612 | lo0.v = 0; |
602 | lo1.v = 0; |
613 | lo1.v = 0; |
603 | 614 | ||
604 | cp0_entry_lo0_write(lo0.value); |
615 | cp0_entry_lo0_write(lo0.value); |
605 | cp0_entry_lo1_write(lo1.value); |
616 | cp0_entry_lo1_write(lo1.value); |
606 | 617 | ||
607 | tlbwi(); |
618 | tlbwi(); |
608 | } |
619 | } |
609 | } |
620 | } |
610 | 621 | ||
611 | interrupts_restore(ipl); |
622 | interrupts_restore(ipl); |
612 | cp0_entry_hi_write(hi_save.value); |
623 | cp0_entry_hi_write(hi_save.value); |
613 | } |
624 | } |
614 | 625 | ||
615 | /** @} |
626 | /** @} |
616 | */ |
627 | */ |
617 | 628 |