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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/interrupt.h> |
29 | #include <arch/interrupt.h> |
30 | #include <arch/types.h> |
30 | #include <arch/types.h> |
31 | #include <arch.h> |
31 | #include <arch.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <time/clock.h> |
33 | #include <time/clock.h> |
34 | #include <panic.h> |
34 | #include <panic.h> |
- | 35 | #include <print.h> |
|
- | 36 | #include <symtab.h> |
|
- | 37 | #include <arch/drivers/arc.h> |
|
- | 38 | ||
- | 39 | static void print_regdump(struct exception_regdump *pstate) |
|
- | 40 | { |
|
- | 41 | char *pcsymbol = ""; |
|
- | 42 | char *rasymbol = ""; |
|
- | 43 | ||
- | 44 | char *s = get_symtab_entry(pstate->epc); |
|
- | 45 | if (s) |
|
- | 46 | pcsymbol = s; |
|
- | 47 | s = get_symtab_entry(pstate->ra); |
|
- | 48 | if (s) |
|
- | 49 | rasymbol = s; |
|
- | 50 | ||
- | 51 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
|
- | 52 | pstate->ra,rasymbol); |
|
- | 53 | } |
|
35 | 54 | ||
36 | pri_t cpu_priority_high(void) |
55 | pri_t cpu_priority_high(void) |
37 | { |
56 | { |
38 | pri_t pri = (pri_t) cp0_status_read(); |
57 | pri_t pri = (pri_t) cp0_status_read(); |
39 | cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
58 | cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
40 | return pri; |
59 | return pri; |
41 | } |
60 | } |
42 | 61 | ||
43 | pri_t cpu_priority_low(void) |
62 | pri_t cpu_priority_low(void) |
44 | { |
63 | { |
45 | pri_t pri = (pri_t) cp0_status_read(); |
64 | pri_t pri = (pri_t) cp0_status_read(); |
46 | cp0_status_write(pri | cp0_status_ie_enabled_bit); |
65 | cp0_status_write(pri | cp0_status_ie_enabled_bit); |
47 | return pri; |
66 | return pri; |
48 | } |
67 | } |
49 | 68 | ||
50 | void cpu_priority_restore(pri_t pri) |
69 | void cpu_priority_restore(pri_t pri) |
51 | { |
70 | { |
52 | cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
71 | cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
53 | } |
72 | } |
54 | 73 | ||
55 | pri_t cpu_priority_read(void) |
74 | pri_t cpu_priority_read(void) |
56 | { |
75 | { |
57 | return cp0_status_read(); |
76 | return cp0_status_read(); |
58 | } |
77 | } |
59 | 78 | ||
60 | void interrupt(void) |
79 | void interrupt(struct exception_regdump *pstate) |
61 | { |
80 | { |
62 | __u32 cause; |
81 | __u32 cause; |
63 | int i; |
82 | int i; |
64 | 83 | ||
65 | /* decode interrupt number and process the interrupt */ |
84 | /* decode interrupt number and process the interrupt */ |
66 | cause = (cp0_cause_read() >> 8) &0xff; |
85 | cause = (cp0_cause_read() >> 8) &0xff; |
67 | 86 | ||
68 | for (i = 0; i < 8; i++) { |
87 | for (i = 0; i < 8; i++) { |
69 | if (cause & (1 << i)) { |
88 | if (cause & (1 << i)) { |
70 | switch (i) { |
89 | switch (i) { |
71 | case 0: /* SW0 - Software interrupt 0 */ |
90 | case 0: /* SW0 - Software interrupt 0 */ |
72 | cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */ |
91 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
73 | break; |
92 | break; |
74 | case 1: /* SW1 - Software interrupt 1 */ |
93 | case 1: /* SW1 - Software interrupt 1 */ |
75 | cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */ |
94 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
76 | break; |
95 | break; |
77 | case 2: /* IRQ0 */ |
96 | case 2: /* IRQ0 */ |
78 | case 3: /* IRQ1 */ |
97 | case 3: /* IRQ1 */ |
79 | case 4: /* IRQ2 */ |
98 | case 4: /* IRQ2 */ |
80 | case 5: /* IRQ3 */ |
99 | case 5: /* IRQ3 */ |
81 | case 6: /* IRQ4 */ |
100 | case 6: /* IRQ4 */ |
- | 101 | print_regdump(pstate); |
|
82 | panic("unhandled interrupt %d\n", i); |
102 | panic("unhandled interrupt %d\n", i); |
83 | break; |
103 | break; |
84 | case TIMER_INTERRUPT: |
104 | case TIMER_INTERRUPT: |
85 | /* clear timer interrupt & set new */ |
105 | /* clear timer interrupt & set new */ |
86 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
106 | cp0_compare_write(cp0_count_read() + cp0_compare_value); |
87 | clock(); |
107 | clock(); |
88 | break; |
108 | break; |
89 | } |
109 | } |
90 | } |
110 | } |
91 | } |
111 | } |
92 | 112 | ||
93 | } |
113 | } |
94 | 114 |