WebSVN – HelenOS – Diff – /trunk/kernel/arch/mips32/src/exception.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/exception.h>
#include <arch/interrupt.h>
#include <panic.h>
#include <arch/cp0.h>
#include <arch/types.h>
#include <arch.h>
 
void exception(void)
{
    int excno;
    __u32 epc;
    __u32 epc_shift = 0;
    pri_t pri;
 
    /*
     * NOTE ON OPERATION ORDERING
     *
     * On entry, cpu_priority_high() must be called before exception bit is cleared.
     * On exit, exception bit must be set before cpu_priority_restore() is called.
     */
 
    pri = cpu_priority_high();
    epc = cp0_epc_read();
    cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
 
    if (THREAD) {
        THREAD->saved_pri = pri;
        THREAD->saved_epc = epc;
    }
    /* decode exception number and process the exception */
    switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
        case EXC_Int:
            interrupt();
            break;
        case EXC_TLBL:
        case EXC_TLBS:
            tlb_invalid();
            break;
        case EXC_Mod:
            panic("unhandled TLB Modification Exception\n");
            break;
        case EXC_AdEL:
            panic("unhandled Address Error Exception - load or instruction fetch\n");
            break;
        case EXC_AdES:
            panic("unhandled Address Error Exception - store\n");
            break;
        case EXC_IBE:
            panic("unhandled Bus Error Exception - fetch instruction\n");
            break;
        case EXC_DBE:
            panic("unhandled Bus Error Exception - data reference: load or store\n");
            break;
        case EXC_Bp:
            /* it is necessary to not re-execute BREAK instruction after returning from Exception handler
               (see page 138 in R4000 Manual for more information) */
            epc_shift = 4;
            break;
        case EXC_RI:
            panic("unhandled Reserved Instruction Exception\n");
            break;
        case EXC_CpU:
            panic("unhandled Coprocessor Unusable Exception\n");
            break;
        case EXC_Ov:
            panic("unhandled Arithmetic Overflow Exception\n");
            break;
        case EXC_Tr:
            panic("unhandled Trap Exception\n");
            break;
        case EXC_VCEI:
            panic("unhandled Virtual Coherency Exception - instruction\n");
            break;
        case EXC_FPE:
            panic("unhandled Floating-Point Exception\n");
            break;
        case EXC_WATCH:
            panic("unhandled reference to WatchHi/WatchLo address\n");
            break;
        case EXC_VCED:
            panic("unhandled Virtual Coherency Exception - data\n");
            break;
        default:
            panic("unhandled exception %d\n", excno);
    }
   
    if (THREAD) {
        pri = THREAD->saved_pri;
        epc = THREAD->saved_epc;
    }
 
    cp0_epc_write(epc + epc_shift);
    cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);
    cpu_priority_restore(pri);
}
 

Rev 195	Rev 213
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/exception.h>	29	#include <arch/exception.h>
30	#include <arch/interrupt.h>	30	#include <arch/interrupt.h>
31	#include <panic.h>	31	#include <panic.h>
32	#include <arch/cp0.h>	32	#include <arch/cp0.h>
33	#include <arch/types.h>	33	#include <arch/types.h>
34	#include <arch.h>	34	#include <arch.h>
35		35
36	void exception(void)	36	void exception(void)
37	{	37	{
38	int excno;	38	int excno;
39	__u32 epc;	39	__u32 epc;
40	__u32 epc_shift = 0;	40	__u32 epc_shift = 0;
41	pri_t pri;	41	pri_t pri;
42		42
-		43	/*
-		44	* NOTE ON OPERATION ORDERING
-		45	*
-		46	* On entry, cpu_priority_high() must be called before exception bit is cleared.
-		47	* On exit, exception bit must be set before cpu_priority_restore() is called.
-		48	*/
-		49
43	pri = cpu_priority_high();	50	pri = cpu_priority_high();
44	epc = cp0_epc_read();	51	epc = cp0_epc_read();
45	cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);	52	cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
46		53
47	if (THREAD) {	54	if (THREAD) {
48	THREAD->saved_pri = pri;	55	THREAD->saved_pri = pri;
49	THREAD->saved_epc = epc;	56	THREAD->saved_epc = epc;
50	}	57	}
51	/* decode exception number and process the exception */	58	/* decode exception number and process the exception */
52	switch (excno = (cp0_cause_read() >> 2) & 0x1f) {	59	switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
53	case EXC_Int:	60	case EXC_Int:
54	interrupt();	61	interrupt();
55	break;	62	break;
56	case EXC_TLBL:	63	case EXC_TLBL:
57	case EXC_TLBS:	64	case EXC_TLBS:
58	tlb_invalid();	65	tlb_invalid();
59	break;	66	break;
60	case EXC_Mod:	67	case EXC_Mod:
61	panic("unhandled TLB Modification Exception\n");	68	panic("unhandled TLB Modification Exception\n");
62	break;	69	break;
63	case EXC_AdEL:	70	case EXC_AdEL:
64	panic("unhandled Address Error Exception - load or instruction fetch\n");	71	panic("unhandled Address Error Exception - load or instruction fetch\n");
65	break;	72	break;
66	case EXC_AdES:	73	case EXC_AdES:
67	panic("unhandled Address Error Exception - store\n");	74	panic("unhandled Address Error Exception - store\n");
68	break;	75	break;
69	case EXC_IBE:	76	case EXC_IBE:
70	panic("unhandled Bus Error Exception - fetch instruction\n");	77	panic("unhandled Bus Error Exception - fetch instruction\n");
71	break;	78	break;
72	case EXC_DBE:	79	case EXC_DBE:
73	panic("unhandled Bus Error Exception - data reference: load or store\n");	80	panic("unhandled Bus Error Exception - data reference: load or store\n");
74	break;	81	break;
75	case EXC_Bp:	82	case EXC_Bp:
76	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler	83	/* it is necessary to not re-execute BREAK instruction after returning from Exception handler
77	(see page 138 in R4000 Manual for more information) */	84	(see page 138 in R4000 Manual for more information) */
78	epc_shift = 4;	85	epc_shift = 4;
79	break;	86	break;
80	case EXC_RI:	87	case EXC_RI:
81	panic("unhandled Reserved Instruction Exception\n");	88	panic("unhandled Reserved Instruction Exception\n");
82	break;	89	break;
83	case EXC_CpU:	90	case EXC_CpU:
84	panic("unhandled Coprocessor Unusable Exception\n");	91	panic("unhandled Coprocessor Unusable Exception\n");
85	break;	92	break;
86	case EXC_Ov:	93	case EXC_Ov:
87	panic("unhandled Arithmetic Overflow Exception\n");	94	panic("unhandled Arithmetic Overflow Exception\n");
88	break;	95	break;
89	case EXC_Tr:	96	case EXC_Tr:
90	panic("unhandled Trap Exception\n");	97	panic("unhandled Trap Exception\n");
91	break;	98	break;
92	case EXC_VCEI:	99	case EXC_VCEI:
93	panic("unhandled Virtual Coherency Exception - instruction\n");	100	panic("unhandled Virtual Coherency Exception - instruction\n");
94	break;	101	break;
95	case EXC_FPE:	102	case EXC_FPE:
96	panic("unhandled Floating-Point Exception\n");	103	panic("unhandled Floating-Point Exception\n");
97	break;	104	break;
98	case EXC_WATCH:	105	case EXC_WATCH:
99	panic("unhandled reference to WatchHi/WatchLo address\n");	106	panic("unhandled reference to WatchHi/WatchLo address\n");
100	break;	107	break;
101	case EXC_VCED:	108	case EXC_VCED:
102	panic("unhandled Virtual Coherency Exception - data\n");	109	panic("unhandled Virtual Coherency Exception - data\n");
103	break;	110	break;
104	default:	111	default:
105	panic("unhandled exception %d\n", excno);	112	panic("unhandled exception %d\n", excno);
106	}	113	}
107		114
108	if (THREAD) {	115	if (THREAD) {
109	pri = THREAD->saved_pri;	116	pri = THREAD->saved_pri;
110	epc = THREAD->saved_epc;	117	epc = THREAD->saved_epc;
111	}	118	}
112		119
113	cp0_epc_write(epc + epc_shift);	120	cp0_epc_write(epc + epc_shift);
114	cp0_status_write(cp0_status_read() \| cp0_status_exl_exception_bit);	121	cp0_status_write(cp0_status_read() \| cp0_status_exl_exception_bit);
115	cpu_priority_restore(pri);	122	cpu_priority_restore(pri);
116	}	123	}
117		124

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(root)/trunk/kernel/arch/mips32/src/exception.c @ 3921 – Rev 195 → 213