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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/exception.h> |
29 | #include <arch/exception.h> |
30 | #include <arch/interrupt.h> |
30 | #include <arch/interrupt.h> |
31 | #include <panic.h> |
31 | #include <panic.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #include <arch.h> |
34 | #include <arch.h> |
- | 35 | #include <debug.h> |
|
35 | 36 | ||
36 | void exception(void) |
37 | void exception(void) |
37 | { |
38 | { |
38 | int excno; |
39 | int excno; |
39 | __u32 epc; |
40 | __u32 epc; |
40 | __u32 epc_shift = 0; |
41 | __u32 epc_shift = 0; |
41 | pri_t pri; |
42 | pri_t pri; |
42 | 43 | ||
- | 44 | ASSERT(CPU != NULL); |
|
- | 45 | ||
43 | /* |
46 | /* |
44 | * NOTE ON OPERATION ORDERING |
47 | * NOTE ON OPERATION ORDERING |
45 | * |
48 | * |
46 | * On entry, cpu_priority_high() must be called before exception bit is cleared. |
49 | * On entry, cpu_priority_high() must be called before exception bit is cleared. |
47 | * On exit, exception bit must be set before cpu_priority_restore() is called. |
50 | * On exit, exception bit must be set before cpu_priority_restore() is called. |
48 | */ |
51 | */ |
49 | 52 | ||
50 | pri = cpu_priority_high(); |
53 | pri = cpu_priority_high(); |
51 | epc = cp0_epc_read(); |
54 | epc = cp0_epc_read(); |
52 | cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit); |
55 | cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit); |
53 | 56 | ||
54 | if (THREAD) { |
57 | if (THREAD) { |
55 | THREAD->saved_pri = pri; |
58 | THREAD->saved_pri = pri; |
56 | THREAD->saved_epc = epc; |
59 | THREAD->saved_epc = epc; |
57 | } |
60 | } |
58 | /* decode exception number and process the exception */ |
61 | /* decode exception number and process the exception */ |
59 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
62 | switch (excno = (cp0_cause_read() >> 2) & 0x1f) { |
60 | case EXC_Int: |
63 | case EXC_Int: |
61 | interrupt(); |
64 | interrupt(); |
62 | break; |
65 | break; |
63 | case EXC_TLBL: |
66 | case EXC_TLBL: |
64 | case EXC_TLBS: |
67 | case EXC_TLBS: |
65 | tlb_invalid(); |
68 | tlb_invalid(); |
66 | break; |
69 | break; |
67 | case EXC_Mod: |
70 | case EXC_Mod: |
68 | panic("unhandled TLB Modification Exception\n"); |
71 | panic("unhandled TLB Modification Exception\n"); |
69 | break; |
72 | break; |
70 | case EXC_AdEL: |
73 | case EXC_AdEL: |
71 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
74 | panic("unhandled Address Error Exception - load or instruction fetch\n"); |
72 | break; |
75 | break; |
73 | case EXC_AdES: |
76 | case EXC_AdES: |
74 | panic("unhandled Address Error Exception - store\n"); |
77 | panic("unhandled Address Error Exception - store\n"); |
75 | break; |
78 | break; |
76 | case EXC_IBE: |
79 | case EXC_IBE: |
77 | panic("unhandled Bus Error Exception - fetch instruction\n"); |
80 | panic("unhandled Bus Error Exception - fetch instruction\n"); |
78 | break; |
81 | break; |
79 | case EXC_DBE: |
82 | case EXC_DBE: |
80 | panic("unhandled Bus Error Exception - data reference: load or store\n"); |
83 | panic("unhandled Bus Error Exception - data reference: load or store\n"); |
81 | break; |
84 | break; |
82 | case EXC_Bp: |
85 | case EXC_Bp: |
83 | /* it is necessary to not re-execute BREAK instruction after returning from Exception handler |
86 | /* it is necessary to not re-execute BREAK instruction after returning from Exception handler |
84 | (see page 138 in R4000 Manual for more information) */ |
87 | (see page 138 in R4000 Manual for more information) */ |
85 | epc_shift = 4; |
88 | epc_shift = 4; |
86 | break; |
89 | break; |
87 | case EXC_RI: |
90 | case EXC_RI: |
88 | panic("unhandled Reserved Instruction Exception\n"); |
91 | panic("unhandled Reserved Instruction Exception\n"); |
89 | break; |
92 | break; |
90 | case EXC_CpU: |
93 | case EXC_CpU: |
91 | panic("unhandled Coprocessor Unusable Exception\n"); |
94 | panic("unhandled Coprocessor Unusable Exception\n"); |
92 | break; |
95 | break; |
93 | case EXC_Ov: |
96 | case EXC_Ov: |
94 | panic("unhandled Arithmetic Overflow Exception\n"); |
97 | panic("unhandled Arithmetic Overflow Exception\n"); |
95 | break; |
98 | break; |
96 | case EXC_Tr: |
99 | case EXC_Tr: |
97 | panic("unhandled Trap Exception\n"); |
100 | panic("unhandled Trap Exception\n"); |
98 | break; |
101 | break; |
99 | case EXC_VCEI: |
102 | case EXC_VCEI: |
100 | panic("unhandled Virtual Coherency Exception - instruction\n"); |
103 | panic("unhandled Virtual Coherency Exception - instruction\n"); |
101 | break; |
104 | break; |
102 | case EXC_FPE: |
105 | case EXC_FPE: |
103 | panic("unhandled Floating-Point Exception\n"); |
106 | panic("unhandled Floating-Point Exception\n"); |
104 | break; |
107 | break; |
105 | case EXC_WATCH: |
108 | case EXC_WATCH: |
106 | panic("unhandled reference to WatchHi/WatchLo address\n"); |
109 | panic("unhandled reference to WatchHi/WatchLo address\n"); |
107 | break; |
110 | break; |
108 | case EXC_VCED: |
111 | case EXC_VCED: |
109 | panic("unhandled Virtual Coherency Exception - data\n"); |
112 | panic("unhandled Virtual Coherency Exception - data\n"); |
110 | break; |
113 | break; |
111 | default: |
114 | default: |
112 | panic("unhandled exception %d\n", excno); |
115 | panic("unhandled exception %d\n", excno); |
113 | } |
116 | } |
114 | 117 | ||
115 | if (THREAD) { |
118 | if (THREAD) { |
116 | pri = THREAD->saved_pri; |
119 | pri = THREAD->saved_pri; |
117 | epc = THREAD->saved_epc; |
120 | epc = THREAD->saved_epc; |
118 | } |
121 | } |
119 | 122 | ||
120 | cp0_epc_write(epc + epc_shift); |
123 | cp0_epc_write(epc + epc_shift); |
121 | cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit); |
124 | cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit); |
122 | cpu_priority_restore(pri); |
125 | cpu_priority_restore(pri); |
123 | } |
126 | } |
124 | 127 |