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1 | /* |
1 | /* |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
2 | * Copyright (C) 2003-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <arch/exception.h> |
29 | #include <arch/exception.h> |
30 | #include <arch/interrupt.h> |
30 | #include <arch/interrupt.h> |
31 | #include <panic.h> |
31 | #include <panic.h> |
32 | #include <arch/cp0.h> |
32 | #include <arch/cp0.h> |
33 | #include <arch/types.h> |
33 | #include <arch/types.h> |
34 | #include <arch.h> |
34 | #include <arch.h> |
35 | #include <debug.h> |
35 | #include <debug.h> |
36 | #include <proc/thread.h> |
36 | #include <proc/thread.h> |
37 | #include <symtab.h> |
37 | #include <symtab.h> |
38 | #include <print.h> |
38 | #include <print.h> |
39 | #include <interrupt.h> |
39 | #include <interrupt.h> |
40 | 40 | ||
41 | static char * exctable[] = { |
41 | static char * exctable[] = { |
42 | "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store", |
42 | "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store", |
43 | "Address Error - load/instr. fetch", |
43 | "Address Error - load/instr. fetch", |
44 | "Address Error - store", |
44 | "Address Error - store", |
45 | "Bus Error - fetch instruction", |
45 | "Bus Error - fetch instruction", |
46 | "Bus Error - data reference", |
46 | "Bus Error - data reference", |
47 | "Syscall", |
47 | "Syscall", |
48 | "BreakPoint", |
48 | "BreakPoint", |
49 | "Reserved Instruction", |
49 | "Reserved Instruction", |
50 | "Coprocessor Unusable", |
50 | "Coprocessor Unusable", |
51 | "Arithmetic Overflow", |
51 | "Arithmetic Overflow", |
52 | "Trap", |
52 | "Trap", |
53 | "Virtual Coherency - instruction", |
53 | "Virtual Coherency - instruction", |
54 | "Floating Point", |
54 | "Floating Point", |
55 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
55 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
56 | "WatchHi/WatchLo", /* 23 */ |
56 | "WatchHi/WatchLo", /* 23 */ |
57 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
57 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
58 | "Virtual Coherency - data", |
58 | "Virtual Coherency - data", |
59 | }; |
59 | }; |
60 | 60 | ||
61 | static void print_regdump(struct exception_regdump *pstate) |
61 | static void print_regdump(struct exception_regdump *pstate) |
62 | { |
62 | { |
63 | char *pcsymbol = ""; |
63 | char *pcsymbol = ""; |
64 | char *rasymbol = ""; |
64 | char *rasymbol = ""; |
65 | 65 | ||
66 | char *s = get_symtab_entry(pstate->epc); |
66 | char *s = get_symtab_entry(pstate->epc); |
67 | if (s) |
67 | if (s) |
68 | pcsymbol = s; |
68 | pcsymbol = s; |
69 | s = get_symtab_entry(pstate->ra); |
69 | s = get_symtab_entry(pstate->ra); |
70 | if (s) |
70 | if (s) |
71 | rasymbol = s; |
71 | rasymbol = s; |
72 | 72 | ||
73 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
73 | printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol, |
74 | pstate->ra,rasymbol); |
74 | pstate->ra,rasymbol); |
75 | } |
75 | } |
76 | 76 | ||
77 | static void unhandled_exception(int n, void *data) |
77 | static void unhandled_exception(int n, void *data) |
78 | { |
78 | { |
79 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
79 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
80 | 80 | ||
81 | print_regdump(pstate); |
81 | print_regdump(pstate); |
82 | panic("unhandled exception %s\n", exctable[n]); |
82 | panic("unhandled exception %s\n", exctable[n]); |
83 | } |
83 | } |
84 | 84 | ||
85 | static void breakpoint_exception(int n, void *data) |
85 | static void breakpoint_exception(int n, void *data) |
86 | { |
86 | { |
87 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
87 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
88 | /* it is necessary to not re-execute BREAK instruction after |
88 | /* it is necessary to not re-execute BREAK instruction after |
89 | returning from Exception handler |
89 | returning from Exception handler |
90 | (see page 138 in R4000 Manual for more information) */ |
90 | (see page 138 in R4000 Manual for more information) */ |
91 | pstate->epc += 4; |
91 | pstate->epc += 4; |
92 | } |
92 | } |
93 | 93 | ||
94 | static void tlbmod_exception(int n, void *data) |
94 | static void tlbmod_exception(int n, void *data) |
95 | { |
95 | { |
96 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
96 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
97 | tlb_modified(pstate); |
97 | tlb_modified(pstate); |
98 | } |
98 | } |
99 | 99 | ||
100 | static void tlbinv_exception(int n, void *data) |
100 | static void tlbinv_exception(int n, void *data) |
101 | { |
101 | { |
102 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
102 | struct exception_regdump *pstate = (struct exception_regdump *)data; |
103 | tlb_invalid(pstate); |
103 | tlb_invalid(pstate); |
104 | } |
104 | } |
105 | 105 | ||
106 | static void cpunsbl_exception(int n, void *data) |
106 | static void cpuns_exception(int n, void *data) |
107 | { |
107 | { |
108 | if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) |
108 | if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) |
109 | scheduler_fpu_lazy_request(); |
109 | scheduler_fpu_lazy_request(); |
110 | else |
110 | else |
111 | panic("unhandled Coprocessor Unusable Exception\n"); |
111 | panic("unhandled Coprocessor Unusable Exception\n"); |
112 | } |
112 | } |
113 | 113 | ||
114 | static void interrupt_exception(int n, void *pstate) |
114 | static void interrupt_exception(int n, void *pstate) |
115 | { |
115 | { |
116 | __u32 cause; |
116 | __u32 cause; |
117 | int i; |
117 | int i; |
118 | 118 | ||
119 | /* decode interrupt number and process the interrupt */ |
119 | /* decode interrupt number and process the interrupt */ |
120 | cause = (cp0_cause_read() >> 8) &0xff; |
120 | cause = (cp0_cause_read() >> 8) &0xff; |
121 | 121 | ||
122 | for (i = 0; i < 8; i++) |
122 | for (i = 0; i < 8; i++) |
123 | if (cause & (1 << i)) |
123 | if (cause & (1 << i)) |
124 | exc_dispatch(i+INT_OFFSET, pstate); |
124 | exc_dispatch(i+INT_OFFSET, pstate); |
125 | } |
125 | } |
126 | 126 | ||
127 | 127 | ||
128 | void exception(struct exception_regdump *pstate) |
128 | void exception(struct exception_regdump *pstate) |
129 | { |
129 | { |
130 | int cause; |
130 | int cause; |
131 | int excno; |
131 | int excno; |
132 | __u32 epc_shift = 0; |
132 | __u32 epc_shift = 0; |
133 | 133 | ||
134 | ASSERT(CPU != NULL); |
134 | ASSERT(CPU != NULL); |
135 | 135 | ||
136 | /* |
136 | /* |
137 | * NOTE ON OPERATION ORDERING |
137 | * NOTE ON OPERATION ORDERING |
138 | * |
138 | * |
139 | * On entry, interrupts_disable() must be called before |
139 | * On entry, interrupts_disable() must be called before |
140 | * exception bit is cleared. |
140 | * exception bit is cleared. |
141 | */ |
141 | */ |
142 | 142 | ||
143 | interrupts_disable(); |
143 | interrupts_disable(); |
144 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
144 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | |
145 | cp0_status_um_bit)); |
145 | cp0_status_um_bit)); |
146 | 146 | ||
147 | /* Save pstate so that the threads can access it */ |
147 | /* Save pstate so that the threads can access it */ |
148 | /* If THREAD->pstate is set, this is nested exception, |
148 | /* If THREAD->pstate is set, this is nested exception, |
149 | * do not rewrite it |
149 | * do not rewrite it |
150 | */ |
150 | */ |
151 | if (THREAD && !THREAD->pstate) |
151 | if (THREAD && !THREAD->pstate) |
152 | THREAD->pstate = pstate; |
152 | THREAD->pstate = pstate; |
153 | 153 | ||
154 | cause = cp0_cause_read(); |
154 | cause = cp0_cause_read(); |
155 | excno = cp0_cause_excno(cause); |
155 | excno = cp0_cause_excno(cause); |
156 | /* Dispatch exception */ |
156 | /* Dispatch exception */ |
157 | exc_dispatch(excno, pstate); |
157 | exc_dispatch(excno, pstate); |
158 | 158 | ||
159 | /* Set to NULL, so that we can still support nested |
159 | /* Set to NULL, so that we can still support nested |
160 | * exceptions |
160 | * exceptions |
161 | * TODO: We should probably set EXL bit before this command, |
161 | * TODO: We should probably set EXL bit before this command, |
162 | * nesting. On the other hand, if some exception occurs between |
162 | * nesting. On the other hand, if some exception occurs between |
163 | * here and ERET, it won't set anything on the pstate anyway. |
163 | * here and ERET, it won't set anything on the pstate anyway. |
164 | */ |
164 | */ |
165 | if (THREAD) |
165 | if (THREAD) |
166 | THREAD->pstate = NULL; |
166 | THREAD->pstate = NULL; |
167 | } |
167 | } |
168 | 168 | ||
169 | void exception_init(void) |
169 | void exception_init(void) |
170 | { |
170 | { |
171 | int i; |
171 | int i; |
172 | 172 | ||
173 | /* Clear exception table */ |
173 | /* Clear exception table */ |
174 | for (i=0;i < IVT_ITEMS; i++) |
174 | for (i=0;i < IVT_ITEMS; i++) |
175 | exc_register(i, "undef", unhandled_exception); |
175 | exc_register(i, "undef", unhandled_exception); |
176 | exc_register(EXC_Bp, "bkpoint", breakpoint_exception); |
176 | exc_register(EXC_Bp, "bkpoint", breakpoint_exception); |
177 | exc_register(EXC_Mod, "tlb_mod", tlbmod_exception); |
177 | exc_register(EXC_Mod, "tlb_mod", tlbmod_exception); |
178 | exc_register(EXC_TLBL, "tlbinvl", tlbinv_exception); |
178 | exc_register(EXC_TLBL, "tlbinvl", tlbinv_exception); |
179 | exc_register(EXC_TLBS, "tlbinvl", tlbinv_exception); |
179 | exc_register(EXC_TLBS, "tlbinvl", tlbinv_exception); |
180 | exc_register(EXC_Int, "interrupt", interrupt_exception); |
180 | exc_register(EXC_Int, "interrupt", interrupt_exception); |
181 | #ifdef CONFIG_FPU_LAZY |
181 | #ifdef CONFIG_FPU_LAZY |
182 | exc_register(EXC_CpU, "cpunus", cpun_exception); |
182 | exc_register(EXC_CpU, "cpunus", cpuns_exception); |
183 | #endif |
183 | #endif |
184 | } |
184 | } |
185 | 185 |